Title of Invention

"AN IMPROVED LOOK-UP TABLE"

Abstract The present invention relates to an improved Look-Up Table (LUT) including address decoder circuitry comprising means for utilizing said address decoder circuitry for producing secondary functions concurrently with the address decoding operations, thereby eliminating or reducing additional circuitry required for generating said secondary functions. This invention further includes a method.
Full Text Field of the invention:
The present invention relates to an Improved Look-up Table. More particularly, it provides concurrent logic operations using decoder circuitry of a look-up table
Background of the invention:
An FPGA consists of lookup tables, which can be programmed to implement different fimctions. Lookup tables, are used to implement functions of 'n' input, where 'n' depends on the Lookup Table size and the addressing scheme involved. The lookup table is most efficiently used when the number of inputs to the LUT are fiilly utilized and there are many minterms.
US Patent no. 6,037,829 describes a LUT decoder implementation.
The Xilinx programmable logic data book (Feb 16, 1999 Version 1.3, Page number 3-9) delineates the Virtex architecture with dedicated multiplier support by adding a two input AND gate at two of the four inputs of the lookup table or LUT 4 as shown in figure 1. This is a dedicated multiplier support and is particularly useful while designing large multipliers. It comes handy in many other applications also. The major flaw lies in the fact that a separate AND is fabricated with each LUT for achieving the AND gate fiinctionality. A lot of chip area is used up in fabricating these AND gates along with the LUTs.
The objects and summary of the invention:
The object of this invention is to obviate the above drawbacks by utilizing the decoder circuit gates of Look-Up Table for achieving the same functionality and thereby eliminating the need for an additional AND gate.
The second object of this invention is to reduce the additional circuitry required for generation of XOR/XNOR functions by employing a single NOR gate.
To achieve the said objectives this invention provides an improved lookup table comprising:
an address decoder for performing address decoding functions based upon a plurality of inputs;
said address decoder for also performing at least one secondary function concurrently with the address decoding fimctions also based upon the inputs.
At least one secondary fiinction comprises an AND function based upon two predetermined inputs.
At least one secondary function comprises an EXCLUSIVE-OR or EXCLUSFVE-NOR function; and wherein said address decoder comprises a NOR gate producing the EXCLUSIVE-OR or EXCLUSIVE-NOR fimction based upon predetermined inputs.
At least one secondary function comprises a sum-of-products/product-of-sums function; and wherein said address decoder comprises a programmable AND-NOR logic array producing the sum-of-products/product-of-sums function.
The said improved lookup table is implemented in a configurable logic element.
The said configurable logic element comprises a field programmable gate array.
The said configurable logic element comprises a complex programmable logic device.
The present invention also provides a method for performing address decoding and at least one secondary fimctions comprising:
using an address decoder for performing the address decoding functions based upon a plurality of inputs; and
using the address decoder for also performing the at least one secondary function concurrently with the address decoding functions also based upon the inputs.
At least one secondary function comprises an AND function based upon two predetermined inputs.
At least one secondary fimction comprises an EXCLUSIVE-OR or EXCLUSIVE-NOR function; and wherein the address decoder comprises a NOR gate producing the EXCLUSIVE-OR or EXCLUSIVE-NOR fimction based upon predetermined inputs.
At least one secondary function comprises a sum-of-products/product-of-sums fimction; and wherein the address decoder comprises a programmable AND-NOR logic array producing the sum-of-products/product-of-sums function.
The above method is implemented in a configurable logic element.
The configurable logic element comprises a field programmable gate array.
The configurable logic element comprises a complex programmable logic device.
Brief description of the drawings:
The invention will now be described with reference to the accompanying drawings:
Figure 1 shows the Look-Up Table (LUT) with two input AND gate in prior art.
Figures 2 & 3 illustrate decoder circuitries used with LUTs in conventional FPGA and CPLDs
Figure 4 shows an LUT with a primary Look-Up Table output and a secondary product term output.
Figure 5 shows simple gate fimctionalities like XOR and XNOR from decoder circuitry by employing a single NOR gate.
Figure 6 illustrates a more complex and flexible embodiment using the primary decoder gates as an AND plane along with a secondary NOR gate array plane for generating sum of product
terms.
Detailed description of the drawings:
An FPGA/CPLD consists of a plurality of Lookup tables and an address decoder associated with each of the lookup tables. The following description assumes a four input lookup table. A four input LUT or lookup table consists of four inputs labelled as A, B, C, D in figure 1. Two of the many possible circuits of the lookup table address decoders are illustrated in figures 2 & 3. The address decoder circuitry is shown partially, with the upper half not shown. Only the C & D inputs to the LUT are shown and all the description for the C & D inputs is equally valid for A & B inputs. The primary decoder for a four input lookup table in the present embodiments consists of eight NOR gates and eight AND gates as seen in figures 2 and 3, which partially delineate the structure. The outputs of these decoder gates drive pass transistors that connect between the lookup table latches and the output of the circuit structure. The primary decoder logic gates, if appropriately resized, may be exploited for generation of other functions, without the burden of any extra propagation delays.
Figures 2 & 3 delineate a convenient method of obtaining a dedicated product terra output fi-om the lookup table decoder logic gates. This output illustrated as CD product term in figures 2 & 3 is available at 7 & 10 by the inherent virtue of the decoder circuitry. Thus, the decoder circuitry obviates the need of a separate AND gate for product term fimctionality in figure 1. Figure 4 shows an LUT with a primary lookup table output and a secondary product term output.
Referring to figure 5, some of the other simple gate functionalities like XOR (11) and XNOR (12) are also possible fi-om the decoder circuitry by employing a single NOR gate. After appropriately resizing the decoder gates, one can tap the decoder gate outputs to generate other gate functions. A large number of such embodiments are possible as many more gates can be connected to the decoder gate outputs to generate complex functions.
Figure 6 illustrates a more complex and flexible embodiment which uses the primary decoder gates as an AND plane and a secondary NOR gate array plane for generating sum of product terms. The primary decoder/AND plane outputs, which fiirther drive the decoder pass transistors are labeled as 15. 14 depicts a configurable switch, which can either be a pass transistor or a buffer type. The switch arrangement shown in figure 6 is one of the many that are possible, and can be varied depending on the requirement. The sum-of-products / product-
of-sums output is available at the output of the secondary plane at 13 a, 13b, 13c, 13d. Also, any type or number of gates can constitute the secondary plane in other embodiments. The aforementioned structures give rise to FPGA architectures with the flexibilities of a looicup table and a programmable gate array with substantial saving in hardware resources.
Thus, it is clear that a decoder circuitry of a lookup table can be utilized for a broad range of fimction generation without disturbing the lookup table operation.





We claim:
1. An improved lookup table comprising:
an address decoder for performing address decoding functions based upon a plurality of inputs;
characterized in that
said address decoder for also performing at least one secondary function concurrently with the address decoding functions also based upon the inputs, thereby eliminating or reducing additional circuitry required for generating said secondary function.
2. An unproved lookup table as claimed in claim 1, wherein the at least one secondary function comprises an AND function based upon two predetermined inputs.
3. An improved lookup table as claimed in claim 1, wherein the at least one secondary fimction comprises an EXCLUSIVE-OR or EXCLUSIVE-NOR function; and wherein said address decoder comprises a NOR gate producing the EXCLUSIVE-OR or EXCLUSIVE-NOR function based upon predetermined inputs.
4. An improved lookup table as claimed in claim 1, wherein the at least one secondary function comprises a sum-of-products/product-of-sums function; and wherein said address decoder comprises a programmable AND-NOR logic array producing the sum-of-products/product-of-sums function.
5. An improved lookup table as claimed in claim 1, being implemented in a configurable logic element.
6. An improved lookup table as claimed in claim 1, wherein said configurable logic element comprises a field programmable gate array.
7. An improved lookup table as claimed in claim 5, wherein said configurable logic element comprises a complex programmable logic device.
8. A method for performing address decoding and at least one secondary functions by an improved lookup table as claimed in any of the preceding claims comprising:
using an address decoder for performing the address decoding functions based upon a plurality of inputs; and
using the address decoder for also performing the at least one secondary function concurrently with the address decoding functions also based upon the inputs.
9. An improved lookup table substantially as herein described with reference to and as
illustrated in the accompanying drawings.

Documents:

570-del-2001-abstract.pdf

570-del-2001-claims.pdf

570-del-2001-correspondence-others.pdf

570-del-2001-correspondence-po.pdf

570-DEL-2001-Description (Complete).pdf

570-del-2001-drawings.pdf

570-del-2001-form-1.pdf

570-del-2001-form-13.pdf

570-del-2001-form-18.pdf

570-del-2001-form-2.pdf

570-del-2001-form-3.pdf

570-del-2001-gpa.pdf

570-del-2001-pa.pdf


Patent Number 246910
Indian Patent Application Number 570/DEL/2001
PG Journal Number 12/2011
Publication Date 25-Mar-2011
Grant Date 21-Mar-2011
Date of Filing 14-May-2001
Name of Patentee ST Microelectronics Pvt. Ltd., an Indian company
Applicant Address PLOT NO.1, KNOWLEDGE PARK III, GREATER NODA-201308, UP, INDIA.
Inventors:
# Inventor's Name Inventor's Address
1 Ankur BAL KF-56 KAVI NAGAR, GHAZIABAD-201002, UP. INDIA.
PCT International Classification Number H03K 19/177
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA