Title of Invention

"A CMOS BUFFER WITH SIGNIFICANTLY IMPROVED GROUND BOUNCE REDUCTION"

Abstract The present invention provides a CMOS output buffer which makes use of feedback from ground node to reduce ground bounce by properly exploiting the tolerable ground bounce limit and making it less sensitive to operating conditions and processing parameters. Input to the NMOS of the output buffer comes from the output of a control element whose one input comes from predriver and the other (the feedback) comes from ground node.
Full Text Field of the invention:
The present invention relates to A CMOS buffer with significantly improved ground bounce reduction
Background of Invention:
In integrated circuits output buffers are used for the interfacing of the core logic with the external world. The prominent problem in output buffers is "ground bounce". The basic property of an inductor is that the change of current through it produces a voltage across it, which is directly proportional to the rate of change of current through it.
This can be given as
dV = LdI/dT Where
dV = Voltage generated L = Inductance dl/dT = Rate of change of current
Thus the voltage across the inductor bounces. We are considering this at ground pin thus we call it as ground bounce. Ground bounce occurs as a result of parasitic inductance of the integrated circuit and packaging interconnect. Ground bounce occurs when the pull down transistor switches from an off to an on state. Referring to FIG. 1, when the pull down transistor N116 is turned ON the potential developed across the capacitor C122 is coupled by the transistor N116 across inductor L120. As a consequence, a transient is generated across
uctor L120. A sudden increase of current flows from output terminal 112 through the pull-down transistor N116 and through the parasitic inductance LI20 to ground. Due to an inductors property, the voltage at the source of the pull down transistor rises. This decreases the gate-source voltage of the pull down transistor. In the case when this rise in source voltage is very large, it can cause ringing, which is reflected in the output of other buffers which are connected to the same ground pin and whose outputs were stable at low level. The worse case being when all the buffers, except one whose output is stable at low level, connected between the same supply pins switches from high to low and this may lead to false triggering if the groundbounce is not kept within limit. This posses a limit on the number of output buffers which can be connected to a single ground pin, thus increasing the number of ground pins of a chip.
Various techniques have been employed to reduce ground bounce. For instance, US patent no. 5,124,579 uses a resistive means for delaying the turn-on time of the output transistors in order to limit the rate of rise of ground current. This method suffers from availability to dynamically adjust to changing output conditions. Furthermore, the delays produced are manufacturing process dependent.
US patent no. 5,148,056 employs feedback taken from the output terminal of the buffer. This technique has poor sensitivity to the actual ground bounce especially when it is produced by the switching of other buffers.
US patent 5,60,453 relies on the matching of the geometric of various individual devices and does not employ any feedback. As a result, it is incapable of dynamically adjusting to changing output conditions. Mismatches arising out of process variations would also influence the effectiveness of this approach.
The object and summary of the invention:
The object of the present invention is to overcome the above drawbacks and to provide a CMOS buffer with significantly improved ground bounce reduction.
To achieve the said objective this invention provides a CMOS buffer with significantly improved ground bounce reduction, comprising: a ground terminal (GND),
feedback means (CE22) for sensing a ground bounce voltage at the ground terminal (GND), and
controller (CE11) having an input terminal connected to said feedback means, and output terminal connected to the gate of NMOS transistor of the output stage of CMOS buffer for dynamically adjusting a gate voltage thereof to limit the rate of increase of the ground current and includes means for dynamically adjusting a rate of increase of a ground current to reduce the sensed ground bounce voltage below a threshold while maintaining speed of operation of the CMOS buffer.
The said feedback means comprises an amplifier (CE22) for amplifying a difference between the sensed ground bounce voltage and an internal reference ground voltage.
The said controller comprises a slew-rate control circuit (CE11).
The said output stage is connected to said ground terminal and provides an output of the CMOS buffer (11), said output stage including a PMOS transistor (PI 1) connected together with the said NMOS transistor.
Description of The Drawings:
The invention will now be described with reference to the accompanying drawings.
Figure 1 shows a basic inverter with parasitic package inductances for explaining ground bounce
Figure 2 shows the circuit diagram for present invention.
Figure 3 shows a control element configuration, which can be used in Figure 2.
Figure 4 shows another control element configuration, which can be used in Figure 2.
Figure 5 shows a flowchart for describing circuit's operation.
Figure 6 shows a simplified diagram of the output buffer showing control circuit as block 101 according to the present invention.
Figure 7 shows a simplified diagram of output buffer along with control circuit shown in detail.
Figure 8 shows a voltage waveforms diagram showing the operation of circuit.
Detailed Description of the drawings:
Figure 1 has already been described under the heading background of the invention.
pure 2, shows a diagram, which contains three buffers output buffers, BUFFER11, BUFFER22 and BUFFER33, connected between common supplies VDD and GND through package inductances L218 and L220 on the VDD and GND pins respectively. The inputs to the buffers are INI 1, IN22 and IN33 respectively and the outputs are OP11, OP22 and OP33 respectively. Each buffer has it's input connection to it's pull-down transistor through a control element. These are CE11, CE22 and CE33 for the buffers BUFFER11, BUFFER22 and BUFFER33 respectively. FIG. 3 shows a configuration of control element (here only BUFFER11 is considered). IN 11 is coming to one end of the slew rate control element 305, while its other input 302 is coming from an amplifier 304 whose input 301 is coming as a feedback from L220. The voltage at net 301 varies dynamically according to groundbounce. This voltage is used to keep the bounce in control at a selected level. When the ground bounce at net 301 increases to a specific level it increases the slew of output signal on net 303 going to pull-down transistor Nil and when the groundbounce is not present the singal INI 1 passes through the control element CE11 without any changes and reaches the gate of pulldown transistor. FIG. 4 shows an another configuration of control element. The output 303 of control element CE11 is processed according to the given formula. Here K is a constant which depends on type of package and technology.
In FIG. 2 consider a steady state condition when input signal of BUFFER11 ( IN 11 ) is low, input signal of BUFFER22 ( IN22 ) is high and input signal of BUFFER33 (IN33 ) is also high. The pull-up transistor PI 1 is ON, P22 is OFF and P33 is OFF. The pull-down transistor Nl 1 is OFF, N22 is ON and N33 is ON. The output of control element CE11 is low, as at this moment there is no bounce at L220. This pulls up the node OP11 high and also charges the load connected to it. As the pull-down trans N22 and N33 are ON, OP22 and OP33 are pulled down and stable at low level. Now consider the case when the input
11 is switching from low to high state. During this switching as the bounce is produced in L220 it is fed back to the control element CE11. After the feedback has reached a particular selected level the control element CE11 circuitry controls the output going to pull-down transistor Nl 1 by increasing the slew of the signal on net 303, thus regulating the current through it, which decreases the ground bounce at L220. Due to this decrease in ground bounce feedback magnitude also decreases and the input to gate of Nl 1 rises faster (i.e. with decreased slew), which again increases groundbounce. This cycle is repeated until the voltage at INI 1 reaches it's high state. This can be very well understood by the flow-diagram shown in FIG. 5. The selected level of feedback (which is anyway low as compared to the maximum tolerable groundbounce) at which the control element circuitry becomes active is decided depending upon the delay of the control element circuitry. This scheme decreases the sensitivity of circuit to process parameters, different voltage and temperature corners because it mainly depends on the feedback from the package inductance. If process models are slow bounce at L220 will be low and the circuit will be faster and if the process models are fast, bounce at L220 will be more and the circuit will be slower, thus trying to neutralize the effect of process conditions on propagation delays.
Here circuitry is explained for reducing groundbounce. A similar circuitry can be used for controlling VDDBUMP, bounce at VDD pin inductance L218.
A more detailed embodiment of an output buffer and control circuit according to the present invention will now be described with reference to FIGS. 6-8. FIG. 6 illustrates a CMOS output buffer, including a pre-driver 102, a pad driver circuit 100, a control circuit 101 for controlling ground bounce and an AND gate Al. The output buffer also includes IO PAD 103. One input of Al is connected to configuration bit CB while other input is connected to NIN3 which
coming from pre driver 102. Output driver 100 includes PMOS P1 with it's drain connected to the output pad 103 and source connected to power supply VDD. Output driver 100 also includes NMOSs N1 and N2 with their drains connected to output pad 103 and their sources connected to C2. The NMOS transistors are sized in a binary-weighted sequence. C2 is connected to ground GND via parasitic inductor L1. PIN1 and NIN1 are coming from predriver 102 and connected to the gates of transistor P1 and Nl respectively. NIN3 is coming from predriver 102 which is connected to one of the inputs of AND gate Al. NIN2 is gate voltage for N2 coming from control circuit 101."
More specifically, the output buffer as shown in FIG. 7 includes pad driver 100, Pre-driver 102, control circuit 101, AND gate Al and pad 103. Control circuit 101 includes NMOSs N3, N4, N5 and inverter Gl. The source of N4 is connected to ground while it's drain is connected to NIN2. The gate of N4 is connected to line FB. The output of inverter Gl is connected to the gate of N3. The source of N3 is connected to NIN2 while it's drain is connected to line CC. Drain of N5 is connected to node C2. Gate of N5 is connected to VDD and its source is connected to line FB. The input of inverter Gl is connected to line FB while it's output is connected to the gate of N3. Feedback is taken from node C2 which is connected to line FB via N5. N5 is used to protect the gates of Gl and N4 from any occasional high voltage noise at C2. N5 will never allow a voltage greater than VDD-Vt(N5) to pass through it.
Vmtp is maximum tolerable peak voltage. This is the maximum amplitude of ground bounce pulse that can be tolerated for a particular pulse width. Vtrip(Gl) is the trip point voltage of inverter Gl. Depending on the current sinking capability required either Nl is conducting or both Nl and N2 are conducting. This is decided by configuration bit CB. It is presumed that for lower sinking
ability (CB=0) i.e when only Nl is conducting, ground bounce remains in acceptable limits. With CB=0 line CC remains at 0V.
With only Nl ON, voltage at node C2 is low enough (lower than Vtrip(Gl)) to keep the gate of N3 at logic 1. This keeps NIN2 at OV and hence N2 OFF. For higher sinking capability CB=1 Where both Nl and N2 are ON. In this case the current flowing through inductor LI is high which raises the voltage at C2 above tolerable limit. The control circuit 101 controls the voltage at C2 so that it always remains within tolerable limits. Considering a stable condition when output from pre driver 102 i.e NIN1, PIN1 and NIN3 are all 0V. With CB=1 and NIN3=0V line CC remains at 0V. NIN1 is 0V which makes Nl OFF. Node C2 and line FB remains at 0V. The input to Gl is 0V while its output which is connected to the gate of N3 is at VDD. This makes N3 ON and hence makes NIN2 OV. The gate of N4 is connected to 0V which makes N4 OFF. With PIN1=0V PI is ON, keeping PAD 103 at VDD. Now considering NIN1, PIN1 and NIN3 all makes a transition from logic low to high. This makes PI OFF. Sizing of Predriver is such that slew rate of voltage (dV/dt) at NIN3 is much faster than NIN1. Sinking is faster as the control circuitry never allows ground bounce to exceed Vmtp. Also sinking capability of Nl is such that if only Nl is ON ground bounce never exceeds beyond maximum tolerable value Vmtp.
Now voltage at NIN3 and NIN1 starts increasing. Increase in voltage at NIN1 turns ON Nl. At the same time the voltage at NIN3 also starts increasing and increases at a rate faster than NIN1. This makes line CC to go at logic 1. With N3 ON the voltage at line CC is transmitted to NIN2. This makes N2 ON. Now Nl and N2 both are ON to pull down PAD 103. This increases the current flowing through L1. Because of this voltage at C2 starts increasing the current flowing through inductor L1 is not constant therefore the voltage at point C2 is given by V(C2)=Ll[di(t)/dt] i(t) is the current flowing through L1.
Depending on the maximum tolerable peak voltage (Vmtp) at C2 the trip point of Gl is adjusted. The threshold voltage of N4 is less as compare to the trip point of Gl. As mentioned earlier Vmtp will be defined for a particular noise pulse width. The size of N4 is small in comparison to that of N3. As the voltage at C2 approaches threshold voltage of N4, it starts conducting. N4 tries to slow down the increase in voltage at NIN2. Now depending on the operating conditions and the type of models used two things can happen.
Firstly, under best operating conditions when both Nl and N2 starts conducting, the voltage at C2 starts increasing. The trip point of Gl is higher than that of threshold voltage of N4. Increase in the voltage at C2 first of all turns N4 ON. Now both N4 and N3 are ON. But the size of N4 is much smaller than that of N3. Conducting N4 slightly reduces the voltage slew rate (dv/dt) at NIN2. But still the slew rate is enough high and the voltage at C2 is still increasing. As the voltage at C2 reaches to the trip point of Gl, the output of Gl becomes zero which makes N3 OFF. With N3 OFF and N4 ON the magnitude of voltage at NIN2 starts decreasing. This will reduce the conductivity of N2 and hence the voltage at C2 also starts decreasing. Reduction in voltage at C2 again trips Gl which again turns ON N3 and voltage at NIN2 starts increasing. This will again increase current through inductor LI. If the voltage at C2 again exceeds the trip point of Gl, the above explained process is repeated again.
FIG. 8 shows the voltage waveforms at different nodes. NIN2 starts increasing from OV at time TO. As N2 becomes ON ground bounce starts increasing. At time Tl V(C2) crosses the threshold level of N4. This will reduce the slew rate of NIN2. Reduction in the slew rate of NIN2 can be seen from time Tl to T2. Even with the reduction in slew rate ground bounce (V(C2)) still increasing. At time (T2-dt) Gl trips and makes N3 OFF. At time T2 voltage at line NIN2
rts falling because of N4. This reduces the current flowing through L1 because of which voltage at node C2 starts decreasing. At time (T2+dt) G1 again trips making N3 ON. NIN2 doesn't start increasing instantaneously as N3 has some delay and also N4 is still conducting to stop NIN2 from increasing. At T3 NIN2 starts increasing which again results in increase in the ground bounce. But this time the magnitude of voltage at V(C2) remains well below Vtrip(Gl). The control circuit is working on feedback principle so it never allows ground bounce to cross Vmtp,
Secondly, under worst operating conditions magnitude of voltage at C2 is less than Vtrip(Gl). The output of Gl always remains VDD and hence N3 always remains ON. During slow operating conditions its N4 which slightly reduces the slew rate at NIN2. The above explained circuitry not only controls the ground bounce but it also tries to equalize delays under different operating conditions. Under fast operating conditions as the bounce approaches Vmtp, N3 becomes OFF which controls the bounce from further increase. With N3 OFF and N4 ON, the voltage at NIN2 actually starts falling as shown in FIG. 8. This reduces the current flowing through L1 because of which voltage at node C2 starts decreasing. This makes N4 less conducting. After a time 2dt N3 again turns ON but voltage at NIN2 starts increasing only after a delay of T3-(T2+dt) as shown in FIG. 8 whereas under slow operating conditions N3 is always ON and a slight reduction in the slew rate by N4 is sufficient to control the bounce. Thus in best operating conditions the bounce is controlled by actually decreasing the voltage at NIN2 whereas in worst operating conditions the bounce is controlled by slightly reducing the slew rate of voltage at NIN2."
Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood
A the invention is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.







We Claim:
1. A CMOS buffer with significantly improved ground bounce reduction,
comprising:
a ground terminal (GND),
feedback means (CE22) for sensing a ground bounce voltage at the
ground terminal (GND), and
controller (CE11) having an input terminal connected to said
feedback means, and output terminal connected to the gate of
NMOS transistor of the output stage of CMOS buffer for
dynamically adjusting a gate voltage thereof to limit the rate of
increase of the ground current and includes means for dynamically
adjusting a rate of increase of a ground current to reduce the sensed
ground bounce voltage below a threshold while maintaining speed
of operation of the CMOS buffer.
2. The CMOS buffer as claimed in claim 1 wherein said feedback means comprises an amplifier (CE22) for amplifying a difference between the sensed ground bounce voltage and an internal reference ground voltage.
3. The CMOS buffer as claimed in claim 1 wherein said controller comprises a slew-rate control circuit (CE11).
4. The CMOS buffer as claimed in claim 1 wherein said output stage is connected to said ground terminal and provides an output of the CMOS buffer (11), said output stage including a PMOS transistor (P11) connected together with the said NMOS transistor.
5. A CMOS buffer with significantly improved ground bounce reduction substantially as herein described with reference to and as illustrated in the accompanying drawings.

Documents:

804-del-2001-abstract.pdf

804-del-2001-claims.pdf

804-del-2001-complete specification (granted).pdf

804-del-2001-correspondence-others.pdf

804-del-2001-correspondence-po.pdf

804-del-2001-description (complete).pdf

804-del-2001-drawings.pdf

804-del-2001-form-1.pdf

804-del-2001-form-13.pdf

804-del-2001-form-18.pdf

804-del-2001-form-2.pdf

804-del-2001-form-3.pdf

804-del-2001-pa.pdf

804-del-2001-petition-137.pdf

804-del-2001-petition-138.pdf

abstract.jpg


Patent Number 246067
Indian Patent Application Number 804/DEL/2001
PG Journal Number 07/2011
Publication Date 18-Feb-2011
Grant Date 11-Feb-2011
Date of Filing 27-Jul-2001
Name of Patentee STMICROELECTRONICS LTD.
Applicant Address PLOT NO.2 & 3, SECTOR 16A, INSTITUTIONAL AREA, NOIDA-201 3001, UTTAR PRADESH, INDIA
Inventors:
# Inventor's Name Inventor's Address
1 RAJESH KAUSHIK H.NO: 600, URBAN ESTATE II, HISAR, HARYANA, INDIA
PCT International Classification Number H03K 17/16
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA