Title of Invention  A COMPLED BASEBAND ADAPTIVE DIGITAL NONLINEAR DEVICE AND METHOD THEREOF 

Abstract  A solution is disclosed for achieving a functional complex baseband adaptive digital nonlinear device model providing RFpower amplifier distortion (i.e. linearization or predistortion) minimizing distortion characterization including memory effects. The present inventive solution is based on real device nonlinear performance observations and the physical cause for the distortion is compensated in the application. This also means that a predistorter digital circuit is derived to have the inverse functionality of the digital device model. The model and the digital predistortion circuit are designed in such way, that function blocks are connected in cascade. Each function block is then designed to handle a certain type of distortion performance and can be optimized individually. The model gives possibilities to describe and evaluate different device properties. An accurate AM to AM and AM to PM characterization can be evaluated and the frequency response of the device when excited with envelope modulated signals can be evaluated. The properties evaluated can also be used in a test procedure in a production facility to verify production quality. 
Full Text  TECHNICAL FIELD The present invention relates to a method for achieving a functional Digital circuit to provide RFpower amplifier distortion minimization (i.e. linearization or predistortion) being based on a real device nonlinear performance observations and the physical cause for the distortion to be compensated. BACKGROUND OF THE INVENTION, Mobile communication systems, such as those used for cellular telephone communication, divide the spectrum into a multiplicity of individual signaling channels or frequency bands. Particular channels are allocated to individual users as they access the system. Each user's communication path is routed through the system through the channel allocated to that user. Signals broadcast by the system must be carefully regulated so that they remain within the channels allocated to the various users. Signals "out of band" can spill over from one channel to another, causing unacceptable interference with communications in the other channels. In order to increase the data transfer in such channels linear modulations like QAM, 8PSK and others containing amplitude modulation are utilized in contrary to older systems using constant amplitude phase or frequency modulation. The new 3G systems will need multicarrier amplifiers. Those new modulations require high linearity amplifiers and upconverters not to cause interference to other channels in the cellular system. Although combining of a plurality of carriers of any modulation into a single RFpower amplifier (MCPA) means that the amplifier will require very high demand on linearity in order to avoid spectral regrowth spreading RFpower into regions of the spectrum not appearing in the input signal. Normal RFpower linearization techniques are utilizing the known FeedForward, technique, (FF) and variants thereof. In order to improve the performance of the concept various attempts of improving the FF architecture by predistorting the signal to the main power amplifier are utilized. This is done to reduce the distortion in the main amplifier before applying the correcting signals in the feed forward loop thus achieving better efficiencies and less correcting needed in the FFloop. Examples of such patents are W097/37427, W099/23756, WO99/45640 and W099/45638 which shows a general increase of analogue complexity of generating the predistortion signals to the Main Power amplifier in a FeedForward Application or only using predistortion linearization of an RFamplifier without the feedforward loop for less demanding applications. With the semiconductor technology improving in both DSP and ADC and DAC techniques a strive has been taken of doing the predistortion in the digital domain instead of the analogue. Various patents on digital predistortion have been filed. First the digital predistortion patents were covering linear modulation single carrier amplifier improvements. References to be mentioned here are U.S. Patent No. 4,291,277, U.S. Patent No. 5,049,832 et al. Technical articles like James CarverIEEE Transactions on Vehicular technology, Vol. 39 No. 4, Nov 1990: "Amplifier Linearization using Digital Predistorter with fast adaptation and Low Memory requirements" and Andrew S. Wright and Willem Durtler, IEEE Transactions on Vehicular technology, Vol. 41, No. 4, Nov 1992:"Experimental Performance of an adaptive Digital Linearized Power Amplifier" gives good insight in the preceding history for the evolution of Digital Predistortion. In Figure 1 is illustrated a digital predistorter outline as described by Carvers et al. RFpower amplifier multicarrier power amplifiers (MCPA) require very high demand on linearity in order to avoid spectral regrowth spreading RFpower into regions of the spectrum not appearing in the input signal. In analogy with the known analogue feedforward technique, different patents of digital predistortion and postdistortion implementations are disclosed in for instance patent documents WO97/30521, WO98/51005, U.S. Patent No. 5,923,712 by Leyondecker and WQ98/12800. Figure 2 shows a basic outline for a digital predistortion (DPD) application applied to a wireless system. However, DPD can be applied to other systems needing digital linearization. The mentioned patents deals with the implementation of the so called digital real time circuit and then in smaller content with the calculation routines (algorithms) used in the DSP for updating lookup tables and other steering parameters. A practical design must take care of both the hardware and the software for the ease of the practical implementation. All mentioned patents relies on the basic structure illustrated in Figure 1 with some functional additions to handle and compensate for more than the basic gain and phase nonlinearity transfer function, that a real physical device has. The digital model for the nonlinear device like an amplifier (PA) must incorporate models containing more dimensions of data taking account for the so called "Memory effects". By integration of the input signal over a certain time a measure of the input signal Peak to Average signal level is made. This is then utilized to create tables describing the device performance dependence not only dependent of the actual input signal strength. The patent document W098/12800 from Spectrian describes one way of from measured amplifier performance by use of a so called "leaky integrator" get information of the moving average magnitude of the signal and from that create a function to describe the performance of the amplifier combined into one table. The Spectrian patent used the signal magnitude as input to the "leaky integrator", which is basically wrong as the claims are for power dependence. The "leaky integrator" shall work on the squared magnitude representing the signal power instead. The above mentioned patent as well as U.S. Patent No. 5,949,283 and U.S. Patent No. 5,959,500 are different implementations of how to create tables from observations of the amplifier output signal. The observations are used to create tables to predistorted input signals to the amplifier in order to improve the distortion at the output of the amplifier. By adding complexity in the predistorters the lookup table (LUT) dimension are often increased drastically. The patents also deals with the scenarios of using the created lookup tables to create signals to be used as a postdistortion that is subtracted from the main amplifier by another amplifier upconverter at the output of the main amplifier. This adds complexity to the solutions. The present invention only applies to the design of the digital parts needed to make distortion cancellation of a nonlinear device like a RFpower amplifier (PA) and the algorithms for achieving the results. The power amplifier is considered to be the nonlinear device for the rest of this paper. Different outlines and patents have been granted for this issue. Worth mentioning is the following. The results achieved in those patents are that very large multidimensional memory size is needed and the algorithms for calculating the needed memory contents are unclear. The available distortion cancellation in applying these patents are also unknown as the structures and algorithms does contaminate different PA performances of a real device like phase delay, power dependence and bias dependence in the same function blocks of the implemented digital block diagrams. U.S. Patent No.5,923,712 describes a method of tables containing extracted several weighting taps in some peculiar manner combining both power and magnitude samples with different delays to decide some average performance. The result is combined with direct inverse predistortion modeling. Figure 8 in U.S. 5,923,712 shows how complex the implementation becomes for a practical case if memory predictions are going to be used. Multidimensional tables are also implemented for power dependence predictions disclosed in other patents. The basic for all these patents are that the compensating gain calculations to be put into the LUT is done by a direct inverse division of the observed RFpower output signal and a time delayed (adjusted) input signal. There are a lot of special designed algorithms needed to be applicable to each particular patent for improving the basic failures from direct inverse calculations and the particular outlines used like signal noise sensitivity reduction and algorithm convergence. Thus there is still a need for an efficient method for providing RFpower amplifier distortion minimizing (i.e. linearization or predistortion). Therefore the present invention does not perform direct inverse calculations as outlined above and which will be explained in the description of the present new procedure. SUMMARY OF THE INVENTION The solution for achieving a functional Digital circuit to provide RFpower amplifier distortion minimizing (i.e. linearization or predistortion) must be and is in this invention based on real device nonlinear performance observations and the physical cause for the distortion is compensated in the application. This also means that a baseband digital model for a nonlinear device is extracted and the predistorter digital circuit is derived to have the inverse functionality of the digital device model. The model and the digital predistorter circuit are designed in such way, that function blocks are connected in cascade. Each function block is designed to handle a certain type of distortion performance and can be optimized individually In a first embodiment of the invention a nonlinear device modeling method results in a digital baseband representation of a device, with the capability of optimizing the model validity for each modeled characteristic of the nonlinear device used. The model gives possibilities to describe and evaluate different device properties. An accurate AM to AM and AM to PM characterization can be evaluated. The frequency response of the device when excited with envelopemodulated signals can be evaluated. The thermal time responses can be found. The properties evaluated can be used in a test procedure in a production facility to verify production quality. Device thermal mounting failures can be evaluated as one example. In a second embodiment of the invention the digital predistorter function blocks according to the present invention are built as the inverse functionality of the real PA device performance based on real device characterizations. The digital functionality is designed as functional blocks aligned in cascade for the signal to pass through. The blocks are designed in such a way that different function blocks can each be assigned to different performance descriptions of a real power amplifier. Depending on performance demand the functional blocks can be enabled or disabled. The algorithms for calculating the block parameters are based on modern signal processing techniques for DSP application. The basic digital circuit solution is scalable in functions. This means that for moderate demands a smaller part of the blocks can be used and a smaller part of the algorithms calculated in the Digital Signal Processor (DSP). Multidimensional memory LUT is not needed in any function block. The solution according to the present invention also makes it possible to correct for the introduced group delay errors within the signal bandwidth that prior art solutions for digital predistortion application will not be able to correct for. According to a third embodiment of the invention, for the ease of DSP implementation and reducing the memory need for the programs only a few basic reusable algorithms are needed for calculation and updating the different function blocks of the new digital predistorter or for calculation of a nonlinear device digital model characteristics. These algorithms are used both for signal time alignments, memory effect calculations and LUT table update calculations. According to still a fourth embodiment of the invention, with new modern digital signal processing algorithms applied to the DPD circuit disclosed, the basic digital function block as outlined in figure 1, and in prior art regarded as a "Memoryless digital predistorter" can be made to function as a "Digital PreDistorter with Memory Compensation". A method according to the present invention is set forth by the independent claim 1 and the dependent claims 27 and a baseband adaptive digital predistorter circuit according to the invention is set forth by the independent claim 8 and further embodiments are defined by the dependent claims 8 to 16. SHORT DESCRIPTION OF THE DRAWINGS The invention, together with further objects and advantages thereof, may best be understood by making reference to the following description taken together with the accompanying drawings, in which: FIG. 1 illustrates a basic AM to AM and AM to PM predistorter block. (Prior Art); FIG. 2 illustrates a Digital Predistortion application (Prior art); FIG. 3 is an evaluation schematic for PAmodel characterization; FIG. 4a shows power amplifier with a bias supply circuit; FIG. 4b shows a digital model representation with a FIRfilter and arrangement for multiplying the input signal by the Complex Gain Table LUT; FIG. 5a shows the basic complex gain adjustment block of the new digital predistorter; FIG. 5b illustrates that the new digital predistorter is an inverse function of the derived digital PA model in Figure 4b; FIG. 6a illustrates a measured input signal spectrum for spectrum performance of the derived PAmodel; FIG. 6b shows the spectrum performance of the derived PAmodel with no predistortion applied, FIG. 6c shows the spectrum performance of a prior art direct inverse gain predistorter achieved after 5 adaptations of the LUT; FIG. 6d shows the improved spectrum performance of a predistorter according to the present invention also after 5 adaptations of the LUT; FIG. 7a illustrates magnitude gain data base and inverted phase gain data base for first adaptation of prior art direct inverse gain calculation DPD solutions; FIG. 7b illustrates magnitude gain data base and inverted phase gain data base for fifth adaptation of prior art direct inverse gain calculation DPD solutions; FIG. 7c shows the content of the LUT table for magnitude gain and phase gain after 5 adaptations of prior art direct inverse gain calculation DPD solutions; FIG. 8a shows the same Magnitude and Phase gain data's plotted in the same scale as in Figure 7a for the first adaptation for calculating the PAmodel + DPD performance, according to the present invention, using the FIRequalization algorithm described earlier in this invention in the digital signal processor; FIG. 8b shows the same data's after the fifth adaptation according to the present this invention indicating a remarkable reduction of the data area for gain calculations and adaptation is seen; FIG 8c shows the inverted amplitude and phase gain table contents put into the predistorter LUT after the fifth adaptation according to the present invention; FIG. 9 illustrates the new proposed digital model function blocks for further reduction of the error vector between the digital PAmodel and the PAmeasured performance; FIG. 10 illustrates the digital model differential complex gain dependence function block; FIG. 11a shows the achieved results from consecutive optimizations of the first PAmodel "Gain/Phase" dependence block; FIG. lib shows the same result when the "Differential Gain" dependence block is added to the digital device model; FIG. lie shows the differential gain magnitude and the differential gain phase in radians versus input signal magnitude; FIG. 12 illustrates a plot of the input signal differential power and the Model Magnitude errors versus the measured power amplifier; FIG. 13a shows differential input power cross correlation versus the magnitude errors of the model and the actual device; FIG. 13b shows corrected magnitude errors and the original magnitude errors between the model and the measured device; FIG. 14 shows the Digital Model with power dependence function block; FIG. 15a illustrates comparison of the digital model spectrum errors versus the actual device with differential gain compensation added to the basic gain/phase dependence block; FIG. 15b shows comparison of the digital model spectrum errors versus the actual device with further addition of the power dependence function block correction; FIG. 16a illustrates the enhanced digital model function blocks; FIG. 16b shows error spectrum performance between the digital model and the measured device and the measured PA spectrum performance; FIG. 16c illustrates the flow chart for model calculations for the result shown in Figure 16b and the enhanced digital model blocks are numerically designated "Block 1" to "Block3" according to Figure 16a; FIG. 16d illustrates the detailed calculations in "Block 1" of Figure 16c; FIG. 16e illustrates the detailed calculations in "Block 2" of Figure 16c; FIG. 16f illustrates the detailed calculation in "Block 3" of Figure 16c; FIG. 17a illustrates a basic predistorter system according to the present invention; FIG. 17b shows the flow chart for using the basic predistorter system; FIG. 18 shows the Gain/Phasor Multiplier block; FIG. 19 shows the gain/phase predistortion function block; FIG. 20 shows the differential complex gain predistortion block; FIG. 21 shows the predistortion blocks needed for DPD application; and FIG. 22 illustrates the digital predistorter according to the present invention applied to a combined DPD and Feed Forward MCPA application. DETAILED DESCRIPTION OF THE INVENTION In order to define a well functioning digital predistorter, the performance of the nonlinear device named (PA) must be known. Therefore the PA performance must be known by measurements and a digital baseband PA model described as function of the real vector I and the imaginary vector Q samples of the input digital signal designed accordingly. Model characterization is done by down loading of a defined range of samples in time of the input signal and an equal range of samples of the digital measurements of a real Power Amplifier or other nonlinear device. The signal errors between the digital model and the actual measurement of the real device signals are normally estimated as the performance that a digital predistortion application can achieve, if it is designed according to the modeled device. To explain this invention for a person normally skilled in the art the first part of the invention describes in detail the derivation of a cascade of function block in the PAmodel feasible for digital baseband representation of a real PA, based on the understanding of the physical cause for different nonlinear distortions emerging from a real circuit. The algorithms applied are based on modern digital signal processing techniques and not on internally invented optimization routines in order to get the prior art digital predistorters to work. The examples in this derivation is done by showing measurements using a commercial test setup and a company power amplifier capable of delivering more than 300W peak power. Next the proposed digital predistortion circuit is outlined as the inverse function of the PAmodel with the complete functionality applied. Performance simulations are shown of a minimum predistorter simulation according to the fourth embodiment of this invention in order to show the performance improvement, which the inventive improvement makes possible compared to prior art digital predistorters mentioned in referenced patents based on direct inverse gain calculation algorithms compared to the algorithms used in this new invention. PA Digital Model Derivation. The distortion of a PA can be regarded to emerge from different factors and can be assigned to different phenomena. I) AM to AM and AM to PM nonlinearity from the used device II) Linear Memory Effects emerging from time and phase delays in the actual circuit matching networks and the bias supply and the device. This can be considered as the envelope response of the device. III) Nonlinear Memory effects of the device such as input power and temperature dependence and the input signal dependency of changes in device voltages. The first type of distortion is normally handled by the Inverse Gain compensation as for the memoryless DPD described in prior art. The second category, the Linear Memory effect is missed, when prior art predistorters use the direct inverse gain calculations by dividing the input signal with the measured signal. The prior art patents show different ways of trying to describe these phenomena. A way to handle and describe the second type of phenomena will be shown in the performance evaluation described below when describing a sample simulation of a PA + DPD performance difference between this invention and prior art techniques according to the fourth embodiment of this invention. The third category of memory effects is the most difficult one to describe, but the approach in this invention gives possibilities to characterize this behavior and apply predistortion solutions for signal power dependence and further improvements like power supply clipping if needed. Power Amplifier Measurement Techniques. A person normally skilled in the art will realize that the performance of the total system for digital predistortion application relies very much on the actual design of the measurement device. In Figure 2, which describes a typical DPD application, the measurement device is the downconverter and the ADC. The closed loop system achieved by using digital adaptation will also compensate for the inaccuracies in the measurement device if the measurement device is uncalibrated. Figure 3 is an outline for measurements intended for nonlinear device characterization and digital model evaluation. Commercial available signal generators and Vector Signal analyzers can be used. The signal generator creates the modulated test signal. With this test procedure the same measurement errors are present both in the input signal tested by using the "through line" and by testing the "Power Amplifier and Attenuator" performance by using the same stimuli signal from the signal generator. The complex signals are sampled and provided to a data collection unit. The output and input signals are then exported to a processor for analysis and PAmodel evaluation. The basic structure illustrated in Figure 2 can also be changed to this type of measurement system by introducing the same type of switches into the outline. In the present invention disclosure the measurements shown are done on a 1carrier WCDMA signal as the input signal, due to the bandwidth limitation of commercial equipment. However, several types of amplifiers have been tested. Evaluations of the measurements showed that he method according to the invention was applicable to all of the devices measured. There were differences shown in both type 2 and type 3 performances of the tested devices. The higher output power capability of the tested device, the more of input signal actual power dependence was shown. Gain Model For The PA Representation. Figures 4a and 4b are the basis for deriving the model representation in the present invention. In Figure 4a the bias supply circuit of a device is also shown. There are some decoupling capacitors of the bias supply lines and there are resistive losses in cables and circuit board lines to the device. This means that the device is not driven by an ideal voltage source, but more likely by a voltage source with nonzero resistance followed by a lowpass filter. This means that there is some delay introduced in the device current when the input signal changes in magnitude. Also the device itself has a step response that introduces a delay. Although a normal gain versus frequency response measurement on a network analyzer shows very flat gain response on a device, the nonlinear device response for a digitally modulated input signal with envelope variation will be bandwidth limited. The first obvious thing is then to describe the introduced delays for a real PA hardware by adding a Lowpass filter to the digital baseband model of the PA, taking care of the introduced phase delays. The low pass filter is implemented as a FIRfilter or other type of digital filter. Only a few taps of this filter are needed, as the main purpose is to describe an average approximated delay of the PA signal. This delay is the main contributor to different sideband levels at the high side and the low side of the output distortion, when measuring a practical PA with a spectrum analyzer. Due to the delay, the high frequency side distortion is always higher than at the low frequency side. The new PAmodel for digital baseband is shown in Figure 4b. This model representation gives possibilities to describe the bias supply low pass influences in the model and also other delays. PA Model FIRFilter Calculation. To characterize the filter used in the model, the equalizer filter algorithms and methods known from digital receiver technologies are used. The FIR filter is referred to as HO in Figure 4b in this description. Looking at Figure 4b, the input signal multiplied by the Complex Gain Table LUT weight results in a signal denoted SinGC, which is used for a comparison with the measured PA output signal. The filter Tap Coefficients are found by solving the convolution equation with time aligned signals with the PA output signal on time sample basis. Then the equations of the filter convolution: Sin_GC H0 = Vout is solved for the HO tap values. Normally the input signal in the discrete time convolution SinGC is written as a matrix and HO and Vout as vectors, and the HO FIR tap values are solved by matrix mathematics. The achieved HO FIRfilter gain at zero frequency is adjusted equal to 1 in order not to change the magnitude gain of the model affecting the LUT absolute gain values. When few taps are used in the H0filter, the so named "Equalizer FIRfilter", the matrix equation acts as a least square approximation of the solution. The filter taps are defined from more equations than needed. The equalization thus also gives noise suppression in the signals as the result. The actual equalizer filter algorithm used here is designed in such way that the filter group delay is centered at the midtap of the FIRfilter and an odd number of taps are used to achieve sample time aligning. A number of 3 or 5 taps in the filter will normally work very well in a normal application, although there is no limitation in a practical implementation. Then a convolution of the input signal SinGC with the derived FIRfilter is calculated in the processor and the resulting signal is used for the complex gain calculations by comparing with the measured PA output signal. The FIRfilter application gives an accurate weighting for calculation of a complex gain table LUT for device characterization. This calculated complex gain LUT can be used in a digital predistorter application if the inverted gain values for the complex gain are applied in a LUTmemory. The implementation of an equalizer FIRfilter algorithm gives far better result in weighting of the data for calculations than the prior art direct signal samplings and inverse gain implementations by division of the signals described for instance in patent WO98/51047. The inventors realized that there are some delay associated with a real nonlinear device that a predistorter has to compensate for and tried to add more time delayed sampling of signals into the DPD block structures. A linear interpolation approximation used in prior art by sampling at two times or more gives only minor improvements and normally results in multidimensional table LUT memories as seen in mentioned patents by Leyondecker et al. Using the direct inverse gain evaluation in prior art without filter equalization of the signals used for inverse complex gain table calculations will mean that the digital adaptation of updating the LUT tables will converge to non optimum result. The result is that the output signal after digital predistortion shows unequal side band level suppression of the distortion in Prior art implementations. Prior art can only work on special PAdesigns with very low memory effects. Using the equalization filter also reduces the noise in the data's used for calculating the LUT table values. Some shortcomings of prior art solutions are shown below in this description. Basic Digital PreDistorter (DPD) For Gain And Phase Distortion Reduction In this chapter the algorithms and methods for applying the derived digital PAmodel in Figure 4 used in an inverse manner as a DPD will be explained. A sample simulation in the end of this chapter will show the differences between the prior art solutions and the solution disclosed in the present invention. Application Description In such an application as illustrated in Figure 5a for a simple gain/phase adjustment predistorter the difference in the outline from prior art shown in Figure 1 is the introduced inverse FIRfilter (H01) shown in Figure 5b. Figure 5b shows that the digital predistorter is an inverse function of the derived digital PAmodel in Figure 4b. The FIRfilter (HO1) in the predistorter is the inverse filter of the earlier mentioned HO filter describing a device response to an envelope modulation. The predistorter gain table LUT has the inverse complex gain of the device. There are differences in the approach in this invention compared to the prior art. By calculation for each iteration the equalized complex gain of the complete predistorter and PA and then adapt the inverted complex gain values to the predistorter for each adaptation an improved performance of such a simple predistorter is achieved. The main difference is the use of the HO FIR weighing of the data for complex gain calculation. Figure 5b shows the new digital predistorter in front of the derived digital device model for gain phase description of an actual device. From the figure is it observed that the predistortion circuit is designed as the direct inverse model of the PA digital model according to Figure 4b. Figure 5b can be used in a simulation environment. By disabling the inverse filter compensation HO1 the predistorter has the same outline as in prior art illustrated in Figure 1. Contrary to PAmodel evaluation, which adjusts the Vin signal to resemble the signal V0ut and where Vin is applied to the PAmodel input port, the procedure is to do an inverse PA modeling by adjusting the Vin signal by the predistorter to make the Vout signal to resemble or equal to the Vin signal. When calculating the total gain for the combined Predistorter and PAmodel filter in the DPD calculations, the resulting gain is updated inversely into the predistorter LUT. A comparison with the prior art procedures is then available by disabling the HO PAmodel filter in the calculations in the simulation as the HO1 filter and in this way show the performance differences between the new technique and the prior art technique. The disabling of the FIRfilter HO in the gain calculations is the same as doing direct inverse modeling i.e. no weighting of the LUT table values are done before the calculation. This evaluation is done in a later chapter and the results are shown. The Time Alignment Algorithm Description To be able to calculate the gain tables etc for a digital predistorter as in Figure 5b, the calculations must be done on sampled input and output complex I/Qsignal vectors. The signal vectors are loaded into the DSP and the exact time delay between the signals in sample times are calculated by cross correlation of the complex signal vectors or the magnitude of the signal vectors as in prior art descriptions based on modern signal processing methods. For accuracy reasons even further time alignment must be done on subsample basis in order to extract a correct values for updating the gain LUT's. This is very important especially for getting prior art predistorters to work. Prior art uses sometimes algorithms based on sub samples of the sampling time (7) and adjusts the signals timing to a value t+T/N, where N is an integer value. For this invention only a phase adjustment to one of the signals is utilized. New Signal Phase Adjustment Method For correct function of a Predistorter the observed signal and the input signal I/Q diagrams must be adjusted and aligned to a better accuracy than the sample time alignment. This means that there is a ±180 degree phase adjustment that can be done to the observed signals, when the exact timing in sample times is found. This procedure can be done by use of complex number multiplication correction to each sample of one of the signals. This invention only needs a phase alignment on sample basis of the used signals for comparison. The new approach in this invention is to reuse the FIRfilter equalization algorithm by adjusting the complex input and measured signals by doing 1tap FIRfilter equalization using the input signal as input to the algorithm and the measured signal as result vector in the algorithm. If this 1Tap filter tap value is A+jB, the time aligned input signal to the DSP can be multiplied by a complex "phasor" calculated as (A+jB)/ abs(A+jB) for each time sample of the vector or using the conjugate "phasor" value (AjB)/abs(AjB) for multiplying the measured signal depending on the application. In the same manner as explained in the previous chapter the advantage is, that the error between the signals at the zero frequency will be the least square approximation. The prior art methods must rely on further sub sample optimization of the time difference between the signals. This problem is taken care of in this invention by using the 1tap FIRfiltering techniques described earlier. Matrix Algorithm For Calculating LUT Memory. One way of calculating the LUT memory values is by using a matrix for the calculations. The calculations for the prior art LUT is shown as an example. Values for each sample of the input and measured signals are evaluated for the inverse gain. The magnitude [Rin) of the input signal is sorted into digital binsizes Rin(Bin). Normally the bin size is 1/127 or 1/255 of the maximum allowed input signal amplitude. This corresponds to (27)l and (28)l, which is practical when the DSP processor calculates in the base of 2. The first column of the matrix will contain values of the magnitude of the input signal expressed in bin sizes Rin[Bin(t)] and contain as many rows as the sampled signal size in time samples. The second column contains the corresponding time sample magnitude of the observed sampled device signal inverse gain defined as below. The third column of the matrix will contain the corresponding phase of the observed sampled device signal. This will give a matrix suitable for calculating LUT tables. The Inverted Complex Gain is calculated in prior art as: Inv_CG(R(t))=Vin(t+ )/Vout(t) for each of the time aligned samples, is the number of sample clock time delays used for optimum crosscorrelation evaluation. Further time alignment can also used for the signal Vin(t+) and is normally also performed on sub sample basis. After that the matrix is sorted for values size of column 1, i.e. the input magnitude expressed as bin values in an increasing order. This means that the rows of the matrix are changed. After that a sub matrix is extracted corresponding to each bin of Rin. expressed as the input signal magnitude bin value. The average value for the Magnitude and Phase of the corresponding Inv_CG(R(Bin)) is then calculated. For each calculation done the predistorter LUT is updated according to: Mag[lnvCG(New)]=Mag[lnvCG(Old)]+a*Mag[lnvCG(Calc)1)) Phase[Inv_CG(New)]=Phase[Inv_CG(Old)]+ß*(Phase[Inv_CG(Calc)]) Where α and ß are the predistorter adaptation feedback factor values for updating the LUT for each calculation or adaptation. The adaptation feedback factor values is normally in the range 0 to It shall also be mentioned that algorithms for removing the empty Bins, i. e. submatrix's containing no values from the calculations, shall be used and the table values gets smoother if the calculation is using some type of smoothing or regression of the final calculated Inverse Complex Gain LUTresult. The basic problem with predistortion is to predict the performance of a nonlinear device and compensate for it. This is always done in such a way that the average performance is calculated. Therefore the average values are calculated in the digital signal processor (DSP). The New LUT Updating Algorithm Description. The digital predistortion (DPD) application in figure 5a is based on the PAmodel. The Predistorter shall be the inverse of the PAmodel function, the inverse of the HO filter is situated before the predistorter complex gain block driven by the predistorter LUTmemory content. The usage of the inverse HOfilter is only for frequency dependence and phase correction of the output signal for canceling of the group delay residues in the linearized output signal from the predistorted device. This is not possible with the mentioned prior art patents. If group delay compensation is utilized the filter shall give the opposite phase delay compared to the PAmodel HO calculated filter. The inverse HOfilter must be used in further extensions of the new invented predistorter blocks described later in this invention disclosure. In a simple DPD application as in Figure 1, the PAmodel HO is only used virtually in the DSP calculations for achieving a correct convergence of the predistorter LUTmemory. The change in the algorithms for the new invention will be explained below. In calculating the DPD gain table LUT, the convolution of the signal Sin with the calculated HO filter is used by solving Sin HO = Vout. The filter magnitude gain of HO at zero frequency is adjusted equal to 1. The resulting signal from the convolution of Sin and the gain normalized HO is named SinHO. After that this signal is time adjusted again with the measured PAsignal due to the introduced FIRfilter digital delay in samples of sampling time (7). The magnitude of that signal (SinHO) is sorted into magnitude bins Rin[Bin(t)] and the complex gain expression for the PA and the predistorter is calculated. An error vector EV is calculated as EV=VoutSinHO for each sample. V0ut is the measured performance of the combined digital predistorter, upconverter, PA and downconverter in figure 1. As mentioned before the downconverter and ADC must be very accurate in a real design. The modification and derivation of the gain expression is done as below for each sample of time: (Remember that the DCgain of SinHO is the same as for Sin). Vout(t)=SinHO(t)+ EV(t) The complex gain expression can be written as a vector V0ut/SinHO=l + EV/SinH0, where the rows is corresponding to the sampling time t Arranging this expression for ease in DSPimplementation gives the Complex Gain expressed as below by multiplying both the nominator and the denominator with the conjugate of the input signal (remembering that a complex vector multiplied by its conjugate value is the magnitude squared): For each time sample of the signals the following expression is evaluated: CG= 1 +[ EV*SinHO(conjugate) ]/[ mag(SinH0) ]2 where mag(SinH0)=Rin. As Rin(t) squared is the input signal power the complex gain can also be made as dependent on the input signal power. But in this invention the input signal magnitude is used and shown. The result from the evaluation is put into a row of a matrix having one row for each sample time instant of the signals. A matrix row will contain the following column contents. Rin(Bin(t)], mag(CG(t)] and phase[CG(t)] and contain as many rows as the total number of samples used in the DSP from the Sin and V0ut signals after time adjustments and FIRfiltering. The same matrix algorithm calculations for solving the earlier described inverse complex gain LUT's of prior art is used. Update of the combined [DPD and PA gain], giving the accumulated and adopted Complex Gain Table virtually present in the DSP as a function of the input signal magnitude values in Bins is done. Then the updated PA_DPD magnitude gain table is inverted by 1/X division The PA Phase Gain table is multiplied by a factor 1. The new inverted table values are inserted as new values in the Predistorter LUT, will thus be the inverted complex gain. LUT content: Inv_CG(Bin)=l/CG(Bin) The adaptation is done in the following way. When the predistorter is initiated the virtual PAgain table situated in the DSP is filled by complex values according to a Magnitude gain of "1" and a Phase gain of "0" and the predistorter will have the same values as start in the LUT. The reverse HO filter is filled by zeros for all tapvalues except the middle tap, which is loaded by a unity value. For this simulation when comparison to prior art the predistorter inverse H0FIRfilter is not updated. This means that this inverse HO FIRfilter is disabled in Figure 5b. But the HO filter method is used in the DSP calculations for achieving the improved performances of this new invention. Each DSP calculation gives a new correction (adaptation) added to the PAmodel complex gain table virtually situated in the DSP according to: Phase (GC(bin))=Phase(GC(bin))_old +a*(Phase(GC(bin)_calculated) Then the Virtual table is read and the Inverse Complex Gain is calculated and loaded into the Digital PreDistorter LUT memory according to the adaptation procedures as before. The new way of calculating the complex gain table and the algorithms used gives possibilities to improve the prior art Memoryless DPD application into a DPDsystem, that covers memory effects emerging from time and phase delays in the actual real nonlinear device due to the FIRfilter equalization algorithm method used for weighting the frequency response of the data for the LUT calculations. Higher values of a and the ß predistorter adaptation feedback factors can be used and still a good convergence can be achieved with this new DPD application. This allows for faster convergence of the predistorter. Performance Evaluation of the new gain/phase predistortion applied in a DPD solution Verification of the new algorithms described in this invention is done by simulation. The aim has been to compare the basic prior art direct inverse gain calculation algorithms according to a Figure 1 block, with the algorithms applied for the new digital predistorter according to Figure 5 discussed in connection to the present invention, applied to an amplifier, that does not behave as in an "ideal" amplifier without time and phase delays in the envelope modulation response. A basic simulation of digital predistortion performance was done. For the simulation the Digital Power Amplifier model according to Figure 4b, derived from the PAmodel work, was used as the active device in the simulation. The BaseBand digital PAmodel used was derived from measurements. The model was implemented with FIRfilters for achieving a model with memory effects emerging from time delays and frequency response from envelope modulations. Simulation results. Figure 6b shows the spectrum performance of the derived PAmodel with no predistortion applied and using the input signal shown in Figure 6a. The signals have been filtered to approximately 30 kHz resolution bandwidth in the spectrum display. The amplifier has due to the memory effects unsymmetrical distortion spectrum. Figure 6c shows the spectrum performance after five updates of the LUT by using settings according to the prior art direct inverse gain calculations. Figure 6d gives the improved spectrum performance also after five updates of the LUT based on the new predistorter according to the present invention where the FIRfilter weighting algorithm was used for the gain calculations. For both the prior art and the new method improvement after five updates was not noticeable. In Figure 7a is shown the magnitude and phase of the inverse gain used for achieving the average calculation for prior art predistorters for the initial first adaptation calculation of this type of predistorter. Figure 7b shows the same data after the fifth adaptation according to prior art. Only a minor tendency, of the database area shrinking during adaptation, is observed. Further, Figure 7c shows the content of the LUT table after five adaptations in prior art. The LUT table still contains a lot of ripple in the prior art procedures and this is the explanation for all the peculiar mathematical algorithms patented for prior art applications in order to reduce the LUT value ripples normally blamed on noisy input data's. Figure 8a shows the same Magnitude and Phase gain data's plotted in the same scale as in Figure 7 for the first adaptation for calculating the PAmodel + DPD performance using the FIRequalization algorithm described earlier in this invention in the digital signal processor. Figure 8b shows the same data's after Five adaptations for this invention. A remarkable reduction of the data area for gain calculations and adaptation is seen. Figure 8c shows the inverted gain table contents put into the predistorter LUT after five adaptations. Figures 6, 7 and 8 shows the enhanced performance of applying the algorithms disclosed in this invention to a simple DPD outline. The equalization FIRfilter algorithm solves many problems like noise suppression and helps to reduce the data spread for calculating the average values used in a predistorter lookup table memory. No noise was added to the basic simulations shown. The results are in accordance with the fourth embodiment if this invention. The basic conclusion from the simulation was that the prior art predistorters based on direct inverse gain calculations, are not able to converge to an optimized solution. Prior art solutions are not able to achieve equal sideband levels of the distortion on a real PA with time delay in the actual response as no consideration of the frequency response of the actual device can be made. Prior art patents mentioned in this disclosure tries to improve the basic problem of direct inverse gain calculations by implementing own invented additions and approximations to the basic DPD outline based on Figure 1. It will be shown later in this invention that the application of the inverse H01 filter in the "Gain/Phase" predistortion block, that minimizes the group delay differences between the input signal and the device output signal, will give possibilities to investigate the cause and adjust more of the remaining distortions that a complex gain table LUT DPD function block not can handle. The PAModel With Added Functional Dependence Block Description. The derived PAmodel shown in Figure 4b can be improved to handle more than the first and the partly second type of distortion. This is possible because the new model method reduces the error vector between the model and the device measured so more detailed performance differences between the model and the actual device is revealed after each step. This is not possible when only a distortion reduction is achieved without error vector minimizing as in prior art. The functionality enhancement is done by cascade connections of further digital PAmodel functions blocks. Figure 9 shows the new proposed digital model function blocks for further reduction of the error vector between the digital PAmodel and the PAmeasured performance. The figure shows the already described "Gain/Phase dependence block" followed by the "Differential Dependence Block" and the "Power Dependence block". The approach is to compensate for any systematic remaining errors and having in mind that the function blocks shall be related to the real device physical cause of the systematic errors. The function blocks in the digital model in this invention have the availability to be individually optimized for the model performance in a consecutive and adaptive way. The Differential Complex Gain Dependence Block. Looking at Figure 4a there is a time constant () shown in the power amplifier symbol representing the intrinsic device turn on delay for input signal change which is believed to be much smaller than the sampling time used in the predistorter or the measurement sampling clock time. The influence from this behavior is described by looking at the first time derivative of the PAmodeled signal and the measured signal. The basic idea is to reuse the algorithms from the first block and design a "Differential Complex Gain" table depending on the derivative versus time of the input signal and calculate a differential gain influence in the function block referred to as the "Differential Complex Gain" dependence block (dCG). The Differential Complex Gain Dependence Block Derivation. The mathematics for the "Differential Complex Gain" block design is presented below. The modeled signal after the "Gain/Phase Gain" block gives the averaged performance characterization of the first gain block in the PAmodel and is here named as Vavg(t). The measured signal is named as V0ut(t). Those signals can be written also as a function of the first derivative versus time (samples of sampling time T). (Equation Removed) where dV0ut(t+T)=Vout(t+T)Vout(t) and all are complex numbers (Equation Removed) The goal is for the digital PAmodel to have as small errors as possible. Therefore the demand on the above equations are that Vout(t+T) equals Vavg(t+T). Putting this into the above equations and solving for dV0ut(t+T) gives: (Equation Removed) A new average model error vector EVavg after the gain and phase block is identified and defined as: (Equation Removed) Solving for the differential complex gain expression defined as: (Equation Removed) gives: (Equation Removed) From equation (4) it is also realized that the EVavg(t) has a corresponding Vavg(t) value and also a magnitude R of Vavg(t) input signal to this block associated. Therefore the differential complex gain dCG(t+T) values has a dependence of the preceding sample input signal magnitude.{R(t)). A similar digital function block as for the first gain block in the digital PAmodel can be designed. It is also possible to design a function block depending on the dVavg(t+T). The output signal after this block is modified in the following way: (Equation Removed) Where dCG(Rbin) is the differential complex gain value calculated from equation (5) in the same manner as described for the first "Gain and Phase Gain" dependence block and put into a differential complex gain LUT memory. Adaptations of the differential complex gain block LUT can be done as in the previous block and a performance measure can be evaluated by comparing the maximum adaptation value to a present limit. Figure 10 shows the "Differential Complex Gain" dependence block digital functionality, where the delays (DO, Dl, D2) in sample times T are accordingly designed for time alignment within the function block to satisfy equation (6). The same gain matrix calculation routines can be applied to this block as the previous Gain/Phase block to calculate a differential gain LUT depending on the input signal amplitude (R) to the block. Figure 11a shows the achieved results from consecutive optimizations of the first PAmodel "Gain/Phase" dependence block. Figure l1b then shows the same result when the "Differential Gain" dependence block is added to the digital device model. Both graphs in Figures 11a and l1b show the measured PAoutput spectrum and the error vector spectrum between the Device and the modeled performance. Figure l1c shows the database for calculation and optimization of the differential gain LUT table dCG(Rbin) for the device. The result from the modeling shows that the differential gain modeling takes care of the fine gain/phase errors within the signal bandwidth and further reduces the error spectrum between the model and the measured device. The Power Dependence Block. The PAmodel derived so far still has residues of distortion left. An investigation of the remaining error vector shows magnitude errors but essentially very low phase shifts. The magnitude errors are considered to be the influence associated by the input power to the PA. To investigate this, the remaining signal amplitude errors between the measured PA magnitude (RouL.Measured) and the PAmodel (R_Modet\ are evaluated for further investigations. Rerr(t)=Rout.Measured(t) R_Model(t), the magnitude error vector versus time. Plotting the vector Rerr versus sampling time "t and [R_Model(t)]2, which is the Power P(t) in the modeled PAsignal, shows that there are some memory effects emerging from the input signal power to the PA still left to be modeled. The approach and thinking in this invention is different from prior art methods. The basic idea is by looking of what have so far been done in the PAmodeling function blocks. The "average" PAmodel performance is derived from an input signal. This input signal also has an average power versus time. Therefore the performance for power dependence built into the model must then depend on the power levels where the average power corresponds to the average power of the input signal. A model that most correct describes the Power dependence of the real Power Amplifier must then be based on the "difference from the average power of the signal used for the modeling work". The average power of the input signal to this power block is calculated and denoted PM. A new difference power vector is designed as: dP(t)=P(t)PM Figure 12 shows the differential power dP(t) (dashed curve) plotted together with the remaining amplitude errors Rerr(t) (solid curve) between the digital model and the actual PAmeasurement in order to get a view of how the dependence looks like. From the figure a conclusion is drawn that there is some correlation a few samples after the dP(t) plot versus the Rerr(t). To have closer look at the dependence of the differential power dP(t) versus the remaining magnitude errors Rerr(t), a crosscorrelation evaluation common in signal processing theory is done. Figure 13a shows the crosscorrelation result is plotted as a function of different sample time differences in time samples (7) between the signals used. Looking at Figure 13a, a person skilled in the art draws the conclusion, that the crosscorrelation result basically shows the combined impulse response from combined low pass filters with different time constants, gain and bandwidth. In a PAmodel power compensation block function aiming to achieve low distortion sidebands, the highest response that also have the most bandwidth (short impulse response) is considered to the best job of suppressing the distortion outside the carrier from the power influence. The correction solution for the next block is then to add a filtered differential power influence correction to the magnitude of the so far modeled signal. The "Power Filter" may be designed with symmetrical taps from the crosscorrelation evaluation as having the cross correlation values from the zero cross correlation timing up to the maximum value defining the center FIRfilter tap of the impulse response. When half of the impulse response is chosen the rest of the response is achieved by mirroring the tap values from the center to the end of the FIRfilter. The number of taps is then set to be an odd number and the FIR filter is symmetrical around the center tap. This reduces the numerical calculations in the power correction block to be defined. Another simpler approach implemented in the simulation is to design the filter as a standard signal processing windowfunction filter. The crosscorrelation is evaluated in time response from the first positive going zerocrossing to the max value as above. The number of taps is decided as 2 times+1 of the time difference in samples. A "Hanning" window function is used for the differential Power FIRfilter in this invention description. Other common window function filters or low pass FIRfilters can also be used. A filter function with more taps and unsymmetrical tap values more resembling the crosscorrelation evaluation results can also be used, but this will mean a filter containing more taps and introducing more processing efforts For evaluation of all the parameters to be designed into this power correction block, a convolution of the differential power vector dP(t) with the chosen differential Power FIRfilter is used to achieve a differential moving average power vector as the new result named dPma(t). This new vector is then again crosscorrelated versus the Rerr(t) vector to define the optimum time delay td in time samples for doing the power influence correction in the model. The power FIRfilter gain factor GP for optimum compensation gain is calculated by reusing the 1tap FIR equalizing DSP routine, used before in this invention description, once more on the signals resulting in dPma(t+td)*GP equal to Rerr(t) m the least square optimization manner. The achieved factor value GP is the optimum moving average difference power correlation to the magnitude error Rerrft) signal. The power correction to the digital model signal is done as (Equation Removed) where 8 is a small number for preventing overflow in the calculations. In the expression the investigated power dependence of the magnitude error is converted to a gain expression affecting the magnitude of the signal to describe the power dependence. This is possible as the previous block evaluations result in an error mainly in magnitude but not in phase between the signals. Figure 13b shows the power corrected magnitude error vector (1) and the magnitude error vector without power correction compared to the device measured signal (2) plotted versus the input signal magnitude Rin to the power dependence block compared with the device measured signal. Figure 14 shows the derived power dependence block digital outline. The shown time delays are adjusted according to the digital implementation so the expression Sin_Model_Power_Correct(t) is satisfied. The blocks so far achieved in the digital model was shown in Figure 9. Further refinement of the model is available at the choice of the user. This model works very well as each individual function has the availability to optimize the performance for each individual characteristic of a real device as long as the characteristic is based on some physical dependence that can be described. As the error between the digital baseband model and the measured PA performance is reduced for each implementation of a function block there is also possibilities to apply the methods described above to achieve even further reduction of the model errors. Devices showing errors depending on the input signal magnitude can be evaluated in the same way as for power dependence by providing differential magnitude correlation versus the remaining errors between the model and the measured device as an example. Figure 15 shows the achieved spectrum improvement of the Error Vector between the modeled performance compared to the measured PAperformance. The enhancement in the digital model with differential power predistortion correction applied versus the no powercorrected model is shown Figure 15a shows comparison of the digital model spectrum errors versus the actual device with dependence correction the results model results after differential complex gain dependence model from Figure 11 is repeated In Figure 15b the results after the Power dependence model corrections are shown. Both figures show the spectrum performance of the measured PAdevice and the corresponding error vector spectrum versus the digitally modeled device. The resulting error vectors are normally regarded to be the result how good a predistortion can be applied and how it works on the actual device. The achieved error vector for the power corrected model shall be compared to the used input signal spectrum shown in Figure 11a for a simple AM to AM and AM to PM digital model. By comparing Figure 15 to previous figures of spectrum and error plots of the derived digital model the conclusion is that each block contributes to the accuracy of the model as expected when it is based on physical dependence of a device. Figure 15 shows how far the modeling work can be performed on relative poor measurement equipment based on 12bit ADC and DAC built in to the commercial equipment. This PAmodel can also be used for simulation purposes in a predistorter environment for optimizing the predistorter system performance and implementation, which is done in this invention. For instance no considerations to the introduced errors in the sampling clock synchronization between the commercial instruments are done. The noise from the downconverter and the local oscillator present in the test equipment is also present in the model calculations presented in this invention disclosure. Improved Modeling of The Digital PA Model. Looking at Figure 13b there is seen a curvature in the power corrected magnitude error that is remaining. The errors are not following the center zero line on yaxis. This means that there is some gain errors remaining in the model so far done. To include this in the digital model a rearrangement of the model blocks shown in Figure 9 is done. The power correction is done prior to the Complex gain/phase block. This means that the gain LUT reading in this block will be corrected for the power influence before the signal magnitude is selected as address in the gain LUT. The correction is done with the same formulas as for post correction described before. With this method multidimensional LUT memory is not needed. Figure 16a shows the rearrangement of the digital device model blocks with the power correction dependence block used as the first block in the Digital Device Model blocks. By evaluation a device calculating a model the Power correction block is first disabled and the two following blocks are evaluated for best agreement of the model. Then the power dependence block data base needed is evaluated and the data is loaded with the same values as for the post correction to the precorrection block and the gain/phase block and the differential complex gain block is evaluated again. Figure 16b shows the spectrum performance achieved by this model evaluation. An improvement is seen of the digital model accuracy to the measured PAperformance by comparing the plots to Figure 15b. The difference in the error vector spectrum on the high and the low side of the signal is caused by the simplification of the power dependence FIR used a Hanning window filter, where the time delay can not be corrected exactly to the delay of the power dependence without doing more over sampled signals. This means that the measurement setup shall have higher sampling clock rate. Improvement of the result can be made by use of the crosscorrelation function values as the power FIR approximation described earlier instead. Comparison with the input signal spectrum in Figure 6a shows that the modeling errors comes very close to the spectrum limits of the measured input signal. The remaining errors are also highest within the input signal bandwidth as the power dependence correction was chosen to work mainly for the side band suppression errors. It shall also be mentioned that the possibility of performing a less accurate power dependence evaluation is possible by disabling the differential gain block evaluations. Figures 16c to 16f illustrates the principal flow diagrams for the digital model calculations according to Figure 16a. Digital Signal PreDistorter Based On Nonlinear Device modeling. With the preceding chapters describing the digital PAmodel in mind the derivation of a new digital predistorter is obvious according to the first embodiment of this invention. In the section in pages 17 to 25 the application of the inverse PA complex gain model was shown to work as a very efficient digital predistorter for complex gain distortion cancellation. By applying the same concept for all blocks of the derived PAmodel a new digital predistortion circuit is proposed. Figure 17 shows the proposed digital predistortion circuit. The invention describes four basic blocks named 1, 2, 3 and 4. The first function block 1 is the hardware digital implementation of the predistorter. It is the real time digital circuit with all function blocks 101 to 106 shown. The second block 2 is the Digital signal processor used for updating the different parameters and lookup tables used in the predistorter. The different software blocks 201 to 206 are shown. The third block 3 shown is the Control word used for controlling the system, which contains data accessible for all the other blocks shown in the picture for read and write. It can be placed in the digital HW block 1 but is shown as a separate block for the sake of clarity. The fourth block 4 is the External System Control to monitor the system present status and updating it. The external control can decide if there is a calibration procedure to be done or an operation where some of the blocks in the basic predistorter are disabled or not by overwriting the content in the control word 3. It can be used for SW updates, signal down load etc from the DSP 2. Basic Calibration And Initialization For calibration purposes a known signal with approximately the same power as intended in the highest power case application shall be used. A basic calibration run of the system is performed to fill the tables and parameters with default data according to the active device used. The average power and the peak power in the input signal used for the power correction evaluation shall be in the range of the intended usage of the system to ease the calibration and application afterwards. When calibrating and initializing the system a basic routine is utilized. The digital real time circuit blocks for Power dependence 103 and the differential gain block 104 are disabled. This means that the signal goes through these blocks unaffected. The EVFIR block 102 is loaded with zeros for all tap values except the middle tap, which is loaded with the value of "1". This is described in detail in the descriptions of the individual blocks later in this paper. The Gain/Phase predistortion block 105 is loaded with LUT tables corresponding to a gain of 1 and phase angle of zero. The FIRfilters are loaded with center taps equal to one and the rest of the taps are zeroed. The External DSP and Predistortercontrol block 4 initiates a digital word 5 to be read by the digital predistorter 1 telling the circuit to start and to use the calibration data base stored in memories inside the block 1. The parameter block for each function has three memory locations 0, 1 and 2 as an example. The first is for the initialization and is denoted the "0"block. The DSP, which is monitoring the control word 3 starts to download signals SI and VM from the memory in 106 and starts processing the data. When the DSP 2 has done calculations according to software blocks 202 and 203 and is ready for updating, it reads the control word 5 defining the database usage and decides where to put the updated data's. If the control word has a "0" for this position the DSP loads the new data's into a memory position called "1". When the loading is ready the DSP overwrites the "0" in the contol word 3 data base pointer with a " 1" telling the digital real time circuit 1 that it shall start using the new database. If the DSP already reads a "1" in the digital control word, the DSP decides to put the new updates into a position "2" and change the control word database pointer accordingly. If the DSP reads a "2" memory position it toggles back and puts the new data's in "1"position and updates the control word 5 database pointer. Time Phase And Gain Adjustment A defined number of samples from the input signal SI and the output signal VM is loaded down to the DSP. The DSP routine 201 calculates the time difference in samples and the correct phasor to be used as the correction of the Gain Table LUT and stores it for updating later. The DSP stores the time difference delay (ts) to reduce calculation time for further updates later. The DSP can also do a correction of the gain of the input signal in block 101. If too high level of the input signal is applied to the system the DSP reports to the control word 3 that reports further to the external control 4 that can adjust some external attenuators. The control word 3 can also have the possibility to do external adjustments by itself with added interfaces and DSP functionality. The calculation of the timing and phase correction is done the same way as described in the section in pages 17  25. The control block 3 can be loaded with a "gain back off factor to be used in the system to cope with the analog device gain change versus temperature and put an appropriate margin to the input signal so the signal levels inside the system never exceeds a maximum allowed value. The phase difference between the VM and the SI signals can be incorporated into the inverse FIRfilter tap values by multiplying each complex by the correction phase value for a first adaptation. The inverse FIRfilter incorporated in 105 will adapt and correct for the slow drift in the upconverter and PA group delay and frequency response drifts. The gain setting shall be done in such a way that the predistorter 1 has the availability to adjust the tables within the input signal range so slow predistorter adaptation can be made due to the ambient temperature change of the used nonlinear device. Some type of digital signal gain back off is used and adjusted in the AGA block 101. The ambient temperature is supposed to be corrected by the adaptation of the predistorter. The gain backoff adjustment can also be adopted for calibrated transfer drifts in the hard ware setup  upconverters and downconverters the nonlinear PA. Gain /Phase Predistortion Block. The updating of gain table LUT's and FIRfilter Tap memories of the gain and phase equalization block 105 is calculated in the DSP block 203 in accordance to the description above. Each calculation means an update of the LUT and FIRfilter memories used in the predistorter 105. A measure of the performance described in later chapters is reported to the predistorter control 3, that updates the enabling functions in the digital control word 5 for operating the system with more functions applied. When all functions of the Gain/phase equalizer blocks have adopted to a certain performance measurement factor, the DSP according to the control word reading goes further to calculate the next block according to the settings of the control word 3. The Differential Gain Predistortion Block. The procedures of calculating this block 204 and updating of the digital part 104 can be done in two different ways depending on the DSP processor calculation power capability. First it can be calculated by the same procedure as for the differential gain according to the magnitude and phase database shown in Figure lie. The updating is then done as the inverse complex gain values into the LUT A second more fast way but less accurate than the first approach is to use linear regression of the data put into the LUTtables. Application of this procedure is dependent on the nonlinear device performance. When the DSP has done the calculation it updates the respective memory positions in 1 and writes the respective update to the Control Word 5. Adaptation of the differential gain predistortion block is done in the same manner as for the complex gain/phase block before proceeding to the next block. The Power correction evaluation block. The system goes further to calculate the differential power dependence according to the DSP block 205. There are two choices of how to do this and the procedures. The first method is that it is done automatically. The DSP calculates all of the procedures by proper programming of the DSP. The DSP can be controlled to do an update of the power dependence periodically afterwards if the ambient temperature will affect this performance. This was outlined in the section "The Power Dependence Block" starting in page 30. How often the dependence adaptation must be done is unclear as there is no data available. The experience by applying the DPD solution according to the present invention will give more insight to this question in the future. Adaptation of the power FIR gain factor will probably be most feasible. The second method is that the DSP and predistorter control reads the control word and loads appropriate S2 and VM signals to the external control where the Power dependence FIRfilter is evaluated in another processor controlled by a human interface doing the calculations and evaluations. This is possible if the power dependence of a device is not expected to change and then it can be evaluated just once. There will probably be a failure in the actual device if the temperature dependence starts to change in the applied nonlinear device. By doing the power dependence outside the system, a lot of memory location for program is saved in the DSPblock 205 in Figure 16. After the evaluation of the differential power dependence is done, the new data's for the FIRfilter, the delay and the weighting according to a previous chapter are loaded into the memory of the Power dependence Predistortion block 103 and the control word 3 is updated so the predistorter 1 starts to use this function. If a Proper adjustment of the mean power value PM for the differential Power correction block and the time delay is done, the result is symmetrical side band suppression in the predistorter. EV FIR application. In some applications of the proposed DPD circuit, the error vector between the input signal and the output signal has to cancel a very low level of errors between the digital input signal and the measured output signal taking account for the upconverter frequency characteristics as the influences from the blocks 103 and 104. The FIRfilters in the Gain/phase predistortion block will adapt to an input signal that is modified with the power and differential gain predistortion applied. The use of the EV__FIR 102 is applied to correct the group delay and frequency response versus the true input signal to the system. The calculations is the same as for the later described Inverse HO calculations used in block 105 but with the input signal S1used instead of the S2 signal together with the measured signal VM in Figure 17a. For wider frequency coverage of the EV_FIR performance than the intended input signal bandwidth, the signal S1 in this case can be a wider frequency signal but with less power level to the PA and thus reducing the distortion from the active device that may effect the calculation and results from the EV_FIR tap evaluations. Even better is to use a phase modulated signal with no amplitude modulation present. Utilizing the System. After the calibration is done the system is ready for use. The setting of the last control word 3 defines the data base for operation for the individual blocks. The calibrating data has been stored in nondestructive memory media. The system loads the data's into the DSP 2 and the predistorter 1 and starts running. The DSP calculates and updates the three basic blocks 101, 103 and 104 according to the control word 5 settings described already. The initial DSP control evaluation parameters are monitored by the DSP and predistorter control which checks the validity of the monitored parameters and put an alarm to the external control 3 if the validity limits are overdriven. As the performance of the predistorter dependency is relying of all DPD functions applied, multiple block adaptations may cause variations in the DPD application spectrum response instead of refining the spectrum for each adaptation. The predistorter gain/phase correction block shall have the highest priority for adaptation for each DSP evaluation, while the other function blocks can be updated when the gain/phase predistortion block agrees with the performance limit set. Basic outline of the Predistorter blocks. A sample outline of the four proposed predistortion blocks is made in this chapter. Basic for all blocks are that they have the inverse correction applied as compared to the PAmodel blocks described in this paper. The difference between this outline of the new predistortion proposal is, that the introduced group delay of the prior art predistorters will be cancelled giving very small error vectors emerging from the DPDsystem used in the received signal for a wireless system receiver to handle. For the second embodiment, it shall also be noted that the proposed digital predistorter system can be modified and used as part of the MCPA system using a feed forward loop. The algorithm description in this invention is defined in a way that is operating on Error Vectors in the function blocks Therefore it is possible to achieve error cancellation in an added feed forward loop application to the basic digital predistorter application outlined in Figure 22. The same algorithms can be used on a system that measures the error vector in a canceling point in a FFsystem. The new invented predistorter also makes group delay cancellation and thus reduces the error signal to be used in a second loop Error Amplifier in a Feed Forward solution. Phasor Multiplier. The multiplier in Figure 18 is a complex number A+jB with the magnitude equal to "1", which is multiplied with each of the complex input signal samples to provide a phase corrected output signal. This phasor is used to make a perfect fit in rotation of the I/Qdiagrams of the used signals VM and S2 in Figure 17. The complex number used in the memory is provided from the DSP 2 in Figure 17. The LUT tables in 105 in Figure 16 can be updated with the inverse complex gain multiplied with the phasor adjustment and thus reducing the hardware need. No external phasor block is then needed. The adaptive updating of the phasor is done by taking the last phasor value and multiply it with the new calculated value found by 1Tap FIRfilter equalizing technique described before for device modeling. Gain/phase equalization Predistortion Block. The gain and phase equalization block for the final solution in Figure 19 is changed somewhat compared to Figure 5a. The earlier mentioned inverse HO FIRfilter is divided into two filters HC1 and HC2, which are used for coarse and fine correction adjustment of the time and phase performance equalization or group delay cancellation. For the first optimization or adaptation run the filters with equal odd number of taps are loaded with zero tap values except for the middle tap which is loaded with a "1". For the first initial runs the updating is not done. When the adaptation has reduced the distortion so a more linear response is achieved, the basic linear FIRfilter algorithm will give accurate response for group delay cancellation purposes using the FIRfilters HC1 and HC2. The optimization and adaptation of the predistorter inverse gain and phase goes on until a measure of performance of the used HO in the algorithms described before is achieved. Normally the performance of the predistorter can be measured by evaluating the power of the error vector, but a much more efficient evaluation is described here. The measure of the optimization process is done by evaluating the improvement of the FIRfiltering, not on the gain tables in the following described way. When the calculated HO tap values is stabilized in the adaptation it means that the predistorter works correctly. The PAmodel algorithm HO filter Tap values from previous and the present adaptation for complex gain calculations are measured. The magnitude of the squared sum of difference Tap vector will be made. This measure here called "HCl_CanceV is compared to a limit value "HCl_Cancel_Limit' in the DSP. As soon as the "HCl_Cancer is less than the limit, the DSP starts the update the HC1 FIRfilter coefficients and uses the last HC1 filter that gave the limit satisfaction above. The following FIRfilter adaptations of the predistorter 2 block 105 in Figure 17 will be done by updates of the second fine tuned FIRfilter HC2. Both complex valued filters are magnitude gain adjusted to have a gain equal to "1" at zero frequency in order not to affect the used gain tables. The inverse HO filter is designed by FIRfilter equalization described before reversing the signals S2 and VM in Figure 17 in the algorithm described for device modeling discussed in the section "Gain Model For The PA Representation" in page 14 and onwards. The two FIRfilters HCl and HC2 are feasible, because using only the first FIRfilter HCl may give oscillations in the adaptation when the time delays of the actual device is exceeding the actual time sampling by some fraction of the clock time. The filter HCl preserves the correct time sampling phase adjustment so the second FIRfilter HC2 is centered in the FIR Tap response. The second FIRfilter HC2 refines the predistortion result and adapts for the slow changes in the system. When the FIRfilter HCl is used, the following adaptations will adapt the values of filter HC2 in the following manner. From the previous FIRfilter HC2, the complex FFT is calculated. The new FIRfilter HC2 complex FFT is also calculated. This goes very fast when only a few taps are used. The two FFT's are multiplied and the inverse complex FFT is done of the result. This new FIRfilter is stored as update in the system of the filter HC2. The number of taps of the filter HC2 is preserved by this method. Direct convolution of the previous and the last FIRfilter HC2 will increase the number of taps. The two filters in cascade will give a flat frequency response of the system response, canceling the nonlinear device response as the upconverters. For the reduction of the number of complex taps in the predistorter, the two filters HCl and HC2 can be calculated in the DSP by convolution to provide updating of a single filter HCtot still having the desired frequency response for optimal error cancellation. Each adaptation or calculation in the DSP will give updated LUT and filter taps in the predistorter. Updating of the Predistortion Control Word 5 in Figure 16 is also done. There are also possibilities to use one compensation FIRfilter HCtot in the application and update this filter in the same way as described for the filter HC2. The basic difference for the new predistorter disclosed in this paper compared to prior art predistorters are that the filters for group delay cancellation in this block, filters HC1 and HC2, have to be implemented in order to be able to do further DPD function block evaluations. The other predistortion function properties will be evaluated by investigations of the error vectors and without group delay cancellation it is not possible to resolve accurate measures for those properties. The added predistortion functions as the "Differential Gain predistortion Calculation" 203 and the "Power Predistortion Calculation" 205 in Figure 17a will need the low level of the group delay and magnitude errors to provide the correct applications of the function blocks 104 and 103. The Differential Gain PreDistortion Block. After the gain and equalization block 105 in Figure 16 calculations are done and the predistorter system has gone so far in the adaptation that the FIRfilter HC2 is used, the differential gain correction 104 is calculated. The updating is done to a circuit according to Figure 20. The outline of this block is essentially the same as in Figure 10, but the inverse differential complex gain is used in the table. The inverse differential complex gain LUT can be calculated directly or by using the inverse of the gain expression derived for the digital model work. Adaptation is done until a performance measure limit for adaptation is reached as described before. Power Dependence Predistortion block. The Power Predistortion block is the same as in Figure 14 and has the same outline as for the PAmodel PreDistortion and shall apply to the following formula. Sinl_Power_Correct(t)=Sin(t)*(l + dPconv(t+Td)*GP/(Rin(t)+δ)] Where GP is the Power FIRfilter gain. The sign of the factor GP will automatically be the correct depending on the 1Tap equalizing process used to find the GPvalue described in earlier paragraph on page 32. "dPconv" is the convolution of the difference power dP(t)PM in the input signal with the selected Power FIRfilter according to section "The Power Dependence Block" in page 29. Td is the power filtering response delay in time units. The shown delays, in the Figure 14, are adjusted according to the actual digital implementation to fulfill the formula above. The enable and disable of this power function can be made by zeroing the gain factor GP or the Power FIRfilter taps as an example. The mean power value for calculating the differential power can be further optimized depending on the active device used. Some remarks of using this function must be mentioned in order to achieve the best performance. If a faulty delay value "td" is used the distortion spectrum will be shifted in frequency. When a symmetrical spectrum result is achieved for the system the Power adjusting time delay td is optimal. When the lowest spectrum performance is achieved the mean power value PM is adjusted to an optimum value for the device used. Fine adjustment of the PM value may be needed when the mean power in an input signal is not the same as the mean power from a nonlinear device. When the power FIRfilter is decided, further adaptations will be to the power FIRfilter gain value. Normal Utilized Predistortion Blocks. Figure 21 shows the needed predistorter function blocks according to an application as in Figure 2. The main difference is that the EVFIR block 102 in Figure 17 is omitted and therefore the signal "SI" does not need to be transferred to the DSP for signal processing. Extended Usage of The New DPP of The Invention. Figure 22 shows a principle application of the Digital Predistortion circuit described by the present disclosure for a combined DPD and Feed Forward Loop MCPA. The predistorter function blocks shall then have the outline as in Figure 17 including the EV_FIR 101. The added EV_FIR block in Figure 17 minimizes the error between the true input signal S1 and the output signal. The predistorter FIRfilters HCl and HC2 minimize between the modified input signal and the input signal predistortion containing differential gain predistortion. The advantage of this solution is that the DPD in present invention is designed to minimize the error. In a canceling point in a FF design the error has to be minimized for an efficient design. The present DPD solution reduces signal levels to the error power amplifier and therefore the MCPA power consumption in that a lower power output Error Power Amplifier may be used. This combined DPD and FFloop application can be used for MCPA applications requiring very high demands on distortion cancellation. The Feed Forward loop reduces the distortion errors further. In Figure 22 a complex baseband generator 1 provides a digital input signal Vin to a digital predistorter 2 which is controlled by a DSP 3. The input signal is also fed to a DAC and a Reference Upconverter 4. The reference upconverter is used to provide a clean signal without distortion to a signal cancel point 5 in a FF MCPA outline. The cancel point shall only contain the remaining distortion from the Power Amplifier 7. The DPD 2 drives a DAC and upconverter 6 providing a signal to a Main Power Amplifier 7 reducing the distortion. The output signal from the MPA 7 is sampled and provided to the canceling point 5. The output signal after the canceling point is sampled to a measurement receiver 8 measuring the Errors between the required signal and The MPA 7 signal. This signal will contain the remaining distortion from the MPA that has to be minimized. This signal is provided in digital format to the DSP 3. The error signal is also put though an Error Power Amplifier 9 and applied in a correct antiphase provided by the delay adjustment 10 for the EPA 9 time delay to the MCPA output which cancels the introduced delay of the Error Power amplifier. The feed forward loop then cancels the remaining distortion errors, that is present after the DPD adjustment to the MPA 7 output signal. This application is available for the DPD in this invention. The DPD in this invention works on the error vector difference calculating the BV = VPA Vin signal in the predistorter calculations and the algorithms described before in this paper. In the application according to Figure 22, the signal EV is known and the signal Vin is also known. Therefore the signal Vout can be calculated and the same method as in this invention can thus be used for an application as illustrated in Figure 22. The DPD adjusts the signal VPA in Figure 22 until the errors compared to the signal Vin at the reference point is minimized. Any introduced errors in the reference upconverter chain will remain. The DPD will adjust the upconverter frequency response to be the same as for the reference upconverter, when minimizing the errors at the canceling point. The application in Figure 22 is drawn in a simplified form only to illustrate the principle. The reference chain 4 normally uses a frequency translation digital block numerically controlled oscillator NCO in the reference chain to provide the baseband input signal within the useable video frequency range of the used DAC. The used up and down converters will do frequency adjustment so the signals at RFfrequencies are the same by use of different local oscillators settings in the up and down converters. We claim: 1. A complex baseband adaptive digital predistorter circuit providing signal distortion side band suppression and also memory effect compensation for an input signal envelope response dependency of a nonlinear device, characterized in that the digital predistorter circuit comprising an inverse complex gain lookup table memory configured to be read using an amplitude or power of an input signal to provide an inverse complex gain correction; a complex multiplier for multiplying the input signal with an inverse complex to produce a gain correction feeding a distorted signal provided to a non linear device; a measurement receiver for sampling an output signal from the nonlinear device to provide a digital baseband output signal to be compared with the input signal; a time alignment circuirty configured to time align the input signal and the digital baseband output signal on a samplebysample basis; and a phase alignment circuitry configured to phase align complex I/Q signals in the digital signal processing by phase multiplication and alignment of input complex signal baseband I/Q signal; wherein values adapted to an inverse complex gain lookup table memory are evaluated by calculating a complex gain of a combined digital predistorter and the nonlinear device including optional DACs and upconverters, wherein a virtual complex gain table situated in a digital signal processing memory is updated adaptively by using an adaptive virtual digital filter also in a digital signal processing for correct weighting of the complex gain evaluations and wherein the inverse of the virtual complex gain table is loaded into the inverse complex gain lookup table in the digital predistorter circuit for each adaptation; wherein a performance measure of the digital predistorter circuit is evaluated either by comparing difference in impulse response values of the adaptive virtual digital filter in the DSP for each adaptation or a difference in complex gain values. 2. A complex baseband adaptive digital predistorter circuit as claimed in claim 1, comprising a complex phase multiplier inserted into the digital pre distorter circuit multiplying the input signal complex values by a phase value for phase aligning of the signals; a digital filter is inserted in front of an inverse gain compensation function of the digital predistortion circuit, the digital filter being selected to have an inverse frequency response of the adaptive virtual digital filter used for complex gain table evaluations giving added frequency response compensation of the nonlinear system; wherein digital hardware is reduced by incorporating the complex phase multiplier in the digital filter by multiplying complex impulse response values with the phase value; and wherein the inverse gain table values are provided and the digital filter impulse response values are updated adaptively by evaluating the input signal in front of the phase multiplier and the digital filter with a measured output signal of the nonlinear device. 3. A complex baseband adaptive digital predistorter circuit as claimed in claim 2, comprising an inverse complex differential gain correction block is inserted into the digital predistortion circuit in front of the phase multiplier, digital filter and the inverse complex gain block, wherein the inverse complex differential gain correction block comprises a complex difference gain lookup table memory addressed by the magnitude or power of the input baseband signal to this block, a selected value from the inverse differential gain lookup table being provided to a complex multiplier which multiplies an input signal difference vector for next sample to provide an inverse differential gain correction added to the input complex digital baseband I/Q signal at previous sample time as a resulting output signal; and an inverse differential gain lookup table memory is adapted for the inverse of complex differential gain values found by evaluating the measured signal of a combined digital predistortion circuit, the DAC: s and upconverters, and the nonlinear device with the input signal at the inverse complex gain table when the apparatus has adapted to a preset measured performance level for the gain phase compensation block, whereby the inverse differential complex gain block is calculated and adapted in the same manner as for the gain phase compensation block. 4. A complex baseband adaptive digital predistorter as claimed in claim 3, comprising a power dependence correction function block is inserted as a first function block in the digital predistortion circuit, wherein values to be put into parameter value memories for a first function block of the digital nonlinear device model for input power dependence correction of the digital predistorter solution is achieved by a power dependence function being corrected with a power digital filter, which is designed with impulse response selected from a crosscorrelation evaluation between a differential input power from a mean power of the input signal and the remaining magnitude errors between the input signal and the predistorted nonlinear device digital measurement, wherein the cross correlation values from zero cross correlation timing up to a maximum set value of impulse response defining a chosen digital filter, whereby the gain of the power digital filter is adjusted by an equalizing method between a power dependence convolution correction and remaining magnitude errors between the input signal and the predistorted nonlinear device digital measurement, and a correct timing of the power dependence convolution is further evaluated by cross cancellation; and wherein a power correction is made as an amplitude gain correction factor to the incoming digital signal and an update rate of this function block being done according to a need for ambient temperature dependence of the used nonlinear device and is utilized by adaptation of the power digital filter gain. 5. A complex baseband adaptive digital predistorter as claimed in claim 3, comprising: a power dependence correction function block is inserted as a function block in the digital predistortion circuit; wherein for achieving values to put into parameter value memories for a first function block the digital nonlinear device model is evaluated with a power dependence FIRfilter is designed with symmetrical taps from the crosscorrelation evaluation having the cross correlation values from zero cross correlation timing up to a maximum value defining a center FIRfilter tap value of an impulse response, wherein when half of the impulse response is chosen the rest of the response is achieved by mirroring the tap values from the center to the end of the FIRfilter, the number of taps then being set to be an odd number and the FIRfilter becomes symmetrical around the center tap, thereby reducing numerical calculations in the power correction function block to be defined; wherein parameter values for a power dependence correction function block is in the digital predistortion circuit, to be put into memories for a first function block of the digital nonlinear device model, and are evaluated with a power FIRfilter designed with taps selected from a cross correlation evaluation between an input differential power and remaining magnitude errors between the input signal and the predistorted nonlinear device digital measurement, wherein the power dependence FIRfilter has cross correlation related values from zero cross correlation timing up to a maximum value defining a center FIRfilter tap value defining half of the power dependence FIRfilter impulse response, whereby an other half of the impulse response is chosen by mirroring the tap values around the center tap, the number of taps then being set to an odd number and the FIRfilter becomes symmetrical around the center FIRfilter tap value thereby reducing numerical digital convolution calculations in a power correction function block to be defined, wherein the gain of the power dependence FIRfilter is adjusted by 1tap FIR equalizing between the differential power dependence convolution and the power dependence FIRfilter and remaining magnitude errors between the input signal and the predistorted nonlinear device digital measurement, wherein a correct timing of the power dependence convolution is further evaluated by cross cancellation and power correction is made as an amplitude gain correction factor to the incoming digital signal, and an update rate of this function block is performed according to a need for ambient temperature dependence of the nonlinear device and is utilized by adaptation of gain of the power dependence FIRfilter. 6. A complex baseband adaptive digital predistorter as claimed in claim 4, wherein the digital predistorter is applied to a circuit including an added feed forward loop apparatus, wherein a predistortion upconverter mean power amplifier signal sample is provided to a canceling point to be compared to a digitally delayed and phase adjusted input signal provided by a reference upconverter, a resulting signal after the canceling point containing remaining errors from the predistortion main power amplifier is put to an error amplifier, whereby the amplified error signal is added in antiphase to a delayed main power amplifier signal to further reduce output distortion from the apparatus, the complex baseband adaptive signal predistortion futher comprising: a measurement receiver for the digital predistortion circuit and wherein error canceling is arranged to measure a signal after the cancellation point, wherein digital predistortion calculations are modified to compare a time aligned input signal modified by phase and power dependence functions with same signal added with the canceling point signal, an extra error compensation digital filter block is placed in front of the digital predistortion circuit for further error vector reduction after the canceling point by comparing the time aligned input signal with the measured signal added with the time aligned input signal, wherein time delay in samples are arranged for a best performance for the apparatus by introducing appropriate digital time delay blocks in up converters for predistortion and reference signals. 7. A complex baseband adaptive digital predistorter circuit as claimed in claim 1, wherein phase multiplication values are found by 1Tap FIR equalization methods. 8. A complex baseband adaptive digital predistorter circuit as claimed in claim 2, wherein the phase value for phase aligning of the signals is found by 1 tap FIRfilter equalizing methods using time sample aligned input measured signals evaluated only once. 9. A complex baseband adaptive digital predistorter circuit as claimed in claim 2, wherein the digital frequency response compensating filter is an inverse Ntap FIRfilter to an Ntap virtual FIRfilter found by equalization techniques. 

00805DELNP2004Form13Form2630052006.pdf
805DELNP2004Abstract(04092009).pdf
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805DELNP2004Description (Complete)(17122008).pdf
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Patent Number  245687  

Indian Patent Application Number  805/DELNP/2004  
PG Journal Number  05/2011  
Publication Date  04Feb2011  
Grant Date  29Jan2011  
Date of Filing  29Mar2004  
Name of Patentee  TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)  
Applicant Address  S126 25 STOCKHOLM, SWEDEN.  
Inventors:


PCT International Classification Number  H03F 1/26  
PCT International Application Number  PCT/SE02/01958  
PCT International Filing date  20021029  
PCT Conventions:
