Title of Invention

AN INK JET PRINTHEAD

Abstract An ink jet printhead (100) having three columnar arrays (61) of ink drop generators (40) configured for multi-pass color printing at a print resolution having a media axis dot spacing that is less than the columnar nozzle spacing of the ink drop generators. The ink jet printhead more particularly include high resistance heater resistors (56) and efficient FET drive circuits (85) that are configured to compensate for variation in parasitic resistance presented by power traces (86a, 86b, 86c, 86d, 181).
Full Text AN INK JET PRINTHEAD
BACKGROUND OF THE INVENTION
[1] The subject invention generally relates to ink
jet printing, and more particularly to a narrow multi-color
thin film ink jet printhead.
[2] The art of ink jet printing is relatively well
developed. Commercial products such as computer printers,
graphics plotters, and facsimile machines have been
implemented with ink jet technology for producing printed
media. The contributions of Hewlett-Packard Company to ink
jet technology are described, for example, in various
articles in the Hewlett-Packard Journal, Vol. 36, No. 5
(May 1985); Vol. 39, No. 5 {October 19885; Vol. 43, No. 4
(August 1.992); Vol. 43, No. 6 (December 1992); and Vol. 45,
No. 1 (February 1994); all incorporated herein cy
reference.
[3] Generally, an ink jet image is formed pursuant to
precise placement on a print medium of ink drops emitted by
an ink drop generating device known as an ink jet
printhead. Typically, an ink jet printhead is supported on
a movable print carriage that traverses over the surface of
the print medium and is controlled to eject drops of ink at
appropriate times pursuant to command of a microcomputer or

ether controller, wherein the timing of the application of
the ink drops is intended to correspond to a pattern of
pixels o£ the image being printed.
[4] A typical Hewlett-Packard ink jet printhead
includes an array of precisely formed nozzles in an orifice
plate that is attached to an ink barrier layer which in
turn is attached to a thin film substructure that
implements ink firing heater resistors and apparatus for
enabling the resistors. The ink barrier layer defines ink
channels including ink chambers disposed over associated
ink firing resistors, and the nozzles in the orifice plate
are aligned with associated ink chambers. Ink drop
generator regions are formed by the ink chambers and
portions of the thin film substructure and the orifice
plate that are adjacent the ink chambers.
[51 The thin film substructure is typically comprised
of a substrate such as silicon on which are formed various
thin film layers that form thin film ink firing resistors,
apparatus for enabling the resistors, and also intercon-
nections to bonding pads that are provided for external
electrical connections to the printhead. The ink barrier
layer is typically a polymer material that is laminated as
a dry film to the thin film substructure, and is designed
to be photodefinable and both UV and thermally curable. In
an ink jet printhead of a slot feed design, ink is fed from
one or more ink reservoirs to the various ink chambers
through one or more ink feed slots formed in the substrate.
[6] An example of the physical arrangement of the
orifice plate, ink barrier layer, and thin film
substructure is illustrated at page 44 of the Hewlett-
Packard Journal of February 1994, cited above. further
examples of ink jet printheads are set forth in commonly

assigned U.S. Patent 4, 719, 477 and U.S. Patent 5,317,346,
tooth of which are incorporated herein by reference.
[7] Considerations with thin film ink jet printheads
include increased substrate size and/or substrate fragility
as more ink drop generators and/or ink feed slots are
employed. There is accordingly a need for an ink jet
printhead that is compact and has a large number of ink
drop generators.
SUMMARY OF THE INVENTION
[8] The disclosed invention is directed to a narrow
ink jet printhead having three columnar arrays of ink drop
generators configured for multi-pass color printing at a
print resolution having a media axis dot spacing that is
less than the columnar nozzle spacing of the ink drop
generators. In accordance with a more specific aspect of
the invention, the ink jet printhead includes high
resistance heater resistors and efficient FET drive
circuits that are configured to compensate for variation in
parasitic resistance presented by power traces.
BRIEF DESCRIPTION OF THE DRAWINGS
[9] The advantages and features of the disclosed
invention will readily be appreciated by persons skilled in
the art from the following detailed description when read
in conjunction with the drawing wherein:
[10] FIG. 1 is an unsealed schematic top plan view
illustration of the layout of ink drop generators and
primitive select of an ink jet. printhead that employs the
invention.

[11] FIG. 2 is an unsealed schematic top plan view-
illustration of the layout of ink drop generators and
ground busses of the ink jet printhead of FIG. 1.
[12] FIG. 3 is a schematic, partially broken away
perspective view of the ink jet printhead of FIG. 1.
[13] FIG. 4 is an unsealed schematic partial top plan
illustration of the ink jet printhead of FIG. 1.
[14] FIG. 5 is a schematic depiction of generalized
layers of the thin film substructure of the printhead of
FIG. 1.
[15] FIG. 6 is a partial top plan view generally
illustrating the layout of a representatve FET drive
circuit array and a ground bus of the printhead of FIG. 1.
[16] FIG. 7 is an electrical circuit schematic
depicting the electrical connections of a heater resistor
and an FET drive circuit of the printhead of FIG. 1.
[17] FIG. S is a schematic plan view of representative
primitive select traces of the printhead of FIG. 1.
[18] FIG. 9 is a schematic plan view of an
illustrative implementation of an FET drive circuit and a
ground bus of the printhead of FIG. 1.
[19] FIG. 10 is a schematic elevational cross
sectional view of the FET drive circuit of FIG. 9.
[20] FIG. 11 is an unsealed schematic perspective view
of a printer in which the printhead of the invention can be
employed.

DETAILED DESCRIPTION OF THE DIsCLOSURE
[21] In the following detailed description and in the
several figures of the drawing, like elements are
identified with like reference numerals.
[22] Referring now to FIG. 1 - 4, schematically
illustrated therein are unscaled schematic plan views and
perspective views of an ink jet printhead 100 in which the
invention can be employed and which generally includes (a)
a thin film substructure or die 11 comprising a substrate
such as silicon and having various thin film layers formed
thereon, (b) an ink barrier layer 12 disposed on the thin
film substructure 11, and (c) an orifice or nozzle plate 13
laminarly attached to the top of the ink barrier 12.
[23] The thin film substructure 11 comprises an
integrated circuit die that is formed for example pursuant
to conventional integrated circuit techniques, and as
schematically depicted in FIG. 5 generally includes a
silicon substrate 111a, an FET gate and dielectric layer
111b, a resistor layer 111c, and a first metallization
layer llld. Active devices such as drive FET circuits
described more particularly herein are formed in the top
portion of the silicon substrate 111a and the FET gate and
dielectric layer 111b, which includes a gate oxide layer,
polysilicon gates, and a dielectric layer adjacent the
resistor layer 111c. Thin film heater resistors 56 are
formed by the respective patterning of the resistor layer
111c and the first metallization layer 111d. The thin film
substructure further includes a composite passivation layer
111e comprising for example a silicon nitride layer and a
silicon carbide layer, and a tantalum mechanical
passivation layer 111f that overlies at least the heater

resistors 56. A gold conductive layer 111c overlies the
tantalum layer 1111.
[24] The ink barrier layer 12 is formed of a dry film,
that is heat and pressure laminated to the thin film
substructure 11 and photodefined to form therein ink
chambers 19 disposed over heater resistors 58 and ink
channels 29. Gold bonding pads 74 engagable for external,
electrical connections are formed in the gold layer at
longitudinally spaced apart, opposite ends of the thin film
substructure 11 and are not covered by the ink barrier
layer 12. By way of illustrative example, the barrier
layer material comprises an acrylate based photopolymer dry
film such as the "Parad" brand photopolymer dry film
obtainable from E.I. duPont de Nemours and Company of
Wilmington, Delaware. Similar dry films include other
duPont products such as the "Riston" brand dry film and dry
films made by other chemical providers. The orifice plate
13 comprises, for example, a planar substrate comprised of
a polymer material and in which the orifices are formed by
laser ablation, for example as disclosed in commonly
assigned U.S. Patent 5,469,199, incorporated herein by
reference. The orifice plate can also comprise a plated
metal such as nickel.
[25] As depicted in FIG. 3, the ink chambers 19 in the
ink barrier layer 12 are more particularly disposed over
respective ink firing heater resistors 56, and each ink
chamber 19 is defined by interconnected edges or walls of
a chamber opening formed in the barrier layer 12. The ink
channels 29 are defined by further openings formed in the
barrier layer 12, and are integrally joined to respective
ink firing chambers 19. The ink channels 29 open towards
a feed edge of an adjacent ink feed slot 71 and receive ink
from such ink feed slot.

[26] The orifice plate 1.3 includes orifices or nozzles
21 disposed over respective ink chambers 19, such that each
ink firing heater resistor 56, an associated ink chamber
19, and an associated orifice 21 are aligned and form an
ink drop generator 40. Each of the heater resistors has a
nominal resistance of at least 100 ohms, for example about
120 or 130 ohms, and can comprise a segmented resistor as
shown in FIG. 9, wherein a heater resistor 56 is comprised
of two resistor regions 56a, 56b connected by a
metallization region 59. This resistor structure provides
for a resistance that is greater than a single resistor
region of the same area.
[27] While the disclosed printheads are described as
having a barrier layer and a separate orifice plate, it
should be appreciated that the printheads can be
implemented with an integral barrier/orifice structure that
can be made, for example, using a single photopolymer layer
that is exposed with a multiple exposure process and then
developed.
[28] The ink drop generators 40 are arranged in
columnar arrays or groups 61 that extend along a reference
axis L and are spaced apart from each other laterally or
transversely relative to the reference axis L. The heater
resistors 56 of each ink drop generator group are generally
aligned with the reference axis L and havn a predetermined
center to center spacing or nozzle pitch P along the
reference axis L. The nozzle pitch P can be 1/600 inch or
greater, such as 1/300 inch. Each columnar array 61 of ink
drop generators includes for example 96 or more ink drop
generators (i.e., at least 96 ink drop generators).
[293 By way of illustrative example, the thin film
substructure 11 can be rectangular, wherein opposite edges
51, 52 thereof are longitudinal edges of a length dimension

L5 while longitudinally spaced apart, opposite edges 53, 54
are of a width or lateral dimension WS that is less than
the length LS of the thin film substructure 11. The
longitudinal extent of the thin film substructure 11 is
along the edges 51, 52 which can be parallel to the
reference axis L. In use, the reference axis L can be
aligned with what is generally referred to as the media
advance axis. For convenience, the longitudinally
separated ends of the thin film substructure will also be
referred to by the reference number 53, 51 used to refer to
the edges at such ends.
[30] While the ink drop generators 40 of each columnar
array 61 of ink drop generators are illustrated as being
substantially collinear, it should be appreciated that some
of the ink drop generators 40 of an array of ink drop
generators can be slightly off the center line of the
column, for example to compensate for firing delays.
[31] Insofar as each of the ink drop generators 40
includes a heater resistor 56, the heater resistors are
accordingly arranged in columnar groups or arrays that
correspond to the columnar arrays of ink drop generators.
For convenience, the heater resistor arrays or groups will
be referred to by the same reference number 61.
[32] The thin film substructure 11 of the printhead
100 of FIGS. 1-4 more particularly includes three ink
feed slots 71 that are aligned with the reference axis L,
and are spaced apart from each other transversely relative
to a reference axis L. The ink feed slots 71 respectively
feed three ink drop generator groups 61, and by way of
illustrative example are located on the same side of the
ink drop generator groups that they respectively feed. In
this manner, each of the ink feed slots 71 feeds ink, along
a single feed edge. By way of specific example, each of

the ink feed slots provides ink of a color that is
different from the color of the ink provided by the other
ink feed slots, such as cyan, yellow and magenta.
[33] The spacing or pitch CP between the columnar
arrays of ink drop generators is less than or equal to 1060
micrometers (µm) (i.e., at most 1060 µm). The nozzles of
all columns can be positioned at substantially the same
locations along the reference axis L, whereby laterally
corresponding nozzles in the columns are substantially
collinear.
[34] The nozzle pitch P and the drop volume of the ink
drop generators are more particularly configured to enable
multiple pass printing that provides for print dot spacing
that is less than the nozzle pitch which is in the range of
1/300 inch to 1/600 inch. The drop volume can be in the
range of 3 to 7 picoliters for dye based inks (as a
specific example about 5 picoliters). Also, the print dot
spacing along a media axis that is parallel to the
reference axis L can be in the range of 1/1200 inch to
1/2400 inch, which corresponds to a dot resolution range of
1200 dpi to 2400 dpi. Relative to nozzle pitch, such print
dot spacing range corresponds to 1/4th to 1/8th of a nozzle
pitch of l/300th inch, or to a dot spacing that is 1/2 to
l/4th of a nozzle pitch of l/600th inch. As a further
example, the print dot spacing along a scan axis that is
orthogonal to the reference axis L can be in the range of
1/600 inch to 1/1200 inch which corresponds to a print
resolution range of 600 dpi to 1200 dpi along the scan
axis.
[35] More particularly for an implementation having
three columnar arrays 61 each having at least 96 ink drop
generators having a nozzle pitch P of 1/300 inch, by way of

illustrative example, the length LS of the thin film
substructure 11 can be about 11500 micrometers, and the
width of the thin film substructure can be about 4200 µm.
As another example, the width WS of the thin film
substructure can be about 3400 µm. Generally, the
length/width aspect ratio (i.e., LS/WS) of the thin film
substrate can be greater than 2.7.
[36] "Respectively adjacent and associated with the
columnar arrays 61 of ink drop generators 40 are columnar
FET drive circuit arrays 81 formed in the thin film
substructure 11 of the printheads 100A, 100B, as
schematically depicted in FIG. 6 for a representative
columnar array 61 of ink drop generators. Each FET drive
circuit array 81 includes a plurality of FET drive circuits
85 having drain electrodes respectively connected to
respective heater resistors 56 by heater resistor leads
57a. Associated with each FET drive circuit array 81 and
the associated array of ink drop generators is a columnar
ground bus 181 to which the source electrodes of all of the
FET drive circuits 85 of the associated FET drive circuit
array 81 are electrically connected. Each columnar array
81 of FET drive circuits and the associated ground bus 181
extend longitudinally along the associated columnar array
61 of ink drop generators, and are at least longitudinally
co-extensive with the associated columnar array 61. Each
ground bus 181 is electrically connected to at least one
bond pad 74 at one end of the printhead structure and to at
least one bond pad 74 at the other end of the printhead
structure as schematically depicted in FIGS. 1 and 2.
[37] The ground busses 181 and heater resistor leads
37a are formed in the metallization layer 111d (FIG. 5) of
the thin film substructure 11, as are the heater resistor

leads 57b, and the drain and source eloctrodes of the FET
drive circuits 85 described further herein.
[38] The FET drive circuits 85 of each columnar array
of FET drive circuits are controlled by an associated
columnar array 31 of decoder logic circuits 35 that decode
address information on an adjacent address bus 33 that is
connected to appropriate bond pads 74 (FIG. 6) . The
address information identifies the ink drop generators that
are to be energized with ink firing energy, as discussed
further herein, and is utilized by the decoder logic
circuits 35 to turn on the FET drive circuit of an
addressed or selected ink drop generator.
[39] As schematically depicted in FIG. 7, one terminal
of each heater resistor 56 is connected via a primitive
select trace to a bond pad 74 that receives an ink firing
primitive select signal PS. In this manner, since the
other terminal of each heater resistor 56 is connected to
the drain terminal of an associated FET drive circuit 85,
ink firing energy PS is provided to the heater resistor 56
if the associated FET drive circuit is ON as controlled by
the associated decoder logic circuit 35.
[40] As schematically depicted in FIG. 3 for a
representatie columnar array 61 of ink. drop generators, the
ink drop generators of a columnar array 61 of ink drop
generators can be organised into four primitive groups 61a,
61b, 61c, 61d of contiguously adjacent ink drop generators,
and the heater resistors 56 of a particular primitive group
are electrically connected to the same one of four
primitive select traces 86a, 86b, 86c, 86d, such that the
ink drop generators of a particular primitive group are
switchably coupled in parallel to the same ink firing
primitive select signal PS. For the specific example
wherein the number N of ink drop generators in a columnar

array is an integral multiple of 4, each primitive group
includes N/4 ink drop generators. For reference, the
primitive groups 61a, 61b, 61c, old are arranged in
sequence from the lateral edge 53 toward the lateral edge
[41] FIG. 8 more particularly sets forth a schematic
top plan view of primitive select traces 86a, 86b, 86c, 86d
for an associated columnar array 61 of drop generators and
an associated columnar array 81 of FET drive circuits 85
(FIG. 6) as implemented for example by traces in the gold
metallization layer 111g (FIG. 5) that is above and
dielectrically separated from the associated array 81 of
FET drive circuit and ground bus 181. The primitive select
traces 86a, 86b, 86c, 86d are respectively electrically
connected to the four primitive groups 61a, 61b, 61c, 61d
by resistor leads 57b (FIG. 8) formed in the metallization
layer 111d and interconnecting vias 53 (FIG. 9) that extend
between the primitive select traces and the resistor leads
57b.
[42] The first primitive select trace 8 6a extends
longitudinally along the first primitive group 61a and
overlies a portion of heater resistor leads 57b (FIG. 9)
that are respectively connected to heater resistors 56 of
the first primitive group 61a, and is connected by vias 58
(FIG. 9) to such heater resistor leads 57b. The second
primitive select trace 86b includes a section that extends
along the second primitive group 61b and overlies a portion
of heater resistor leads 57b (FIG. 9) that are respectively
connected to heater resistors 56 of the second primitive
group 61b, and is connected by vias 58 to such heater
resistor leads 57b. The second trace 8 6b includes a
further section that extends along the first primitive
select trace 86a on the side of the first primitive select

trace 86a that is opposite the heater resistors 56 of the
first primitive group 61a. The second primitive select
trace 86b is generally L-shaped wherein the second section
is narrower than the first section so as to bypass the
first primitive select trace 86a which is narrower than the
wider section of the second primitive select trace 86b.
[43] The first and second primitive select traces 86a,
86b are generally at least coextensive longitudinally with
the first and second primitive groups 61a, 61b, and are
respectively appropriately connected to respective bond
pads 74 disposed at the lateral edge 53 which is closest to
the first and second primitive select traces 86a, 86b.
[44] The fourth primitive select trace 85d extends
longitudinally along the fourth primitive group 6Id and
overlies a portion of heater resistor leads 5?b (FIG. 9)
that are connected to heater resistors 56 of the fourth
primitive group old, and is connected by vias 58 to such
heater resistor leads 57b. The third primitive select
trace 86c includes a section that extends along the third
primitive group 61c and overlies a portion of heater
resistor leads 57b (FIG. 9} that are connected to heater
resistors 56 of the third primitive group 61c, and is
connected by vias 58 to such heater resistor; leads 57b.
The third primitive select trace 86c includes a further
section that extends along the fourth primitive select
trace 86d. The third primitive select trace 86c is
generally L-shaped wherein the second section is narrower
than the first section so as to bypass the fourth primitive
select trace 86d which is narrower than the wider section
of the third primitive select trace 86c.
[45] The third and fourth primitive select traces 86c,
86d are generally at least coextensive longitudinally with
the third and fourth primitive groups 61c, 61d, and are

respectively appropriately connected to respective bond
pads 74 disposed at the lateral edge 54 that is closest to
the third and fourth primitive select traces 86c, 86d.
[46] By way of specific example, the primitive select
traces 86a, 86b, 86c, 86d for a columnar array 61 of ink
drop generators overlie the FET drive circuits and the
ground bus associated with the columnar array of ink drop
generators, and are contained in a region that is
longitudinally coextensive with the associated columnar
array 61. In this manner, four primitive select traces for
the four primitives of a columnar array 61 of ink drop
generators extend along the array toward the ends of the
printhead substrate. More particularly, a first pair of
primitive select traces for a first pair of primitive
groups 61a, 61b disposed in one-half of the length of the
printhead substrate are contained in a region that extends
along such first pair cf primitive groups, while a second
pair of primitive select traces for a second pair of
primitive groups 61c, 61d disposed in the other half of the
length of the printhead substrate are contained in a region
that extends along such second pair of primitive groups.
[47] For ease of reference, the primitive select
traces 8 6 and the associated ground bus that electrically
connect the heater resistors 56 and associated FET drive
circuits 85 to bond pads 74 are collectively referred to as
power traces. Also for ease of reference, the primitive
select traces 8G can be referred to as to the high side or
non-grounded power traces.
[48] Generally, the parasitic resistance (or on-
resistance) of each of the FET drive circuits 85 is
configured to compensate for the variation in the parasitic
resistance presented to the different FET drive circuits 85
by the parasitic path formed by the power traces, so as to

reduce the variation in the energy provided to the. heater
resistors. In particular, the power traces form a
parasitic path that presents a parasitic resistance to the
FET circuits that varies with location on the path, and the
parasitic resistance of each of the FET drive circuits 85
is selected so that the combination of the parasitic
resistance of each FET drive circuit 85 and the parasitic
resistance of the power traces as presented to the FET
drive circuit varies only slightly from one ink drop
generator to another. Insofar as the heater resistors 56
are ail of substantially the same resistance, the parasitic
resistance of each FET drive circuit 85 is thus configured
to compensate for the variation of the parasitic resistance.
of the associated power traces as presented to the
different FET drive circuits 85. In this manner, to the
extent that substantially equal energies are provided tc
the bond pads connected to the power traces, substantially
equal energies can be provided to the different heater
resistors 56.
[49] Referring more particularly to FIGS. 9 and 1.0,
each of the FET drive circuits 85 comprises a plurality of
electrically .interconnected drain electrode fingers 87
disposed over drain region fingers 89 formed in the silicon
substrate 111a (FIG. 5), and a plurality of electrically
interconnected source electrode fingers 97 interdigitated
or interleaved with the drain electrodes 87 and disposed
over source region fingers 99 formed in the silicon
substrate 111a. Polysilicon gate fingers 91 that are
interconnected at respective ends are disposed on a thin
gate oxide layer 93 formed on the silicon substrate 111a.
A phosphosilicate glass layer 95 separates the drain
electrodes 87 and the source electrodes 97 from the silicon
substrate 111a. A plurality of conductive drain contacts

33 electrically connect the drain electrodes 87 to the
crain regions 89, while a plurality of conductive source
contacts 98 electrically connect the source electrodes 97
to the source regions 99.
[50] The area occupied by each FET drive circuit is
preferably small, and the on-resistance of each FET drive
circuit is preferrably low, for example less than or equal
to 14 or 16 ohms (i.e., at most 14 or 16 ohms), which
requires efficient FET drive circuits. For example, the
on-resistance Ron can be related to FET drive circuit area
A as follows:
Ron wherein the area A is in micrometers2 (µm1). This can be
accomplished by for example with a gate oxide layer 93
having a thickness that is less than or equal to 800
Angstroms (i.e., at most 800 Angstroms), or a gate length
that is less than 4 µm. Also, having a heater resistor
resistance of at least 100 ohms allows the FET circuits to
be made smaller than if the heater resistors had a lower
resistance, since with a greater heater resistor value a
greater FET turn-on resistance can be tolerated from a
consideration of distribution of energy between parasitica
and the heater resistors.
[51] As a particular example, the drain electrodes 87,
drain regions 89, source electrodes 97, source regions 99,
and the polysilicon gate fingers 91 can extend
substantially orthogonally or transversely to the reference
axis L and to the longitudinal extent of the ground busses
181. Also, for each FET circuit 85, the extent of the
drain regions 09 and the source regions 99 transversely to

the: reference axis L is the same as extent of the gate
fingers transversely to the reference axis L, as shown in
FIG. 6, which defines the extent of the active regions
transversely to the reference axis L. for ease of
reference, the extent of the drain electrode fingers 87,
drain region fingers 89, source electrode fingers 97,
source region fingers 99, and polysilicon gate fingers 91
can be referred to as the longitudinal extent of such
elements insofar as such elements are long and narrow in a
strip-like or finger-like manner.
[52] By way of illustrative example, the on-resistance
of each of the FET circuits 85 is individually configured
by controlling the longitudinal extent or length of a
continuously non-contacted segment of the drain region
fingers, wherein a continuously non-contacted segment is
devoid of electrical contacts 88. For example, the
continuously non-contacted segments of the drain region
fingers can begin at the ends of the drain regions 89 that
are furthest from the heater resistor 56. The on-
resistance of a particular FET circuit 05 increases with
increasing length of the continuously non-contacted drain
region finger segment, and such length is selected to
determine the on-resistance of a particular FET circuit.
[53] As another example, the on-resistance of each FET
circuit 85 can be configured by selecting the size of the
FET circuit. For example, the extent of an FET circuit
transversely to the reference axis L can be selected to
define the on-resistance.
[54] For a typical implementation wherein the power
traces for a particular FET circuit 85 are routed by
reasonably direct paths to bond pads 7-1 on the closest of
the longitudinally separated ends of the printhead
structure, parasitic resistance increases with distance

from the closest end of the or printhead, and the one
resistance of the FET drive circuits 85 is decreased
(making an FET circuit more efficients with distance from
such closest end, so as to offset the increase in power
trace parasitic resistance. As a specific example, as to
continuously non-contacted drain finger segments of the
respective FET drive circuits 85 that start at the ends of
the drain region fingers that are furthest from the heater
resistors 56, the lengths of such segments are decreased
with distance from the closest one of the longitudinally
separated ends of the printhead structure.
[55] Each ground bus 181 is formed of the same thin
film metallization layer as the drain electrodes 87 and the
source electrodes 97 of the FET circuits 85, and the active
areas of each of the FET circuits comprised of the source
and drain regions 89, 99 and the polysilicon gates 91
advantageously extend beneath an associated ground bus 181.
This allows the ground bus and FET circuit arrays to
occupy narrower regions which in turn allows for a
narrower, and thus less costly, thin film substructure.
[56] Also, in an implementation wherein the
continuously non-contacted segments of the drain region
fingers start at the ends of the drain reqion fingers that
are furthest from the heater resistors 56, the extent of
each ground bus 181 transversely or laterally to the
reference axis L and toward the associated heater resistors
56 can be increased as the length of the continuously non-
contacted drain finger sections is increased, since the
drain electrodes do not need to extend over such
continuously non-contacted drain finger sections. In other
words, the width W of a ground bus 181 can be increased by
increasing the amount by which the ground bus overlies the
active regions of the FET drive circuits 85, depending upon

the length of the continuously non-contacted drain region
segments. This is achieved without increasing the width or
the region occupied by a ground bus 181 and its associated
FET drive circuit array 81 since the increase is achieved
by increasing the amount of overlap between the ground bus
and the active regions of the FET drive circuits 85.
Effectively, at any particular FET circuit 85, the ground
bus can overlap the active region transversely to the
reference axis L by substantially the length of the non-
contacted segments of the drain regions.
[57] For the specific example wherein the continuously
non-contacted drain region segments start at the ends of
the drain region fingers that are furthest from the heater
resistors 56 and wherein the lengths of such continuously
non-contacted drain region segments decrease with distance
from the closest end of the printhead structure, the
modulation or variation of the width W of a ground bus 181
with the variation of the length of the continuously non-
contacted drain region segments provides for a ground bus
having a width W181 that increases with proximity to the
closest end of the printhead structure, as depicted in FIG.
9. Since the amount of shared currents increases with
proximity to the bonds pads 74, such shape advantageously
provides for decreased ground bus resistance with proximity
to the bond pads 74.
[58] Ground bus resistance can also be reduced by
laterally extending portions of the ground bus 181 into
longitudinally spaced apart areas between the decoder logic
circuits 35. For example, such portions can extend
laterally beyond the active regions by the width of the
region in which the decoder logic circuits 35 are formed.
[59] The following circuitry portions associated with
a columnar array of ink drop generators can be contained in

respective regions having the following widths that are
indicated in FIGS. 6 and 8 by the reference designations
that follow the width values.

These widths are measured orthogonally or laterally to the
longitudinal extent of the printhead substrate which is
aligned with the reference axis L.
[60] Referring now to FIG. 11, set forth therein is a
schematic perspective view of an example of an ink jet
printing device 20 in which the above described printheads
can be employed. The ink jet printing device 20 of FIG. 11
includes a chassis 122 surrounded by a housing or enclosure
124, typically of a molded plastic material. The chassis
122 is formed for example of sheet metal and includes a
vertical panel 122a. Sheets of print media are
individually fed through a print zone 125 by an adaptive
print media handling system 126 that includes a feed tray
128 for storing print media before printing. The print
media may be any type of suitable printable sheet material
such as paper, card-stock, transparencies, Mylar, and the

like, but for convenience the illustrated embodiments
described as using paper as the print medium. A series of
conventional motor-driven rollers including a drive toiler
129 driven by a stepper motor may be used to move print
media from the feed tray 128 into the print zone 125.
After printing, the drive roller 129 drives the printed
sheet onto a pair of retractable output drying wing members
130 which are shown extended to receive a printed sheet.
The wing members 130 hold the newly printed sheet for a
short time above any previously printed sheets still drying
in an output tray 132 before pivotally retracting to the
sides, as shown by curved arrows 133, to drop the newly
printed sheet into the output tray 132. The print media
handling system may include a series of adjustment
mechanisms for accommodating different sizes of print
media, including letter, legal, A-4, envelopes, etc., such
as a sliding length adjustment arm 134 and an envelope feed
slot 135.
[61] The printer of FIG. 11 further includes a printer
controller 136, schematically illustrated as a
microprocessor, disposed on a printed circuit board 139
supported on the rear side of the chassis vertical panel
122a. The printer controller 136 receives instructions
from a host device such as a personal computer (not shown)
and controls the operation of the printer including advance
of print media through the print zone .125, movement of a
print carriage 140, and application of signals to the ink
drop generators 40.
[62] A print carriage slider rod 138 having a
longitudinal axis parallel to a carriage scan axis is
supported by the chassis 122 to sizeably support a print
carriage 140 for reciprocating translational movement or
scanning along the carriage scan axis. The print carriage

143 supports first and second removable ink jet prmthead
cartridges .150, 152 (each of which is sometimes called a
"pen," "print cartridge," or "cartridge"). The print
cartridges 150, 152 include respective printheads 154, 156
that respectively have generally downwardly facing nozzles
for ejecting ink generally downwardly onto a portion of the
print media that is in the print zone 125. The print
cartridges 150, 152 are more particularly clamped in the
print carriage 140 by a latch mechanism that includes
clamping levers, latch members or lids 170, 172.
[63] For reference, print media is advanced through
the print zone 125 along a media axis which is parallel to
the tangent to the portion of the print media that is
beneath and traversed by the nozzles of the cartridges 150,
152. If the media axis and the carriage axis are located
on the same plane, as shown in FIG. 11, they would be
perpendicular to each other.
[64] An anti-rotation mechanism on the back of the
print carriage engages a horizontally disposed anti-pivot
bar 185 that is formed integrally with the vertical panel
122a of the chassis 122, for example, to prevent forward
pivoting of the print carriage 140 about the slider rod
138.
[65] By way of illustrative example, the print
cartridge 150 is a monochrome printing cartridge while the
print cartridge 152 is a tri-color printing cartridge.
[66] The print carriage 140 is driven along the slider
rod 138 by an endless belt 158 which can be driven in a
conventional manner, and a linear encoder strip 159 is
utilised to detect position of the print carriage 140 along
the carriage scan axis, for example in accordance with
conventional techniques.

[67] Although the foregoing has been a description and
illustration of specific embodiments oil the invention,
various modifications and changes thereto can be made by
persons skilled in the art without departing from the scope
and spirit of the invention as defined by the following
claims.

CLAIMS
What is claimed is:
1. An ink jet printhead, comprising:
a printhead substrate (11) including a plurality
of thin film layers;
three side by side columnar arrays (61) of drop
generators (40) formed in said printhead substrate and
extending along a longitudinal extent;
each columnar array of drop generators providing
ink drops of a different color and having at least 96
drop generators separated by an drop generator pitch
P;
said columnar arrays of drop generators being
separated from each other by at most 1060 micrometers;
said drop generators producing ink drops having
an ink drop volume that enables multi-pass printing of
a resolution that is not less than 1/(2P) dpi along a
print axis parallel to said longitudinal extent; and
three columnar arrays (81) of FET drive circuits
(85) formed in said printhead substrate respectively
adjacent said columnar arrays of drop generators for
energizing said columnar arrays of drop generators.
2. The printhead of claim 1 wherein P is in the
range of l/300th inch to 1/S00th inch.
3. The printhead of claim 1 wherein said drop
generators are configured to emit drops having a drop
volume in the range of 3 to 7 picoliters.

4. The printhead of claim I wherein eacn of said
drop generators includes a heater resistor (5t) having a
resistance that is at least 100 ohms.
5. The printhead of claim 1 further including ground
busses (181) that overlap active regions of said FET drive
circuits.
6. The printhead of claim 1 wherein each of said FET
drive circuits has an on-resistance that is less than
(250,000 ohms•micrometers2)/A, wherein A is an area of such
FET drive circuit in micrometers2.
7. The printhead of claim 6 wherein each of said FET
drive circuits has a gate oxide (93) thickness that is at
most 800 Angstroms.
8- The printhead of claim 6 wherein each of said FET
drive circuits has a gate length that is less than 4
micrometers.
9. The printhead of claim 1 wherein each of said FET
drive circuits has an on-resistanca that is at most 14
ohms.
10. The printhead of claim 1 wherein each of said FET
drive circuits has an on-resistance that is at most 16
ohms.
11. The printhead of claim 1 further including power
traces (86a, 86b, 86c, 86d, 181), and wherein the FET drive

circuits are configured, to compensate for a parasitic
resistance presented by said power traces.
12. The printhead of claim 11 wherein respective on-
resistances of said FET circuits are selected to compensate
for variation of a parasitic resistance presented by said
power traces.
13. The printhead of claim 12 wherein a size of each
of said FET circuits is selected to set said on-resistance.
14. The printhead of claim 12 wherein each of said
FET circuits includes:
drain electrodes (87);
drain regions (89);
drain contacts (88) electrically connecting said
drain electrodes to said drain regions;
source electrodes (97);
source regions (99);
source contacts (98) electrically connecting said
source electrodes to said source regions; and
wherein said drain regions are configured to set
an on-resistance of each of said FET circuits to
compensate for variation of a parasitic resistance
presented by said power traces.
15. The printhead of claim 1.4 wherein said drain
regions comprise elongated drain regions each including a
continuously non-contacted segment having a length that is
selected to set said on-resistance.

16. The printhead of claim 1 wherein each of said
columnar arrays of FET drive circuits is contained in a
region having a width that is at most 220 micrometers.
17. The printhead of claim 1 wherein each of said
columnar arrays of FET drive circuits is contained in a
region having a width chat is at most 350 micrometers.
18. The printhead of claim 1 v/herein saxd printhead
substrate has a length LS and a width WS, and wherein LS/WS
is greater than 2.7.
19. The printhead of claim 15 wherein WS is about
1200 micrometers.
20. The printhead of claim 16 wherein WS is about.
3400 micrometers.

Documents:

16-KOLNP-2003-(22-03-2012)-CORRESPONDENCE.pdf

16-KOLNP-2003-(22-03-2012)-PA-CERTIFIED COPIES.pdf

16-kolnp-2003-abstract.pdf

16-kolnp-2003-claims.pdf

16-KOLNP-2003-CORRESPONDENCE 1.1.pdf

16-KOLNP-2003-CORRESPONDENCE 1.2.pdf

16-kolnp-2003-correspondence.pdf

16-kolnp-2003-description (complete).pdf

16-kolnp-2003-drawings.pdf

16-kolnp-2003-examination report.pdf

16-kolnp-2003-form 1.pdf

16-kolnp-2003-form 13.pdf

16-kolnp-2003-form 18.pdf

16-kolnp-2003-form 2.pdf

16-kolnp-2003-form 26.pdf

16-kolnp-2003-form 3.pdf

16-kolnp-2003-form 5.pdf

16-KOLNP-2003-FORM-27.pdf

16-kolnp-2003-gpa.pdf

16-KOLNP-2003-OTHERS.pdf

16-kolnp-2003-reply to examination report.pdf

16-kolnp-2003-specification.pdf

16-kolnp-2003-translated copy of priority document.pdf


Patent Number 245227
Indian Patent Application Number 16/KOLNP/2003
PG Journal Number 02/2011
Publication Date 14-Jan-2011
Grant Date 10-Jan-2011
Date of Filing 02-Jan-2003
Name of Patentee HEWLETT-PACKARD COMPANY
Applicant Address M/S 20 BN. 3000, HANOVER STREET, PALO ALTO, CA
Inventors:
# Inventor's Name Inventor's Address
1 BROWNING, ROBERT, N.K. 1715 NW MENIO DRIVE, CORVALLIS, OR 97330
2 TORGERSON, JOSEPH, M. 24901 HIDDEN VALLEY ROAD, PHILOMATH, OR 97370
3 MACKENZIE, MARK, H. 1715 NW MENIO DRIVE, CORVALLIS, OR 97330
4 MILLER, MICHAEL, D. 33788 SUNSET VIEW LANE, SHEDD, OR 97377
5 BAKKOM, ANGELA, WHITE 1645 SW OTANA DRIVE, CORVALLIS, OR 97330
PCT International Classification Number B41J 2/15
PCT International Application Number PCT/US2001/25912
PCT International Filing date 2001-09-07
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 09/774,811 2001-01-30 U.S.A.