Title of Invention

'AN IMPROVED FRACTIONAL DIVIDER'

Abstract This invention relates to an improved fractional divider that comprises an integer value storage means containing the integer part of the division value 'K' connected to the input of a programmable counter means that is configured for a count value of 'K' or 'K+l' depending upon the state of a count control signal and generates the output signal as well a terminal count signal which is connected to an enable input of a fractional accumulator means that produces said count control signal on an addition overflow and has a first input connected to its result output and a second input connected to the output of a fractional value storage means, containing the fractional part of the divider value. Figure 1
Full Text Field of the invention
This invention relates to an improved fractional divider that is completely programmable, enables high resolution and does not utilize any analog components.
Background of the invention
A fractional divider provides a precise division of an input clock signal by a real number value i.e. computing of an integer value and a fractional value. Fractional dividers are widely used in frequency synthesizers and clock recovery circuits.
In these applications the fractional divider is registered to be programmable over a range of values. Often, it is also important to ensure that the output signal is stable - owing to which a purely digital solution is preferred over one that uses analog techniques.
US patent 6,157,693 describes a fractional frequency divider that implements a fixed frequency division. The fractional division is obtained by changing the phase of the frequency to the divider. Multiple clock signals having the same frequency but differing in phase one generated from the input signal. A delay line can be used to produce the different clock phases. The multiple clock signals are applied to the inputs of a multiplexer. The output of the multiplexer is fed to a constant integer value divider. A Finite State Machine (FSM) controls the selection inputs of the multiplexer to selectively apply different clock signals at appropriate times to the input of the divider to obtain the fractional division. The FSM can be preprogrammed or programmable. This invention utilizes an analog approach, which may be prone to noise. Further, the
resolution possible for using this approach is limited, as the number of phase-shifted clocks that can be generated in practical terms is limited.
US patent 3,959,737 is related to field of frequency synthesis. It employs the method of clock inhibition to achieve fractional frequency division. The basic philosophy in working of the fractional division is inhibition of the clock pulse to divider that stretches the output clock period. In this invention this is achieved by configuring the controllable pre-scaler to K or K+l. The pre-scaler control circuit ensures that the control pulse is generated so that there are no timing related issues in high-speed division. The programmable counter controls one of the inputs to the OR gate and periodically configure the pre-scaler in divide by K or K+l. The scheme is limited where a very-fine fractional division is required. To get a particular value of fractional division, programming of at least three registers is required. For some pre-defined fractional divisions a look up table is provided. But it becomes complex to manage the fractional divisions using software. All the counters are re-initialized after the count is complete. This does not allow a fractional factor to be carried out for next divisions. This creates problems in applications where an accurate fractional division is required.
US patent 4,573,176 employs a fractional divider that achieves a division factor of either 2 or 2+1/N. The division factor of 2+1/N is achieved by dropping a clock pulse every N clock cycles. The fractional divider consists of D-type flip-flops and OR gates. The D-flip-flop is configured as a divide by 2. The output of this flip-flop is the output of fractional divider and is fed to a programmable divider. The programmable divider is configured for any division by the configuration bus. The flip-flop gives a divide by 2 clock to the programmable divider. The fractional divider is configured in 2+1/N mode when the mode control is at logic '0'. The clock input to the divide by 2 flip-flop is inhibited for
one clock cycle in one division cycle. This effectively makes the programmable divider as 2N+1 divider, where N is the current programmed value in the programmable divider.
The disadvantage of the approach is that fractional division discussed in this invention can be configured only as 2+1/N. This scheme cannot be used where the fractional division is to be dynamically configured.
US patent 6,127,863 discusses an efficient fraction division algorithm. The invention deals with modifications in the conventional fractional division to get an efficient fractional division (EFD) of M/(2N+ K). The EFD employs N full adders, where the output Y of the full adder is coupled to an associated one of N registers or accumulators. The output of each accumulator is fed back to input of the corresponding full adder. The full adder also includes another set of accumulators, which couple the carryout or the complimented carry out signals of the full adder back to the frequency control inputs of the full adders. The multiplexers are used to select whether carry signals or complimentary carry out signals or the external signals are to be fed back to the frequency control inputs. Depending on the feedback paths from the accumulator to the frequency control inputs of the full adders, the effective denominator value can be increased or decreased to obtain the desired conversion ratio. The EFD feedback paths are chosen in conjunction with the numerator input value. It is possible to increase the effective denominator by replacing an existing ' 1' in the numerator with a complimentary carry out signal. It is possible to decrease the denominator by replacing a '0' in the numerator with a carry out signal. The actual implementation of this fractional divider for a programmable application is very difficult. Firstly there has to be big mutiplexer for connecting any of the carry out or complimentary carryouts to any of the inputs of the full adder. Programming the fractional divider for any increments in the fractional division
involves lot of calculations. This makes this approach not suitable where the fraction division contents have to be dynamically changed for example clock recovery.
The objects and summary of the invention
The object of this invention is to obviate the above disadvantages by providing a complete digital implementation of the fractional divider and thereby avoiding delay lines and noise due to analog components.
The second object of the invention is to have a flexible scheme wherein both the division value and the fractional part are dynamically programmable to achieve better fractional least count.
Further object of this invention is to make technology migration much simpler by implementing the invention in any HDL (Hardware Definition Language).
To achieve the above objectives, the invention provides an improved fractional divider that provides high resolution without the need for any analog components comprising:
• an integer value storage means containing the integer part of the
division value 'K' connected to the input of a
• programmable counter means that is configured for a count value of
'K' or 'K+1' depending upon the state of a count control signal and
generates the output signal as well a terminal count signal which is
connected to an enable input of a
• fractional accumulator means that produces the count control signal on
an addition overflow and has a first input connected to its result output
and a second input connected to the output of a
• fractional value storage means, containing the fractional part of the divider value.
The integer value storage means is any digital value storage means.
The fractional accumulator means is a multibit full adder having a number of bits depending on the desired resolution of the fractional divider.
The integer storage means is a register.
The fractional value storage means is any digital value storage means.
The fractional value storage means is register.
The integer value storage means and the fractional value storage means are connected to a data bus of a microprocessor based system for loading the integer part and fractional part of the division value respectively.
Brief Description of the drawings
The invention will now be described with reference to the accompanying drawings.
Figure 1 shows the fractional divider together with its components, according to this invention.
Figure 2 explains the working of fractional divider, according to this invention.
Detailed description of the drawings
Figure 1 shows the fractional divider together with its components. The fractional frequency division essentially employs the classical method of clock inhibition to achieve fractional frequency division. The fractional divider consists of a divisional value register (1.1), a programmable counter (1.2), Fractional accumulator (1.3) and a fractional value register (1.4) interconnected to each other. The divisional value register (1.1) and the fractional value register (1.4) interface to a microprocessor bus. The microprocessor programs a value into these registers. Let a value 'K' is written into Division value register (1.1). The Programmable Counter (1.2) is configured to divide by 'K' when the Configure Counter signal is at logic 0. If the Configure Counter signal is at logic 1 the Programmable Counter is configured as divide by 'K+l'. The terminal count from the programmable counter (1.2) is at '!' when the count is equal to the value 'K' else it is at logic '0'. The programmable counter (1.2) is synchronously re-initialized when the terminal count is at logic ' 1'. Initializing the counter to 1 will configure the counter as divide by 'K', while initializing the counter to 0 will configure the counter to divide by 'K+l'. The Fractional accumulator (1.3) is a full adder, which processes only the fractional part of the division. The output of the fractional accumulator is fed back as one of its inputs. The other input to it is the output of the fractional value register (1.4). The addition is performed on rising clock edge only when the terminal count is at '1' i.e., once every cycle of frequency out. The configure counter signal (output of fractional accumulator) is '1' only when an overflow in the accumulator occurs.
Figure 2 shows the working of the fractional divider with the help of a timing diagram. Let the requirement be of a fractional division of 4.25. To get this fractional division, program the 'division value register' 4 and 'fractional value register' to 0.25 (01000000b). On reset at time TO, the accumulator is initialized
to 0. At time Tl, when the 'terminal count' is at logic '1' and rising clock edge, the contents of 'fractional value register' are added to the accumulator. This process is repeated at time T2, T3 and T4. At time T4, adding 0.25 to the contents of accumulator (0.75) will result in an overflow. This overflow flag is connected to configure counter signal. When configure counter is at '1', terminal count is at '1' and rising clock edge the count value is loaded with 0. This configures the counter to divide by 5 (K+l).





We claim:
1. An improved fractional divider that provides high resolution without the
need for any analog components comprising:
• an integer value storage means (1.1) containing the integer part of the
division value 'K' connected to the input of a
• programmable counter means (1.2) that is configured for a count value
of 'K' or 'K+1' depending upon the state of a count control signal and
generates the output signal as well a terminal count signal which is
connected to an enable input of a
• fractional accumulator means (1.3) that produces the count control
signal on an addition overflow and has a first input connected to its
result output and a second input connected to the output of a
• fractional value storage means (1.4), containing the fractional part of
the divider value.

2. An improved fractional divider as claimed in claim 1, wherein the integer
value storage means is any digital value storage means.
3. An improved fractional divider as claimed in claim 1, wherein the
fractional accumulator means is a multibit full adder having a number of
bits depending on the desired resolution of the fractional divider.
4. An improved fractional divider as claimed in claim 2, wherein the integer
storage means is a register.
5. An improved fractional divider as claimed in claim 1, wherein the
fractional value storage means is any digital value storage means.
6. An improved fractional divider as claimed in claim 1, wherein the
fractional value storage means is register.
7. An improved fractional divider as claimed in claim 1, wherein the integer
value storage means and the fractional value storage means are connected
to a data bus of a microprocessor based system for loading the integer
part and fractional part of the division value respectively.
8. An improved fractional divider that provides high resolution without the
need for any analog components substantially as herein described with
reference to and as illustrated in the accompanying drawings.

Documents:

1041-del-2001-abstract.pdf

1041-del-2001-claims.pdf

1041-del-2001-complete specification (granted).pdf

1041-del-2001-correspondence-others.pdf

1041-del-2001-correspondence-po.pdf

1041-del-2001-description (complete).pdf

1041-del-2001-drawings.pdf

1041-del-2001-form-1.pdf

1041-del-2001-form-13.pdf

1041-del-2001-form-18.pdf

1041-del-2001-form-2.pdf

1041-del-2001-form-3.pdf

1041-del-2001-gpa.pdf

1041-del-2001-pa.pdf

1041-del-2001-petition-others.pdf

abstract.jpg


Patent Number 244623
Indian Patent Application Number 1041/DEL/2001
PG Journal Number 51/2010
Publication Date 17-Dec-2010
Grant Date 13-Dec-2010
Date of Filing 10-Oct-2001
Name of Patentee STMICROELECTRONICS PVT. LTD.
Applicant Address PLAT NO. 2 & 3, SECTOR 16A, INSTITUTIONAL AREA, NOIDA-201 301, UTTAR PRADESH, INDIA.
Inventors:
# Inventor's Name Inventor's Address
1 KALYANA CHAKRAVARTHY FLAT NO. 7, AIIMS APARTMENTS, MAYUR KUNJ, NOIDA ROAD, DELHI-110 096, INDIA
PCT International Classification Number H03K 23/50
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA