Title of Invention

"A METHOD OF FABRICATING A SEMICONDUCTOR DEVICE IN A SEMICONDUCTOR STRUCTURE"

Abstract A method for fabricating a semiconductor device in a semiconductor structure, provides enhanced quantum well intermixing in desired regions of the device by forming a first, relatively high quality, epitaxial layer on a substrate, the high quality layer including a quantum well; forming a second, relatively lower quality, epitaxial defect layer on top of the high quality layer; and thermally processing the structure to effect at least partial diffusion of the defects from the defect layer into the high quality layer in order to achieve quantum well intermixing in the structure. The use of an epitaxially grown defect layer on top of, or within, a high quality epitaxially grown device body enables quantum well intermixing techniques to be per...
Full Text The present invention relates to a method of fabricating a semiconductor device in a semiconductor structure
The present invention relates to quantum well intermixing methods for application in the manufacture of semiconductor photonic devices and in the integration of such devices onto a semiconductor substrate
Impurity free intermixing allows the hand-gap of a semiconductor quantum well structure to he locally increased in a conn oiled manner thereby' allowing both active and passive components to be fabricated on semiconductor substrate to improve the performance of individual photonic devices This also facilitates large scale photonic integration
Quantum Well Intemixing (QWT) has been developed as a technique to controllably increase the band-gap of a semiconductor quantum well (QW) structure The intermixing modifies the band-gap of QW structures For example, a GaAs QW with AlGaAs barriers may be intermixing to give rise to a parabolic well that is 'blue-shifted' with respect to the QW Intermixing is spatially selective, allowing the fabrication of individual photonic devices or photonic integrated circuits with passive and active regions
A number of intermixing techniques have been reported, most notably impurity induced disordering (IID), laser induced disordering and dielectric cap annealing
Quantum well intermixing by impurity induced disordering requires that impurities are introduced into the semiconductor either by diffusion from the surface or by ion implantation The disadvantage of using impurity induced disordering is that the impurities introduced 10 disorder the crystal also provide light absorption and scattering centres and are hence undesirable
For a discussion of impurity diffusion techniques, see V W D Laidig et al, Appl Phys Lett, Vol 38, p776-778, 1981 For a discussion of lon-implantation techniques, see J P Noel et al, Appl Phys Lett, Vol 69, p3516-3518,1996
The other intermixing techniques do not involve introducing impurities into the crystal, however laser induced disordering is a difficult process to control m a manufacturing environment since it produces non-uruformity across the intermixed regions. For a discussion, of photoabsorption, see A McKee et al, IEEE J of Quantum Electronics, Vol 33, p45-55,1997
Etch and selective regrowth can also provide a method for achieving multiple band-gap material, but tins technique is difficult and expensive See T M Cockenll et al, IEEE Photonics Technology Letter, Vol 6, p786"-788,1994
Dielectric cap annealing piovides a way forward for a manufacturable 'impurity-free' intermixing process, see J H Marsh et al, PCT/GBD2/00292 and PCT/GB 02/00445 However, a very high temperature anneal is required to get sufficient intermixing, which can give rise to contact problems and diffusion of impurities The processes consider depositing a dielectric cap, such as silica, on top of the semiconductor surface During the sputtering process, point defects are generated on the surface of the semiconductor A thermal anneal results in the out-diffusion of Ga from the epilayer into the dielectric cap The out-diffusion results m the intermixing of the QW region and hence a band gap increase The disadvantage with this process is that it can be difficult to control and requires expensive processing equipment
A semiconductor laser capped with a low temperature layer to enhance the QWI has been pioposed by A S W Lee et al, Appl Phys Lett, 78, 21, p3199
(2003) and A S W Lee et al Semicond Sci Tech, 15, 12, L41, (2000) However, a significant temperature change during growth may enhance the intermixing, bm often leads to a deleterious effect on the aser performance
It is therefore an object of the present mvention to provide an impurity free intermixing technique that has a low anneal temperature, that is simple to fabricate, and that is easier and cheaper to manufacture
According to one aspect, the present mvention provides a method of fabricating a semiconductor device m a semiconductor structure, comprising the steps of
forming a first, relatively high quality, epitaxial layer on a substrate, the high quahty layer including a quantum well,
forming a second, relatively lower quality, epitaxial defect layer on top of the high quahty layer, and
thermally processmg the structure to effect at least partial diffusion of the defects from the defect layer into the high quahty layer m order to achieve quantum well intermixing in the structure
Embodiments of the present mvention will now be described by way of example and with reference to me accompanying drawings m which
Figure 1 shows a schematic diagram of an epitaxy structure with a high defect density layer grown on top,
Figure 2 shows the layered structure for a 980 nm laser with a high defect density AlGaAs upper layer,
Figure 3 shows a schematic diagram of the epitaxy structure of figure 1 after photolithography and etching for manufacture of a semiconductor laser,
Figure 4 shows a schematic diagram of the epitaxy structure of figure 3 after deposition of a layer of sihca and during thermal anneal,
Figure 5 shows a band gap diagram of the resulting laser structure with intermixed facet regions,
Figure 6 shows schematic diagram of a epitaxy structure having a high defect AlGaMP layer as a strain layer,
Figure 7 shows a schematic diagram of an InP based epitaxy structure having high defect density layer of GalhAsP grown on top,
Figure 8 shows a schematic diagram of an epitaxy structure having a high defect density layer grown with a strained QW,
Figure 9 shows a schematic diagram of an epitaxy structure with a patterned surface and semiconductor material is grown on top.
Figure 10 shows a schematic diagram of a double QW system having a defect layer located close to the QW nearer to the substrate,
Figure 11 shows a schematic diagram of an epitaxy structure having a high defect density layer that is doped with an impurity grown on top, and
Figure 12 is a schematic diagram of an epitaxy structure havmg a high defect density layer grown by significantly lowering the growth temperature to allow intermixing to OCCUT
The present invention proposes introducing a high defect layer into a semiconductor structure durmg epitaxial growth of the substrate such that the wafer can be easily intermixed by a straightforward and relatively low temperature annealing process
The intermixing technique of the present invention can be applied to any III— V or II-VI semiconductor structures, such as GaAs / AlGaAs, GalnP / AlGalnP, InGaAs / InGaAsP, InGaAs / InAlGaAs and the like An example of a 980 nm InGaAs / AlGalnAs laser with passive intermixed regions near the facet is described by way of example
The invention has application in at least the fabrication of semiconductor laseis, vertical cavit)' light emitting devices, semiconductor optical integration, seimconductor passive waveguides, optoelectronic integrated encuits and photonic integrated circuits
High quality, epitaxy semiconductoi crystal growth requires the source element DI-V ratio, substrate temperature, and other crystal growth parameteis to be optimised to obtain sufficient quality matenai to fabricate high performance photonic devices Growth, conditions outside this 'window of growth parameters can give rise to crystalline defects that degrade the performance of the device Therefore, during conventional epitaxial growth of semiconductor device materials, very careful attention is paid to the maintenance of the correct growth, parameters
The present invention proposes the growth of high quality semiconductor QW structures, such, as a QW laser for example, under these optimum growth conditions, but with the deliberate introduction of a 'defect' layer within the structure m a precise and controlled manner This defect layer is obtained by epitaxial growth nominally outside the optimal growth 'window' The defect layer can be suitably mtermrxed to achieve spatially localised increases in the band-gap
The expression "defect layer" is intended to encompass any epitaxialty grown layer (le having crystalline structural cononuity with an underlying, epitaxially grown high quality crystal structure) that includes a significantly higher number of inherent defects than the underlying high quality crystal structure mat forms the mam part of the semiconductor device Typically, high quality metallo-organic chemical vapour deposition (MOCVD) epitaxy matenai gives a defect density of ~100 defects/cm2 In the present invent on, the defect layers have a defect density >1000 defects/cm2 or > 106 defects / cm3
The expression "defect" is intended to encompass elements in interstitial positions, including those of a dopant material which may be included during epitaxial growth, and generally elements that are not m position in the crystal lattice, as well as vacancies formed m the lattice By contrast, dopant elements that have been incorporated into proper positions m the crystal structure during epitaxial growth are not generally regarded as "defects" for the purposes of this specification
Figure 1 illustrates high quality epitaxial growth of a semiconductor QW well structure 15, suitable for a laser, for example The epitaxial growth is normally earned out using MBE or MOCVD The epitaxy structure 16 is grown at optimum conditions, ie the best 'growth window' to obtain the highest quality material for a laser device (in terms of low threshold, nigh slope efficiency, long lifetime device etc)
In a preferred embodiment, the high quality epitaxy structure is capped during epitaxial growth with a high defect density layer or layers 17 The high defect density layer or layers 17 are grown by changing the epitaxial growth conditions, such as the III-V ratio, to deliberately introduce crystalline defects m a controlled and precise manner The high, density defect layer provides sufficient defect density to allow intermrxmg to occur
In a preferred embodiment, the standard (high quality) epitaxy structure 16 is grown or deposited using a source element V-III ratio of close to standard conditions of 1 1, while the defect layer 17 is grown oi deposited using a source element V-III ratio lying between standard I 2 and standard / 20 corresponding to a ratio of 1 0 5 and 10 05
in a more general aspect for growth of the defect layei 17, the source element ratio is varied from the ideal storchiometric ratio for a high quality crystal structure to a latio which increases the defect levels to > 1000 defects/cm2, or which increases the defect levels by at least a factor of 10, and more preferably by a factor of 100, over those founc in the high quality epitaxy structure 16
Figure 2 shows a laser structure layer chart as an illustrative example A 980 urn laser is chosen as the example, but similar arrangements may be used for any mdividual semiconductor device or device-to-device integration
The exemplary semiconductor laser consists typically of
a) n-type GaAs layer 1
b) n-type AlGaAs layers 2,3
c) tmdoped AlGaAs GRINSCH layer 4
d) undoped InGaAs QW layer 5
e) undoped AlGaAs GRINSCH layer 6
i) p-type AlGaAs layers 7,8,9
g) p-typeGaAs layer 10
h) p-AlGaAs layer 11 (the high defect layer)
l) p-GaAs cap layer layer 12
Layers 1-10 are grown uider the best possible conditions to obtain the optimum performance fiom the laser structure and form, in combination, the high quality epitaxy structure 16 (figure 1) Preferably, the layers are grown using epitaxial MOCVD and MBE techniques
The additional layer 11 (which may comprise a series of separate sub-layers) is grown on top of the laser structure 15 as the nigh defect layer 17 In this case, the high defect layer 11, 17 could be, for example, GaAs, AlGaAs or GalnP The high defect layei is deposited outside the optimum growth 'window' by changing at least one growth parameter, for example the IH-V ratio as discussed above This enhances the introduction of point defects m the layer, such as Ga vacancies In this manner a high defect density layer is grown on top of the laser structure Preferably, layer 11 is grown using MOCVD or MBE techniques using a low UI-V ratio
Preferably the laser structure includes layer 12 which is a cap layer to inhibit oxidation.
As shown m figure 3, the resulting epitaxy structure 15 can be processed hy photohthogiaphy and etching of the high defect layei 17 using known methods to spatially define areas 30 of high defect epitaxy 17 on top of high quality epitaxy 16 In preferred device manufacture, these areas 30 would correspond to facet ends of a laser
With reference to figure 4, the sample can be further processed by depositing a layer 40 of S1O2 over the structure 15, followed by a thermal anneal to allow the high defect material to diffuse into the high quality material intermixing a quantum well region
The effectiveness of the thermal anneal process is substantially enhanced by the high defect material such that a QWI anneal process can be effected at temperatures less than 850 degrees C Preferably, the anneal process takes place at temperatures less than 800 degrees C The annealing process allows the propagation of defects 41 from the 'high defect' areas to diffuse into and intermix the QW regions
Figme 5 shows a band gap diagram of a laser device 50 In a typical example, the intermixed regions are implemented at the facet ends 51 53 of the laser 50 to piovide non-absorbing mirrors (NAMsJ, but not implemented in the laser cavity waveguide region 53 This enables the manifacture of high power, long lifetime devices
This method is not limited to 980 nm laser but any semiconductor laser or semiconductor device that has a QW region and allows improvements m. individual devices or the fabrication of photonic circuits that consist of active and passive components on chip
With reference to figure 6, m an alternative embodiment, a defect layer 61 of GalnP or AlGahiP is epitaxially grown onto the high quality epitaxy GaAs structure 60 The defect layer 61 is lattice matched to the underlying GaAs material structure so that the difference in thermal expansion coefficients creates localised strain and hence induces additional defects in the lower layers which can assist quantum well mtenmxmg during thermal treatment The defect layer 61 may comprise several sub-layers
Preferably, the thermal treatment for quantum well mtermrxmg is earned out at less than S50 degrees C, and more preferably at less than 800 degrees C
Similarly with reference to figure 7, a defect layer 71 of GalnAsP lattice matched to a InP material system can achieve a similar effect to that described m connection with, figure 6 Defect layer 71 may comprise one or rnoie sub-layers (not shown)
The use of quaternary (or quinTernary) IFI-V" materials allows the defect energy to be varied over a wider parameter space since there are three (or
more) group III elements to vary with respect to the group V element during growth. In a preferred example, the V-ffl source element ratio is varied between 10 5 and 1 0 05 In other examples, the relative ratios of the multiple group HI elements to one another may also be varied to achieve varying defect levels, while the group V proportion is maintained at a constant value
With reference to figure 8, in a further arrangement, a stram layer 85 may be incorporated into a defect layer 81 to enhance the dislocation propagation since it is known that the dislocation propagation is directly proportional to the shear stress on the crystal The strain layer 85 may comprise one or more sub-layers (not shown)
The expression "strain layer" is intended to encompass any substantially single crystal layer having a crystalline structuie which differs in terms of lattice constant, penodicity or orientation from an underlying, epitaxially grown, high quality crystal structure to a sufficiently small extent not to substantially mterfeie with the optical properties of a device to be formed, but sufficient to introduce a number of defects to achieve quantum well mtermixing
The strain layer 85 can be introduced by growing one or more quantum wells in the defect layer 81 that are above the critical thickness The critical thickness can be understood to be the thickness of strain layer at which lattice constant mismatch between two layers are sufficiently dissimilar that the strain due to the lattice mismatch can no longer be accommodated without creating significant number of defects In the preferred embodiment, this significant number of defects in >1000 defects / cm2 The number of defects will be directly proportional to the amount of lattice mismatch or strain in the system
Alternatively, it may be possible to intoduce a stain layer S5 and / 01 one OT more quantum wells above the critical thickness to nucleate the desned dislocatons hi tins manner, the dislocation density of the 'defect' layer 81 can be contiolled, since the dislocation density is a function of strain and alloy composition
With reference to figure 9, a defect layer 91 may be grown upon the high quality epitaxy structure 90 by providing nucleation sources 92 on the surface of the epitaxy structure 90, then growing the defect layer 91 thereover The nucleaton sources 92 may be provided by way of a patterned surface 94, wnich could be formed using conventional photolithographic techniques The threading dislocation density can be the dominant misfit dislocation source rather than inherently growing cefects -into the defect layer by the use of sub-optimal process parameters
In a further embodiment the 'defect' layer may be purposely phase separated and / or ordered to introduce localised strain rnto neighbouring layers For example in an AlGalnP epitaxial growth, the growth conditions can be controlled m such a way that instead of a random alloy of AlGafnP, the AlGalnP phase can separate into atomic 'strips' of A1P, GaP, InP and all the various combinations of the ternary HI-V system This ordering creates defect layers at the interfaces of the 'strips'
The defect layer need not be located on the top of the high quality epitaxy structure It could be incorporated within it at a suitable depth below the surface With reference to figure 10, an epitaxy structure 100 includes a first quantum well 101 and a second quantum well 102, and a defect layer 103 buned within the epitaxy structure The defect layer 103 may compnse a number of sub-layers
Defect layers 103 can he located at different depths within the structure to allow intermixing of features in the crystal growth direction as well as across the crystal plane
With reference to figure 11, in a further embodiment the epitaxially grown defect layer 111 on top of the high quality epitaxy structure 110 is highly doped with an impurity in such a manner that, after thermal annealing, the impurity can diffuse into neighbouring layers An exemplary doped layer is AlGaAs doped with Be Preferably, the dopant levels he m the range 1016 to 1020 cm-3 such that QWI effects can he achieved without compromising device performance to an unacceptable degree While the mobile impurity can cause quantum well intermixing, this technique may also have the disadvantage that the impurity can act as an absorption centre
With reference to figure 12, the defect layer 121 may be grown by changing the temperature of epitaxial growth to introduce the defects into the defect layer 121, pioviding that the change in temperature used to form the defect layer is not sufficiently large to have a deletenous effect on the performance of the photonic device
If the temperature window for growth of high quality laser material and the growth of defect layer overlap then there is a clear advantage in using that overlap temperature range for the defect layer growth
A number of advantages are realised by the use of the foregoing techniques The use of defect and strain layers formed within the epitaxially grown semiconductor material provides a relative simple and cost-effective method of mterrruxing a semiconductor structure Thermal anneal temperatures and surface damage is less than the dielectric method described m the prior art
Simpler, moie reliable, moie cost effective and better contiol of the tuning of -he band gap can be obtained Spatially localised inteterved legions can be obtained in the crystal growth direction as well across the crystal plane
Other embodiments are intentionally within fhe scope of the accompanying claims







We Claim:
1. A method of fabricating a semiconductor device in a semiconductor
structure, comprising the steps of:
forming a first, relatively high quality, epitaxial layer on a substrate,
the high quality layer having a quantum well;
forming a second, relatively lower quality, epitaxial defect layer on top
of the high quality layer; and
thermally processing the structure to effect at least partial diffusion of
the defects from the defect layer into the high quality layer in order to
achieve quantum well intermixing in the structure,
wherein the epitaxial defect layer is formed by varying a source
element ratio during growth away from ideal or stoichiometric
conditions to result in crystalline defects.
2. The method as claimed in claim 1, wherein the high quality epitaxial layer is formed comprising a series of sub-layers.
3. The method as claimed in claim 1, wherein the defect layer is formed comprising a series of sub-layers.
4. The method as claimed in claim 1, wherein the step of forming a high quality epitaxial layer on top of the defect layer prior to the thermal processing step.
5. The method as claimed in claim 1, wherein the step of forming a
cap layer on top of the defect layer.
6. The method as claimed in claim 5, wherein the cap layer is adapted to inhibit oxidation of the defect layer during subsequent processing.
7 The method as claimed in claim 1, wherein the defect layer is formed by varying the substrate temperature away from ideal conditions to result in crystalline defects.
8. The method as claimed in claim 1 or claim 7, wherein the defect layer comprises a defect density in excess of 1000 defects/cm2 or 106 defects/cm3.
9. The method as claimed in claim 1 or claim 7, wherein the defect layer comprises a defect density 10 times higher than that of the high quality layer.
10. The method as claimed in claim 9, wherein the defect layer comprises a defect density 100 times higher than that of the high quality layer.
11. The method as claimed in claim 1, wherein the semiconductor device is formed in a III-V crystal structure, having the steps of:
providing a V-III source element ratio during growth of the high quality layer of substantially 1:1; and
providing a V-III source element ratio during growth of the defect layer lying between 1:0.5 and 1:0.05.
12. The method as claimed in claim 1, wherin the step of
photolithographically processing the substrate to spatially define
areas of the defect layer over the surface of the substrate.
13. The method as claimed in claim 12, wherein the defect layer is defined over regions of the structure that will form non-absorbing mirrors of a laser device.
14. The method as claimed in claim l wherein the step of depositing a layer of SiO2 over the defect layer.
15. The method as claimed in claim 1, wherein the defect layer is provided having a different thermal expansion coefficient than the high quality layer, the layers being lattice matched such that the difference in thermal expansion creates a localised strain increasing defect production during the thermal processing step.
16. The method as claimed in claim 15, wherein the defect layer has at least a AlGalnP layer and the high quality layer has at least a GaAs layer.
17. The method as claimed in claim 15, wherein the defect layer has at least a AlGaAs layer and the high quality layer has at least a GaAs layer.
18. The method as claimed in claim 15, wherein the defect layer has at least a GalnAsP layer and the high quality layer has at least an InP layer.
19. The method as claimed in claim 1, wherein the step of incorporating a strain layer within the defect layer to enhance dislocation propagation during the thermal processing step.
20. The method as claimed in claim 1, wherein the thermal processing step is performed at temperatures of less than 850 degrees C.
21. The method as claimed in claim 1, wherein the semiconductor device formed comprises any one of a laser, a vertical cavity light emitting device, a passive waveguide, an optical integrated circuit or a photonic integrated circuit.
22. The method as claimed in any of the preceding claims, used for fabricating the semiconductor device in a semiconductor substrate, the said device having a quantum well intermixed region.

Documents:

1788-delnp-2005-abstract.pdf

1788-delnp-2005-claims.pdf

1788-delnp-2005-complete specification (granted).pdf

1788-delnp-2005-correspondence-others.pdf

1788-delnp-2005-correspondence-po.pdf

1788-delnp-2005-description (complete).pdf

1788-delnp-2005-drawings.pdf

1788-delnp-2005-form-1.pdf

1788-delnp-2005-form-18.pdf

1788-delnp-2005-form-2.pdf

1788-delnp-2005-form-3.pdf

1788-delnp-2005-form-5.pdf

1788-delnp-2005-gpa.pdf

1788-delnp-2005-pct-101.pdf

1788-delnp-2005-pct-210.pdf

1788-delnp-2005-pct-220.pdf

1788-delnp-2005-pct-304.pdf

1788-delnp-2005-pct-308.pdf


Patent Number 241369
Indian Patent Application Number 1788/DELNP/2005
PG Journal Number 28/2010
Publication Date 09-Jul-2010
Grant Date 30-Jun-2010
Date of Filing 02-May-2005
Name of Patentee INTENSE LIMITED
Applicant Address 4 STANLEY BOULEVARD, HAMILTON INTERNATIONAL TECHNOLOGY PARK, HIGH BLANTYRE, GLASGOW G72 0BN, U.K.
Inventors:
# Inventor's Name Inventor's Address
1 STEPHEN PETER NAJDA 8/6 FLEMING HOUSE, 134 RENFREW STREET, GLASGOW G3 6ST, GREAT BRITAIN.
PCT International Classification Number H01L 51/00
PCT International Application Number PCT/GB2003/004705
PCT International Filing date 2003-10-30
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 0225586.7 2002-11-02 U.K.