Title of Invention

"DIGITAL POWER METER APPARATUS AND METHOD FOR THE SAME"

Abstract A digital power meter apparatus and the method for the same are proposed. The input voltage signal and input current signal through dual channels are processed at a first stage to obtained a first digital signal. The first digital signal is sent to a third low-pass filter. The input voltage signal and input current signal are processed in a second-stage processing through a first low-pass filter, a second low-pass filter and a second logic operation unit to obtain a second digital signal. A third logic operation unit processes the first digital signal and a second digital signal in order to obtain a digital power signal proportion to the product of the two input signals.
Full Text BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital power meter apparatus and method for the same more particularly to a digital power meter apparatus using multipliers and
adders arranged in a plurality of stages and method for the same.
2. Description of Prior Art
To calculate the watt consumption for a household user, the prior art electrical power meter generally uses an inductive-tiype AC ampere meter to calculate the used current. However, the prior art electrical power meter uses mechanical wheel driven by gear to count the ampere used, the electrical power
meter using mechanical wheel has problem of erroneous measurement due to
manufacture tolerance and teeth ratio variation. Moreover, the prior art electrical
power meter is sensible to temperature variation, which causes problem for users
distribute at wide area and reduce lifetime of this power meter. This correct watt
measurement causes inconvenience both to client and power company.
The electrical power meter has a trend of digitalization as the progress of
electrical industry and digital technology. For example, Taiwan patent gazette No.
482901 discloses a digital AC power meter. The disclosed digital AC power meter
uses optical signal for outputting digital measurement'and sends output through network. However, this digital AC power meter still uses mechanic wheel to count
the used current. The preesion thereof is still an issue.
Moreover, US Pat. No. 5862069, 5745323, 58/2469 and 5760619 had disclosed related art. More particularly, the US Pal. No. 5862069 discloses a
digital power meter apparatus further comprises a third logic operation unit to process the first digital signal and a second digital signal in order to obtain a digital power signal proportion to the product of the two input signals.
The above summaries are intended to illustrate exemplary embodiments of the invention, which will be best understood in conjunction with the detailed description to follow, and are not intended to limit the scope of the appended claims.
BRIEF DESCRIPTION OF DRAWING:
The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention itself however may be best understood by reference to the following detailed description of the invention, which describes certain exemplary embodiments of the invention, taken in conjunction with the accompanying drawings in which:
Fig. 1 shows a block diagram of the digital power meter apparatus according to a preferred embodiment of the present invention
Fig. 2 shows the flowchart of the operational steps for the digital power meter according to the present invention.
DETAILED DESCRIPTION OF THE INVENTION Fig. 1 shows a block diagram of the digital power meter apparatus according to a preferred embodiment of the present invention. The digital power meter apparatus according to the present invention comprises a first input channel 11, a second input channel 12, a first signal conversion unit 21, a second signal conversion unit 22. a first frequency-down filter unit 31, a second frequency-down filter unit 32, a first logic operation unit 41, a first low-pass filler 51, a second low-pass filler 52, a third low-pass filter 53-connected to output of the firsl logic operation unit 41, a second logic operation unit 42 and a third logic
41 by the third low-pass filter 53 to obtain a filtered digital signal and sending the
filtered digital signal to an input end of the third logic operation unit 61.
Step 710: Filtering a signal output from a second path of the first frequency-down filter unit 31 and a second path of the second frequency-down filter unit 32 by the first low-pass filter 51 and the second low-pass filter 52, respectively and sending the two filtered signals to the second logic operation unit
42 for further processingStep 712: Coupling the output of the second logic operation unit 42 to another input of the third logic operation unit 61.
Step 714: Subtracting the digital signal obtained by the second logic operation unit 42 from the digital signal obtained by the first logic operation unit 41 to obtain a digital power signal proportion to the product of input signals.
Although the present invention has been described with reference to the preferred embodiment thereof, it will be understood that the invention is not limited to the details thereof Various substitutions and modifications have suggested in the foregoing description, and other will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.
The third logic operation unit 61 is connected to the output of the third
low-pass filter 53,, which .gerforms filter processing to multiplication output of the
first logic, operation unit 41. The third logic operation unit 61 performs a
subtraction operation to the output of the third low-pass filter 53 with the output
of the second logic operation unit 42 to generate a digital power signal proportion
to the product of input time-varying signals. ;
The third logic operation unit 61 is implemented by serial connected adders
with single bit operation to generate sum bit and carry b'it for the adding operation
of next stage. , i
Fig. 2 shows the flowchart of the operational steps for the digital power meter according to the present invention, which comprises following steps:
Step 700: Obtaining the first analog input signal and the second analog input
signal from the first input channel 11 and the second input channel 12.
Step 702: Digitalizing the first analog input signal and the second analog
input signal input from the first input channel 11 and the second input channel 12
into digital converted signal by the first signal conversion unit 21 and the second signal conversion unit 22.
Step 704: Filtering the digital converted signal by the first frequency-down
filter unit 31 and the second frequency-down filter unit 32 connected to the output
of the first signal conversion unit 21 and the second signal conversion unit 22,
respectively.
Step 706: Multiplying the two signals output from a first path of the first
frequency-down filter unit 31 and a first path of the second frequency-down filter
unit 32 by the first logic operation unit 41 in order to obtain a digital signal.
Step 708: Filtering the digital signal output from the first logic operation unit
and the second frequency-down filter unit 32, respectively. The first low-pass filter 51 and the second low-pass filter 52 generate filtered output to function as two input signal of the second logic operation unit 42.
In the preferred embodiment of the present invention, the first low-pass filter
51 and the second low-pass filter 52 are implemented by infinite impulse response
(IIR) low pass, units in cascaded connection. The first low-pass filter, 51 and the second low-pass filter 52, each contains a plurality of adders to perform adding operationto input signal, forward signal and reverse feedback signal. The adder of
the third logic operation unit 61 is preceded by a digital multiplier. The output of the digital multiplier is then sent to the input of the coupled adder.
The first low-pass filter 51, the second low-pass filter 52, and the low-pass
filter 53 have the same input sampling frequency and the same data transmission
rate. Moreover, the first low-pass filter 51, the second low-pass filter 52, and the
third low-pass filter 53 have the same input sampling frequency.
The second logic operation unit 42 is a digital multiplier in the preferred embodiment of the present invention and performs adding operation to the output signal of the first low-pass filter 5! and the second low-pass filter 52 in order to generate a digital signal as another input signal of the third logic operation unit 61.
In the operation of the first logic operation unit 41 and the second logic operation] unit 42, the input signals are saved in register and then digital multiplication operation is performed by a shift register and a single adder. Moreover,the first logic operation unit 41 and the second logic operation unit 42
have the same input sampling frequency and the same output transmission data
rate.
operation unit 61.
The first input channel 11 is used to detect an analog time-varying voltage signal for producing a first input signal. The second input channel 12 is used to detect an analog time-varying current signal for producing a second input signal.
The first signal conversion unit 21 and the second signal conversion unit 22 receive the time-varying analog signals from the first input channel 11 and the second input channel 12, respectively and modulate.' the time-varying analog signals into digital signals. The digital signals output by the first signal conversion unit 21 and the second signal conversion unit 22 are the input signals
for the first frequency-down filter unit 31 and the second frequen'cy-down filter
unit 32, respectively.
The first signal conversion unit 21 and the second signal conversion unit 22 have the same sampling frequency and the same data transmission rate. In other word, the first signal conversion unit 21 and the second signal conversion unit 22
convert any analog input into 1-bit digital signal. In this situation, the first signal
conversion unit 21 and the second signal conversiori unit 22 have the same
sampling frequency and the same data transmission rate.
The input of the first frequency-down filter unit 31 and the second
frequency-down filter unit,32 are connected to the first signal conversion unit 21
' and the second signal conversion unit 22, respectively,, in order to remove noise.
More over the first frequency-down filter unit 31 and the second frequency-down
filter unit 32 convert the 1-bit digital input signal into h-bit digital output signal.
Moreover, the output of the.first frequency-down filter unit 31 is sent to one input end of the first logic operation unit 4 1 and the input of the first low -pass filter 5 1.
The output of tire Second frequency-down filter unit 32 is sent to another input end
41 by the third low-pass filter 53 to obtain a filtered digital signal and sending the
filtered digital signal to an input end of the third logic operation unit 61.
Step 710; Filtering a signal output from a second path of the first frequency-down filter unit 31 and a second path of the second frequency-down filter unit 32 by the first low-pass filter 51 and the second low-pass filter 52, respectively and sending the two filtered signals to the second logic operation unit
42 for further processing.
Step 712: Coupling the output of the second logic operation unit 42 to another input of the third logic operation unit 61.
Step 714: Subtracting the digital signal obtained by the second logic operation unit 42 from the digital signal obtained by the first logic operation unit 41 to obtain a digital power signal proportion to the product of input signals.
Although the present invention has been described with reference to the preferred embodiment thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have suggested in the foregoing description, and other will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.







We Claim:
1. A digital electrical power meter, comprising
a first input channel (11) and a second input channel (12) for receiving a first analog input signal and a second analog input signal, respectively;
a first signal conversion unit (21) and a second signal conversion unit (22) connected to the output of the first input channel (11) and a second input channel (12) and converting the first analog input signal and the second analog input signal into corresponding digital signals;
a first frequency-down filter unit (31) and a second frequency-down filter unit (32) connected to the first signal conversion unit (21) and the second signal conversion unit (22), respectively and used to filter the corresponding digital signals;
a first logic operation unit (41) having two input ends connected to the output of first frequency-down filter (31) and the output of the second frequency-down filter unit (32);
a third low-pass filter (53) connected to the output of the first logic operation unit
(41) in order to filter the output of the first logic operation unit (41);
a first low-pass filter (51) and a second low-pass filter (52) connected to the output of the first frequency-down filter unit (31) and the second frequency-down filter unit (32), respectively;
a second logic operation unit (42) processing the output signal from the first low-pass filter (51) and the second low-pass filter (52); and
a third logic operation unit (61) performed a subtracting operation between the output from the first logic operation unit (41) and the second logic operation unit
(42) to obtain a digital power signal proportion to the product of the first analog
input signal and the second analog input signal.
2. The digital electrical power meter as claimed in claim 1, wherein the first analog input signal and the second analog input signal are voltage analog time-varying signal and current analog time-varying signal, respectively.
3. The digital electrical power meter, as claimed in claim 1, wherein the first signal conversion unit (21) and the second signal conversion unit (22) have the same
sampling frequency and the same data transmission rate.
4. The digital electrical power meter as claimed in claim 1, wherein the first
frequency-down filter unit (31) has a frequency-down factor, which is determined by
the ratio of the sampling frequency and the data transmission rate in the input
analog signal; the second frequency-down filter unit (32) has a frequency-down factor,
which is determined by the ratio of the sampling frequency and the data
transmission rate in the input analog signal; the first frequency-down filter unit (31)
having the same frequency-down factor as that of the second frequency-down filter
unit (32) ; the output data transmission rate of the first frequency-down filter unit (31)
being different to the input sampling rate of the first signal conversion unit (21) ; the
output data transmission rate of the second frequency-down filter unit (32) being
different to the input sampling rate of the second signal conversion unit (22) ; the
frequency-down operation of the first frequency-down filter unit (31) and the second
frequency-down filter unit (32) being performed by 2's complement logic operation.
5. The digital electrical power meter as claimed in claim 1, wherein the first low-pass filter (51) and the second low-pass filter (52) are implemented by infinite-impulse-response low pass units in cascaded connection, each contains a plurality of adders to perform adding operation to input signal, forward signal and reverse feedback signal; the adders having input coupled to output of a digital multiplier.
6. The digital electrical power meter as claimed in claim 1, wherein the first low-pass filter (51) has the input sampling frequency same as the data transmission rate thereof, the second low-pass filter (52) has the input sampling frequency same as the data transmission rate thereof, the third low-pass filter (53) has the input sampling frequency same as the data transmission rate thereof, the first low-pass filter (51), the second low-pass filter (52), and the low-pass filter have the same input sampling frequency.
7. The digital electrical power meter as claimed in claim 1, wherein each of the
first logic operation unit (41) and the second logic operation unit (42) has a register
for saving input signal, a shift register and a single adder for digital multiplication
operation.
8. The digital electrical power meter as claimed in claim 1, wherein the first logic operation unit (41) has the input sampling frequency same as the output data transmission rate thereof, the second logic operation unit (42) has the input sampling frequency same as the output data transmission rate thereof.
9. The digital electrical power meter as claimed in claim 1, wherein the third logic operation unit (61) is implemented by serial connected adders with single bit operation to generate sum bit and carry bit for the adding operation of next stage.
10. A method implemented in a digital electric power meter as claimed in claim 1, said
method comprising;
obtaining a first analog input signal and a second analog input signal from a input channel (11) and a second input channel (12);
digitalizing the first analog input signal and the second analog input signal input from the first input channel (11) and the second input channel (12) into digital converted signal by a first signal conversion unit (21) and a second signal conversion unit (22);
filtering the digital converted signal to remove noise by a first frequency-down filter unit (31) and a second frequency-down filter unit (32) connected to the output of the first signal conversion unit (21) and the second signal conversion unit (22), respectively;
operating the two signals output from a first path of the first frequency-down filter unit (31) and a first path of the second frequency-down filter unit (32) by a first logic operation unit (41) in order to obtain a digital signal;
filtering the digital signal output from the first logic operation unit (41) by a third low-pass filter (53) to obtain a filtered digital signal and sending the filtered digital signal to an input end of a third logic operation unit (61);
filtering a signal output from a second path of the first frequency-down filter unit (31) and a second path of the second frequency-down filter unit (32) by a first low-pass filter (51) and a second low-pass filter (52), respectively and sending the two filtered signals to the second logic operation unit (42) for further processing;
coupling the output of the second logic operation unit (42) to another input of the third logic operation unit (61); and
subtracting the digital signal obtained by the second logic operation unit (42)
from the digital signal obtained by the first logic operation unit (41) to obtain a digital power signal proportion to the product of input signals.

Documents:

2430-del-2004-abstract.pdf

2430-del-2004-claims.pdf

2430-del-2004-complete specification(granted).pdf

2430-DEL-2004-Correspondence-Others-(21-03-2011).pdf

2430-del-2004-correspondence-others.pdf

2430-del-2004-correspondence-po.pdf

2430-del-2004-description (complete).pdf

2430-del-2004-drawings.pdf

2430-del-2004-form-1.pdf

2430-del-2004-form-19.pdf

2430-del-2004-form-2.pdf

2430-del-2004-form-26.pdf

2430-DEL-2004-Form-27-(21-03-2011).pdf

2430-del-2004-form-3.pdf

2430-del-2004-form-5.pdf


Patent Number 239806
Indian Patent Application Number 2430/DEL/2004
PG Journal Number 15/2010
Publication Date 09-Apr-2010
Grant Date 31-Mar-2010
Date of Filing 03-Dec-2004
Name of Patentee FORTUNE SEMICONDUCTOR CORPORATION
Applicant Address 28F,NO.27, CHUNG-CHENG EAST RD.,SEC.2, TAM-SHUI, TAIPEI 251, TAIWAN, REPUBLIC OF CHINA
Inventors:
# Inventor's Name Inventor's Address
1 YI-CHOU HUANG 28 F, NO. 27, CHUNG-CHENG EAST RD., SEC. 2,TAM-SHUI, TAIPEI 251, TAIWAN, REPUBLIC OF CHINA
2 KUO-YUAN YUAN 28 F, NO. 27, CHUNG-CHENG EAST RD., SEC. 2,TAM-SHUI, TAIPEI 251, TAIWAN, REPUBLIC OF CHINA
3 ARTHUR SHAOYAN RONG 28 F, NO. 27, CHUNG-CHENG EAST RD., SEC. 2,TAM-SHUI, TAIPEI 251, TAIWAN, REPUBLIC OF CHINA
PCT International Classification Number G01R 21/06
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA