Title of Invention

FLIP-FLOP CIRCUIT ARRANGEMENT

Abstract Flip-flop circuit arrangement A flip-flop circuit arrangement having a total of four Differential amplifiers (1, 2, 3, 4), which are connected to one another to produce a D flip-flop, is specified. According to the suggested principle, the two shared emitter nodes (E1, E2) of the differential amplifiers (1, 2, 3, 4) are connected via a switch pair (S1, S2) to supply potential and are activated by a differential input clock signal at a control input (CN,CP). The present flip-flop circuit is operable using especially low supply voltage (VCC) and is preferably suitable for constructing frequency dividers or shift registers.
Full Text P2003,0256
DESCRIPTION
Flip-flop circuit arrangement
The present invention relates to a flip-flcp circuit
arrangement.
Flip-flop circuits constructed in integrated circuit
technology are among the basic circuit blocks of integrated
circuit technolcgy and have manifold fields of application.
Flip-flop circuits may be constructed using emitter-coupled
transistors in ECL (emitter coupled logic) circuit
technology, for example.
Flip-flop circuits of this type for rapid signal processing
are normally constructed symmetrically and are designed for
processing; differential signals.
Known flip-flop circuits in ECL technology have the problem
that, because of their construction,, they normally require
relatively large operating voltages, since at least two
base-emitter voltages always drop out between the two
supply potentials. However, it is desirable in modern
communication electronics in particular to be able to
operate flip-if 1 Dp circuits with smaller and smaller supply
voltages.
The object of the present invention is to specify a flip-
flop circuit arrangement which may be constructed in ECL
circuit technology and which may be operated using a lower
supply voltage.
The object is achieved according to the present invention
by a flip-flop circuit arrangement comprising
a pair of input terminals, designed for supplying a
differential input clock signal.,

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a pair of output terminals, designed for tapping a
differential, output signal,
four differential amplifiers, each having two
transistors, whose controlled sections are each
positioned in a series circuit with a resistor, the
series circuits being positioned between a supply
potential terminal and a first and/or second shared
emitter node, whose control terminals are coupled to
one another to form a D flip-flop structure and in
which the pair of output terminals is formed at the
output of at least one differential amplifier,
a first current source, which connects the first
shared emitter node to a reference potential terminal,
a second current source, which connects the second
shared emitter node to the reference potential
terminal,
a first switch, whose controlled section is connected
between supply potential terminal and first emitter
node, and
a second svitch, whose controlled section is connected
between supply potential terminal and second emitter
node,
the first and the second switch each having a control
terminal, vhich form the pair of input terminals.
The suggested flip-flop circuit arrangement is constructed
symmetrically and is designed for guiding differential
signals.
The circuit may preferably be implemented in ECL circuit
technology.
According to the suggested principle, the two switches
which are activated using the differential clock signal are
related directly to supply potential from the two emitter
nodes.

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Accordingly, the advantage results that only one base-
emitter voltage UBE drops out between supply potential
terminal and reference potential terminal if the
differential amplifier transistors and the switches are
implemented in bipolar technology, and therefore the
circuit may advantageously be operated using especially low
voltage.
In addition, is corresponds to the suggested principle that
only two current sources are required, which couple each of
the two shared emitter nodes to reference potential. The
current sources for all differential amplifiers are thus
combined into a current source pair.
An additional advantage of the suggested principle results
in that, due 1:o the lower number of required current
sources, the current required for the circuit is reduced.
Still a further reduction of the current required for the
circuit results through preferred implementation of the
first and second switches, which are activated by the
differential clock signal, as transistors which operate as
emitter sequencers. Therefore, emitter sequencers at the
output of the flip-flop circuit may advantageously be
dispensed with.
Nonetheless, ii: is advantageously possible using the
suggested circuit to connect the output of a flip-flop
implemented as suggested to a data input thereof or
directly to a further, identical flip-flop. Accordingly,
frequency divider circuits and/or shift registers may be
constructed without problems using the suggested flip-flop
and emitter sequencers at the output may nonetheless be
dispensed with.

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According to a preferred refinement of the suggested flip-
flop circuit arrangement, the four differential amplifiers
are implemented so that
a first differential amplifier is provided, comprising
a first pair of emitter-coupled transistors in the
first emitter node, whose collector terminals form a
first circuit node and a second circuit node and whose
base termirals are cross connected to their collector
terminals,
a second differential amplifier is provided,
comprising a second pair of emitter-coupled
transistors in the second emitter node, whose
collector terminals are connected to the first circuit
node and/or to the second circuit node and whose base
terminals form a third circuit node and a fourth
circuit node,
a third differential amplifier is provided, comprising
a third psiir of emitter-coupled transistors in the
second emitter node, whose collector terminals are
connected to the third circuit node and/or to the
fourth circuit node and whose base terminals, are cross
connected to their collector terminals, and
a fourth differential amplifier is provided,
comprising a fourth pair of emitter-coupled
transistors in the first emitter node, whose collector
terminals are connected to the third circuit node
and/or to the fourth circuit node and whose base
terminals are connected to the second circuit node
and/or to 1;he first circuit node.
According to a further preferred embodiment of the
suggested principle, the first, the second, the third, and
the fourth circuit nodes, which are formed at the
particular collector terminals of the transistors of the
differential amplifiers, are each connected via a resistor
to the supply potential terminal,

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The resistors may be implemented as current sources. The
current sources may be implemented as wired transistors
suitable for this purpose. The current source transistors
are preferably implemented as field effect transistors in
this case.
The differential amplifiers and the two switches which are
activated using the differential clock signal are
preferably implemented in bipolar circuit technology. The
switch transistors and differential amplifier transistors
are preferably implemented as npn transistors.
The first and the second current sources, which connect the
two shared emitter nodes to the reference potential
terminal of the flip-flop circuit, are preferably
implemented in MOS circuit technology and each comprise a
transistor. The current source transistors are preferably
implemented as a-channel transistors of a self-controlling
type. The control terminals of the transistors which form
the first and :he second current sources are preferably
connected to one another and applied to a constant
reference potertial. In this case, the current source
transistors are preferably each output transistors of a
current balancer. Alternatively, the first and second
current sources may also be implemented as resistors or
bipolar transistors.
Further details and advantageous embodiments of the
suggested principle are the object of the subclaims.
The present invention will be explained in greater detail
in the following in an exemplary embodiment on the basis of
the single figure.
The figure shows an exemplary embodiment of the present
flip-flop circuit arrangement constructed in

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ECL circuit technology on the basis of a
circuit diagram.
The figure shows a flip-flop circuit arrangement, which is
constructed symmetrically and which is designed for
processing differential signals, The present flip-flop
circuit arrangement is constructed in emitter coupled logic
(ECL) circuit technology and is preferably implemented as
an integrated circuit.
The flip-flop circuit arrangement conprises a pair of input
terminals CF, Cft , to which a differential clock signal may
be supplied. The pair of input terminals CN, CP is formed
on each base terminal of each assigned transistor S1, S2.
The npr. transistors S1, S2, which operate as switches, have
their two coll actor terminals directly connected to a
supply potential terminal VCC. The emitter terminal of the
first switch SI is connected to a first shared emitter node
El. The emitter terminal of the second switch S2 is
connected to a second shared emittesr node. The first and
the second emitter nodes El, E2 are connected via one
constant current source Ql, Q2 each to a reference
potential term.ir.al VEE. The constant current sources Ql, Q2
are implemented in the present case as MOS field effect
transistors of the n-channel type. The gate terminals of
the current source transistors Ql, Q2 are connected to one
another and forn a terminal VNB for supplying a reference
level. A current source is preferably connected to this
terminal via a transistor diode, so that the transistors
Ql, Q2 each form the output-side transistor of a current
balancer.
The actual coru of the flip-flop circuit arrangement is
formed by a total of four differential amplifiers 1, 2, 3,
4, whose inputs and outputs are connected as described in
the following to the two summation nodes El, E2. The
transistors of the differential amplifiers I through 4 are

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implemented in this case in bipolar circuit technology as
npn transistors and are switched in ECL circuit technology.
The first differential amplifier 1 comprises two emitter-
coupled transistors 5, 6, whose emitter terminals are
connected directly to one another and to the first emitter
node El. The collector terminal of the first transistor 5
of the first differential amplifier 1 forms a first circuit
node ONI, the collector terminal of the second transistor 6
of the first differential amplifier 1 forms a second
circuit node 0P1, The base terminal of the first transistor
5 is connected to the collector terminal of the second
transistor 6 and the base terminal oi: the second transistor
6 is connected to the collector terminal of the first
transistor 5. The first circuit node ONI is connected via a
first resistor Rl to the supply potential terminal VCC. The
second circuit rode 0P1 is connected via a second resistor
R2 to the supply potential terminal VCC.
The second differential amplifier 2 comprises a first
transistor 7 and a second transistor 8, whose emitter
terminals are connected to one another and to the second
shared emitter rode E2. The collector terminal of the first
transistor 7 oi: the second differential amplifier 2 is
connected to the first circuit node ONI, the collector
terminal of tie second transistor 8 of the second
differential amplifier 2 is connected to the second circuit
node OP1. The base terminal of the first transistor 7 is
connected to a third circuit node 0N2, and the base
terminal of th fourth circuit node 0P2.
The third differential amplifier 3 comprises a first
transistor 9 a:id a second transistor 10, whose emitter
terminals are connected to one another and to the second
shared emitter node E2 of the circuit. Collector and base
terminals of the transistors 9, 10 of the third

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differential amplifier 3 are cross connected to one another
like the transistors 5, 6 in the first differential
amplifier 1, The collector terminal of the first transistor
9 of the third differential amplifier 3 is connected to the
third circuit node 0N2, the collector terminal of the
second transistcr 10 of the third differential amplifier 3
is connected to the fourth circuit node 0P2.
The fourth differential amplifier 4 comprises two emitter-
coupled transistors 11, 12, whose shared emitter terminal
is connected to the first summation node and/or shared
emitter node El, The collector terminal of the first
transistor 11 i;s connected to the third circuit node ON2,
the collector terminal of the second transistor 12 of the
fourth differential amplifier 4 is connected to the fourth
circuit node OPZ. The base terminal of the first transistor
11 is connected to the second circuit node OP1, the base
terminal of the second transistor 12 of the fourth
differential amplifier 4 is connected to the first circuit
node ONI.
The third and the fourth circuit nodes ON2, 0P2 form the
pair of output terminals QN, QP of the flip-flop circuit
arrangement.
The four circuit nodes ONI, OP1, 0N2, 0P2 of the circuit
arrangement are each connected via a resistor Rl, R2, R3,
R4 to the supply potential terminal VCC.
The supply voltage required for operating the circuit
according to the figure results from the potential
difference between the supply potential terminal VCC and
the reference potential terminal VB3. The minimum required
voltage results from the sum of at least three voltages,
namely the voltage which drops out over the resistors Rl
through R4, a base-emitter voltage, which drops out over
the transistors 5 through 12, SI, S2, and a current source

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voltage, which drops out via the current sources Qi, Q2. in
the circuit shovn, in which, for example, a drop of 0.3 V
via the collector resistors, a voltage drop, also of 0.3 V,
at the current balancer transistors Ql, Q2, and a base-
emitter voltage of 0.9 V at the transistors 5 through 12,
SI, S2, are provided, a minimum supply voltage for
realistic operation of the D flip-flop of only 1.5 V
results in the present number example.
The two switches SI, S2 operate as emitter sequencers and
are connected in a bypass circuit to the summation nodes
El, E2 of the differential amplifiers 1 through 4, The
functionality of an output emitter sequencer is accordingly
already integrated into the circuit, so that,
advantageously, no emitter sequencer is necessary at the -
output QN, QP. Accordingly, the circuit offers an
additional current savings.
The circuit according the figure is especially suitable for
being wired as frequency divider, which causes a frequency
division by two. For this purpose, the outputs QN, QP of
the flip-flop, which is a D flip-flop, are connected to the
data inputs of the flip-flop in negative feedback. A signal
having half the clock frequency applied at the clock input
CN, CP may then be tapped at the output QN, QP.
A further, preferred field of application of the circuit is
the construction of shift registers. For this purpose, the
outputs QN, QP of a flip-flop according to Figure 1 are
each connected to the data input pair of a downstream,
identical flip-Elop. The clock inputs CN, CP of all flip-
flops connected in this way to form a shift register are
connected to on«» another and to a shared clock input of the
register.
In alternative embodiment of the present invention, for
example, a transistor may be provided instead of the

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resistors Rl t.h::ough R4. Bipolar transistors may also be
replaced by unipolar field affect transistors and/or vice
versa.

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P2003,0256
PATENT CLAIMS
1. A £lip-flop circuit arrangement, comprising
a paii of input terminals (CP, CN) , designed for
supplying a differential clock signal,
a pair of output terminals (QP, QN), designed for
tapping a differential output signal,
four differential amplifiers (1, 2, 3,. 4), each
having two transistors (5, 6/ 7, 8; 9, 10; 11, 12),
whose controlled sections are each positioned in a
series circuit with a resistor (Rl, R2, R3, R4) , the
series ciicuits being positioned between a first
supply potsntial terminal (VCC) and a first and/or
second shared emitter node (El, E2) , whose control
terminals c.re coupled to one another to form a D flip- -
flop structure and in which the pair of output
terminals fQP, QN) is formed at the output of at least
one differential amplifier (3) ,
a fir:3t current source (Ql) , which connects the
first shared emitter node (El) to a reference
potential terminal (VEE),
a second current source [Q2), which connects the
second she.red emitter node (E2) to the reference
potential terminal (VEE),
a fir,3t switch (SI) , whose controlled section is
connected between.the supply potential terminal (VCC)
and the f i::st emitter node (El) , and
-a second switch (S2), whose controlled section is
connected oetween the supply potential terminal {VCC)
and the second emitter node (E2),
the first and the second switches (SI, S2) each
having a control terminal which form the pair of input
terminals (CP, CM) .
2. The flip-flop circuit arrangement according to Claim
1,
characterized in that

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a first differential amplifier (1) is provided,
comprising a first pair of emitter-coupled transistors
(5, S) in the first emitter node (El), whose collector
terminals form a first circuit node (CN1) and a second
circuit node (0P1) and whose base terminals are cross
connected to their collector terminals',
a seccnd differential amplifier (2) is provided,
comprising a second pair of emitter-coupled
transistors (7, 8) in the second emitter node (E2) ,
whose collector terminals are connected to the first
circuit node (ONI) and/or to the second circuit node
(OPl) and .vhose base terminals form a third circuit
node (0N2) and a fourth circuit node (0P2),
a third differential amplifier (3) is provided,
comprising a third pair of emitter-coupled transistors
(9, 10) in the second emitter node (E2) , whose
collector terminals are connected to the third circuit
node (0N2) and/or to the fourth circuit node (OP2) and
whose base terminals are cross connected to their
collector terminals, and
a fourth differential amplifier (4) is provided,
comprising a fourth pair of emitter-coupled
transistors (11, 12) in the first emitter node (El),
whose collector terminals are connected to the third
circuit node (ON2) and/or to the fourth circuit node
(OP2) and whose base terminals are connected to the
second circuit node (OPl) and/or to the first circuit
node (ONI) .
3. The flip-flop circuit arrangement according to Claim
2,
characterised in that the first, the second, the
third, and the fourth circuit nodes (ONI, OPl, ON2,
OP2) are oach connected via a resistor (Rl, R2, R3,
R4) to the supply potential terminal (VCC).

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4. The flip-flop circuit arrangement according to one of
Claims 1 through 3,
characterized in that the first, the second, the
third, and the fourth differential amplifiers (1, 2,
3, 4) and the first and the second switches (Si, S2)
are implemented in bipolar circuit technology.
5. The flip-flop circuit arrangement according to one of
Claims 1 through 4,
characterized in that the first current source and the
second current source (Ql, Q2) each comprise a
transistor in metal oxide semiconductor circuit
technology.
6. The flip-flop circuit arrangement according to one of-
Claims 1 through 5,
characterized in that it is implemented in emitter
coupled locic circuit technology.

Flip-flop circuit arrangement
A flip-flop circuit arrangement having a total of four
Differential amplifiers (1, 2, 3, 4), which are connected
to one another to produce a D flip-flop, is specified.
According to the suggested principle, the two shared
emitter nodes (E1, E2) of the differential amplifiers (1,
2, 3, 4) are connected via a switch pair (S1, S2) to supply
potential and are activated by a differential input clock
signal at a control input (CN,CP). The present flip-flop
circuit is operable using especially low supply voltage
(VCC) and is preferably suitable for constructing frequency
dividers or shift registers.


Documents:

01978-kolnp-2005-abstract.pdf

01978-kolnp-2005-claims.pdf

01978-kolnp-2005-description complete.pdf

01978-kolnp-2005-drawings.pdf

01978-kolnp-2005-form 1.pdf

01978-kolnp-2005-form 2.pdf

01978-kolnp-2005-form 3.pdf

01978-kolnp-2005-form 5.pdf

01978-kolnp-2005-international publication.pdf

1978-kol np-2005-granted-abstract.pdf

1978-kol np-2005-granted-claims.pdf

1978-kol np-2005-granted-correspondence.pdf

1978-kol np-2005-granted-description (complete).pdf

1978-kol np-2005-granted-drawings.pdf

1978-kol np-2005-granted-examination report.pdf

1978-kol np-2005-granted-form 1.pdf

1978-kol np-2005-granted-form 18.pdf

1978-kol np-2005-granted-form 2.pdf

1978-kol np-2005-granted-form 26.pdf

1978-kol np-2005-granted-form 3.pdf

1978-kol np-2005-granted-others.pdf

1978-kol np-2005-granted-reply to examination report.pdf

1978-kol np-2005-granted-specification.pdf

1978-kol np-2005-granted-translated copy of priority document.pdf

abstract-01978-kolnp-2005.jpg


Patent Number 235985
Indian Patent Application Number 1978/KOLNP/2005
PG Journal Number 37/2009
Publication Date 11-Sep-2009
Grant Date 10-Sep-2009
Date of Filing 06-Oct-2005
Name of Patentee AUSTRIAMICROSYSTEMS AG.,
Applicant Address AUSTRIA, SCHLOSS PREMSTATTEN, UNTEROREMSTATTEN 8141
Inventors:
# Inventor's Name Inventor's Address
1 HOSS,WOLFGANG DR.-LEMISCHSTRASSE 15,GRAZ 8054
2 HOSS,WOLFGANG DR.-LEMISCHSTRASSE 15,GRAZ 8054
PCT International Classification Number H03K 19/086
PCT International Application Number PCT/EP2004/001615
PCT International Filing date 2004-02-19
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 10319089.9 2003-04-28 Germany