Title of Invention

A CIRCUIT SYSTEM FOR CONTROLLING FIRST AND SECOND INTEGRATED CIRCUIT MEMORY UNITS

Abstract A circuit system comprised a means (102) for controlling a first and a second memory unit by means of a differential control signal. The differential control signal comprises a first control signal and a second control signal which is inverted, to the first control signal. Further, the circuit system comprises a differential control signal line (120) which comprises a first signal line (122) for routing the first control signal and a second signal line (12 4) for routing the second control signal. The first switching unit (104) is connected via the first signal line (122) and the second circuit unit (10 6) is connected via the second signal line (124) to the means (102) for controlling.
Full Text Description
Circuit system
5 The present invention relates to a circuit system, and in
particular to a circuit system having two circuit units
which are controlled by control signals which are inverted
to each other.
10 Circuit systems frequently comprise signals connected to
several circuit units. These signals are strongly
capacitively loaded. This problematic in particular occurs
in computer memory systems.
15 In current DDR1 and DDR2 computer storage systems,
"unbuffered DIMMs" (DIMM = dual in-line memory module) are
used. In those systems, in particular the command/address
bus is very strongly capacitively loaded. On one DIMM up to
18 DRAM devices are arranged, which are either directly, or
20 via a hybrid T topology, connected to a command/address bus
line, which is driven by a memory control unit- A DDR2-
memory system comprises approximately 27 CA signals (CA =
command/address). By the scrong capacitive load the signal
quality on the corresponding signal line deteriorates. In
25 order to achieve a good signal quality on the DIMM in spite-
of this, a certain ratio of signal lines to ground lines is
required. The ratio of CA .signals to ground signals on a
DIMM is usually 2:1. Apart from the CA signals, a CA bus
therefore comprises a plurality of ground signals. This
30 increases the line number of a CA bus to usually
approximately 40 signal and ground lines.
Fig- 4 shows a computer memory system according to the
prior art. A memory control means 4 02 in the form of a
35 "controller" is shown, controlling a plurality of memory
devices 404 in the form of DRAMs. The memory devices 404
are arranged on a memory module 412 in the forth of an
"unbuffered DIMM". The memory devices 404 are connected to

200352887
2
the memory controller 402 via a memory bus. For reason's of
clarity, in Fig. 4 only one single CA signal 420 of the
memory bus is shown.
5 On the memory module 412, the CA signal 42 0 comprises a T
topology. The memory devices 404 are connected to the CA
signal 420 via contact locations 430. Open ends of the CA
signal 420 are terminated on the memory module 412 by line
terminations 432.
10
Both, the memory controller 402 and also the memory module
412 are conventionally arranged on a motherboard (not
shown) of a computer system. The memory controller 402 is
hereby usually part of a chip set (not shown), The memory
15 module 412 conventionally comprises up to 13 memory devices
404 of which for reasons of clarity only four are shown. As
all memory devices 4 04 are controlled by the CA signal 4 20,
the CA signal 420 is substantially capacitively loaded.
Thus, .the signal integrity of the CA signal 420 is a big
20 problem, as the data rate possible on the CA signal 420 is
negative1y inf1uenced.
Fig. 5 shows a possibility for improving the signal
integrity in .a memory means according to the prior art. By
25 this, the data rate in the memory means may be increased.
According to Fig. 4, the memory system in Fig. 5 comprises
a memory controller 502' and a plurality of memory devices
504, 506 arranged on a memory module 512. In this
embodiment, the memory devices 504, 506 are separated into
30 first memory devices 504 and second, memory depices 506
For controlling the first and second memory devices 504,
506, the present embodiment comprises two identical copies
of a CA bus. For reasons of clarity, again only two
35 individual CA signal lines 522, 524 of the two CA buses are
shown. A first CA signal is driven from the memory
controller 502 via a first CA signal line 522. to the first
memory devices 504. A second CA signal is driven from the

200352887
3
memory controller 502 via a second CA signal line 524 to
the second memory devices 506. The. memory devices 504, 506
are connected to the first and the second CA signal line
522, 52 4 via contact locations 530. Free ends of the CA
5 signal lines 522, 524 are each provided with a line
termination 532.
The signal integrity of the first and the second CA signal
line 522, 524 is substantially better in this embodiment
10 than in the embodiment shown in Fig. A, as the capacitive
load on the CA signal lines 522, 524 is halved. This
enables a higher transmission rate on the CA signal lines
522, 524.
15 It is a substantial disadvantage of this embodiment, that-
the number of CA signal lines 522, 524 is doubled as
compared to the embodiment shown in Fig. 4. This results in
a very strong increase in the number of pins of a plug (not
shown) connecting the memory module 512 to the motherboard
20 (not shown). This additionally complicates a signal line
routing on the motherboard. The signal routing is
problematic as the available area in which the signals may
be routed is limited and a cross talk between the signals
hag to be prevented. This becomes even more complicated as
25. all CA receivers simultaneously switch into one direction,
whereby additionally potential interferences are caused,
for example on a reference voltage
The doubling of the CA signals in particular also results
30 in a doubling of the ground signals, as the ratio of ground
signals to CA signals remains the same.
It is an object of the present invention to provide a
circuit system comprising a high signal integrity with a
35 low number of control signals and thereby enabling a high
data transmission rate.

200352887
4
This object is achieved by a circuit system according to
claim 1.
The present invention. provides a circuit system,
5 comprising:
a means for controlling a first, circuit unit and a second
circuit unit by means of a differential control signal,
wherein the differential control signal comprise a first
10 control signal and a second control signal which is
inverted, to the first control signal;
a differential control signal line comprising a first
signal line for routing, the first control signal and a
15 second signal line for routing the second control signal,-
and
wherein the first circuit unit is connected via the first
signal line., and the second circuit unit is connected via
20 the second signal line to means for controllings
The present invention is based on the finding that the
characteristics of a differential signal may advantageously
be used in a circuit system in which several circuit units
25 are controlled by the same signal.
According to the present invention, a means for controlling
provides a differential control signal whose first control
signal line is vised for controlling a first circuit unit
30 and whose second control signal line is used for
controlling a second circuit unit, One advantage of the
differential implementation of the control signals is that
a current feedback path of each of the control signal lines
is routed on the associated complementary control signal
35 line. By this, a signal-to-ground ratio may be reduced
substantially. With an ideal differential line pair, no
ground lines are required. A further advantage is an
improved signal integrity, as on a differential line a risk

200352887
5
due to cross talk is reduced. If a plurality of control
lines is routed next to each other, then in the line
routing a cross talk has to be considered only regarding
half of the control signal lines.
5
In the following, preferred embodiments of the present
invention are explained in more detail with reference to
the accompanying drawings, in which:
10 Fig. 1 shows a block diagram of a circuit system
according to the present invention;
Fig, 1 A shows a schematic illustration of a differential
control signal;
15
Fig. 2 shows a preferred embodiment of a memory system
according to the present invention.
Fig:. 3 shows a circuit system in the form of a memory
20 system according to a further preferred
embodiment of the present invention;
Fig. 4 shows a memory system according to the prior art;
and
25
Fig. 5 shows a. further embodiment of a memory system
according to the prior art.
Fig. 1 shows a block diagram of a circuit system according
30 to the present invention. The circuit system comprises a
means 102 for controlling a first and a second circuit
unit, and a first circuit unit 104, and a second circuit
unit 106. The means 102 for controlling provides a
differential control signal on a differential control
35 signal line 12 0. The differential control signal line 120
comprises a first control signal line 122 and a second
control signal line 124. The first control signal line 122
connects the means 102 for controlling to the first circuit

200352887
6
unit 104 and the second control signal line 124 connects
the means 102 for controlling to the second circuit unit
106.
5 In this embodiment, the means 102 for controlling and the
circuit units 104, 106 are integrated circuits arranged on
a printed circuit board (not shown) . The first control
signal line 122. and the second control signal line 124 of
the differential control signal line 120 are touted on the
10 printed circuit board as close as possible to each other
and in parallel in order to prevent an interfering cross
talk on the printed circuit board. A branching 130 of the
control signal lines 122., 124 is arranged as close as
possible to the circuit units 104, 106,
15
Fig. 1A shows a signal course of a differential control
signal 120' on a differential control signal line as it is
shown in Fig. 1. The differential control signal 120'
comprises a first control signal 122' and a second control
20 signal 124' which is inverted to the first control signal
122', The control signals 122', 124' alternate between a
top voltage- potential VH and a bottom voltage potential VL,
If the first control signal 122' is at the voltage
potential VH, then the complementary second control signal
25 124' is at the low voltage potential VL- With an ideal
differential signal, the voltage potentials VH and VL, are
equal regarding their amount, have different signs,
however, In this case, the ideal differential signal
requires not ground terminal, as the respective
30 complementary signal line guarantees a feedback of the
signal current.
With a non-ideal differential signal, i.e. a signal shifted
with regard to the 0 v level, a feedback of a signal
35 current, is required via an additional ground line (not
shown . The signal current to be fed back is substantially
lower however, than in a non-differential signal
implementation. By this, in a bus system the ratio of

200352887
7
signal lines to ground lines is improved in favor of a
reduction of the ground lines.
Fig. 2 shows a further preferred embodiment of a memory
5 system according to the present invention, recording to the
embodiment shown in Fig. 1, the circuit system shown in
Fig, 2 comprises a means 202 for controlling a first and a.
second circuit unit, and a first circuit unit 204, and a
second circuit unit 206. The means 202 for controlling is-
10 connected to the first circuit unit 204 and the second,
circuit unit 20 6 via a differential control signal line 220
which comprises a first control signal line 222 and a
second control signal line 224. Here, the first circuit
unit 204 is again connected via the first control signal
15 line 222, and the second circuit unit 206 is connected via
the second control signal line 224, to the means 202 for
controlling .
In this embodiment, the circuit units 204, 206 are arranged.
20 on a circuit module 212. The circuit module 212 comprises a
differential input 214. Via this differential input 214,
the memory inddule 212 is connected to the means for
controlling a first and a second circuit unit via the
differential control signal line 220.
25
The second circuit unit 206 comprises a. treats 220 for
adjusting to an inverted control signal, in this embodiment
the second control signal line 224. The means 22 8 is
implemented as a signal which is provided by the means 302
30 for controlling. The second circuit unit 206 is implemented
to adjust to the inverted control signal 224 of the
differential control signal line 220 in response to the
signal 228
35 As an alternative to the signal 228, it is also possible,
after splitting up the differential control signal into the
first control signal and the second control signal, to
arrange an inverter in the second control signal line, A

200352887
8
further alternative possibility is an arrangement of an
inverter in the second circuit unit.
In one memory system which uses MRS commands (MRS = mode
5 register set), there is a further possibility to determine
whether a control line is inverted or not. When
initializing a memory system, in the form of a DRAM, an MRS
Command. is transmitted. Here, the control signals are used
in the form of address signals in order to adjust the MRS
10 registers. Not all address signals are- used, however. Thus,
one or two address signals may be used in order to
determine whether an inverse control signal bus is present
or not. Conventionally, a "1" on the address, signal A12
during the MRS command indicates that the bus is inverted,
15
Fig, 3 shows a further preferred embodiment of the
inventive circuit system in the- form of a memory system.
The memory system comprises a memory controller 302
controlling a. plurality of memory devices 304, 306. The
20 memory devices 304, 306 in the form of DRAMs are arranged
on a. memory module 312 in the form of an "unbuffered DIMM".
The memory module 312 may .be a DDR1, DDR2 or DDR3 memory
module. The memory moduls 312 comprises a differential
input 314 via which the memory module 312 is connected to
25 the memory controller 302 via a differential control signal
320. The differential control signal 320 comprises a first-
control signal 322 and 5 second control signal 324, Via the
first control signal 322, the memory controller 302 is
connected to the first memory devices 304, via the second
30 control signal 324, the memory controller 302 is connected
to the second memory devices 306, The memory devices 304,
306 are connected to the control signal lines 322, 3 24 via
contact locations 330. The control signal lines 322, 324
are terminated via, line terminations 332 at their free
35 ends.
The memory system presents a DDR1, DDR2, or DDR3 memory
system. The memory controller 302, which is part of a chip

200352887
9
set, and the memory module 312 are arranged on a
motherboard (not shown) . The memory module 312 typically
comprises up to 18 memory devices .304, 306. The memory
devices- 304, 306 are connected to the memory controller 302
5 via a memory bus. For reasons of clarity, in Fig. 3 only
four memory devices and only one CA signal of the memory
bus are shown. The inventive approach of a differential CA
control signal line enables a reduction of the ground
signal lines required on the memory module 312. In contrast
10 to the embodiment according to the prior art shown in Fig,
5, whose CA bus includes 80 signals including ground signal
lines. for the inventive embodiment of Fig. 3 only two
times 21 signals are required for the CA bus..
15 An inversion of the second control signal 324 has no
influence on an addressing of the second memory devices
306, as a memory field of the second memory devices 306 is
only written to and read out from another direction. An
inversion of the address signals has effects on a mode
20 register set (not shown) of the second memory devices 306r
however, in which during .an initialization phase
functionality .settings are performed, After an
initialization of the memory devices 304, 306, the mode
register set is adjusted. Here, an inversion of the second
25 control signal 324 has to be considered, by switching off
the inversion during writing a mode register set copimand,
or by informing the second memory device 306 via a, signal
(shown in Fig. 2), whether it is addressed invertedly or
normally, or whether the above indicated solution is used
30 with an address signal, like the address signal A12-

200352887
10
Reference Numerals List
102 means for controlling
104 first circuit unit
5 106 second circuit unit
120 differential control signal line
122 first control signal
124 second control signal
130 branching
10
120 differential control signal
122 first control signal
124 second control signal
15 202 means for controlling
204 first circuit unit
206 second circuit unit
212 circuit module
214 differential input
20 220 differential control signal line
222 first control signal
224 second control signal
228 adjusting means
25 302 memory controller
304 first memory devices
306 second memory devices
312 memory module
314 differential input
30 320 differential control signal line
322 first control signal
324 second control signal
330 contact locations
332 line terminations
35
402 memory controller
404 memory devices
412 memory module

200352887
11
420 CA signal
430 contact location
432 line termination
5 502 memory controller
504 first memory device
506 second memory device
512 memory module
522 first CA signal
10 524 second CA signal
530 contact locations
532 line terminations

200352887
Claims
as attached to IPER - clean copy
1. A circuit system, comprising:
a means (102; 202; 302) for controlling a first circuit
unit (104, 204; 304) and a second circuit unit (106; 206;
306) by means of a differential control signal (120'),
wherein the differential control signal comprises a first
control signal (122') and a second control signal (124')
which is inverted to the first control signal;
a differential control signal line (120; 220; 320)
comprising a first signal line (122; 222; 322) for routing
the first control signal and a second signal line (124;
224; 324) for routing the second control signal; and
wherein the first circuit unit is connected via the first
signal line and not the second signal line, and the second
circuit unit is connected via the second signal line and
not the first signal line, to the means for controlling.
2. The circuit system according to claim 1, wherein the
first circuit unit (204; 304) and the second circuit unit
(206; 306) are arranged on a circuit module (212; 312)
comprising a differential input (214; 314) for connecting
the circuit module to the differential control signal line
(220; 320)
3. The circuit system according to one of claims 1 or 2,
wherein the second circuit unit (206) comprises a means
(228) for adjusting to the second control signal (224),
4. The circuit system according to one of claims 1 or 2,
comprising a means for inverting the second control signal,
which is connected to the second circuit unit, and
providing an inverted second control signal to the second
circuit unit.

200352887
5. The circuit system according to one of claims 1 to 4,
wherein the circuit module is a memory module (312) and the
first and the second circuit unit are a first and a second
memory unit (304, 306).
6. The circuit system according to claim 5, wherein the
differential control signal is a command/address bus signal
(320).

A circuit system comprised a means (102) for controlling a
first and a second memory unit by means of a differential
control signal. The differential control signal comprises a
first control signal and a second control signal which is
inverted, to the first control signal. Further, the circuit
system comprises a differential control signal line (120)
which comprises a first signal line (122) for routing the
first control signal and a second signal line (12 4) for
routing the second control signal. The first switching unit
(104) is connected via the first signal line (122) and the
second circuit unit (10 6) is connected via the second
signal line (124) to the means (102) for controlling.

Documents:

00618-kolnp-2006-abstract.pdf

00618-kolnp-2006-claims.pdf

00618-kolnp-2006-description complete.pdf

00618-kolnp-2006-drawings.pdf

00618-kolnp-2006-form 1.pdf

00618-kolnp-2006-form 2.pdf

00618-kolnp-2006-form 3.pdf

00618-kolnp-2006-form 5.pdf

00618-kolnp-2006-gpa.pdf

00618-kolnp-2006-international publication.pdf

00618-kolnp-2006-international search report.pdf

618-kolnp-2006-granted-abstract.pdf

618-kolnp-2006-granted-claims.pdf

618-kolnp-2006-granted-correspondence.pdf

618-kolnp-2006-granted-description (complete).pdf

618-kolnp-2006-granted-drawings.pdf

618-kolnp-2006-granted-examination report.pdf

618-kolnp-2006-granted-specification.pdf

618-kolnp-2006-granted-translated copy of priority document.pdf

abstract-00618-kolnp-2006.jpg


Patent Number 235971
Indian Patent Application Number 618/KOLNP/2006
PG Journal Number 37/2009
Publication Date 11-Sep-2009
Grant Date 10-Sep-2009
Date of Filing 16-Mar-2006
Name of Patentee INFINEON TECHNOLOGIES AG
Applicant Address ST-MARTIN-STRASSE 53 81669 MUNCHEN
Inventors:
# Inventor's Name Inventor's Address
1 MAKSIM KUZMENKA STOCKENWEG 17 81829 MUNICH
2 HERMANN RUCKERBAUER VELLCHENSTR.1 94554 MOSS
3 SIMON MUFF SUDETENRING 72 86415 MERING
PCT International Classification Number H03K 19/003
PCT International Application Number PCT/EP2004/009061
PCT International Filing date 2004-08-12
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 103 45 384.9 2003-09-30 Germany