Title of Invention

AN SOI-BASED ELECTRO-OPTIC ARRANGEMENT

Abstract The present invention relates to an SOI-based electro-optic arrangement comprising a silicon substrate; a buried dielectric layer; a single crystal silicon (SOI) layer formed using an epitaxial growth process to minimize optical defect density, the single crystal silicon layer disposed over the buried dielectric layer; at least one optical component area formed at least in part in the SOI layer and comprising a thin dielectric layer disposed over a portion of the SOI layer and a silicon layer disposed over the thin dielectric layer so as to overlap in part the SOI layer; at least one electrical component area comprising a thin dielectric layer disposed over a separate portion of the same SOI layer and a heavily-doped gate metal-like silicon layer disposed over the thin dielectric layer wherein one or more optical devices are formed in each of the optical component areas and one or more electrical de3vices are formed in each of the electrical component areas; and a common electrical interconnect arrangement comprising one or more layers of metallization.
Full Text The present invention relates to an SOI-based electro-optic arrangement comprising a silicon substrate; a buried dielectric layer; a single crystal silicon (SOI) layer formed using an epitaxial growth process to minimize optical defect density, the single crystal silicon layer disposed over the buried dielectric layer; at least one optical component area formed at least in part in the SOI layer and comprising a thin dielectric layer disposed over a portion of the SOI layer and a silicon layer disposed over the thin dielectric layer so as to overlap in part the SOI layer; at least one electrical component area comprising a thin dielectric layer disposed over a separate portion of the same SOI layer and a heavily-doped gate metal-like silicon layer disposed over the thin dielectric layer wherein one or more optical devices are formed in each of the optical component areas and one or more electrical de3vices are formed in each of the electrical component areas; and a common electrical interconnect arrangement comprising one or more layers of metallization.

Documents:

2690-chenp-2005 complete specification as granted.pdf

2690-CHENP-2005 CORRESPONDENCE OTHERS.pdf

2690-CHENP-2005 CORRESPONDENCE PO.pdf

2690-chenp-2005 correspondence-others.pdf

2690-CHENP-2005 FORM 1.pdf

2690-CHENP-2005 FORM 13.pdf

2690-CHENP-2005 FORM 18.pdf

2690-CHENP-2005 FORM 3.pdf

2690-CHENP-2005 FORM 5.pdf

2690-chenp-2005 form-3.pdf

2690-CHENP-2005 PCT.pdf

2690-chenp-2005-abstract.jpg

2690-chenp-2005.tif


Patent Number 234393
Indian Patent Application Number 2690/CHENP/2005
PG Journal Number 29/2009
Publication Date 17-Jul-2009
Grant Date 26-May-2009
Date of Filing 19-Oct-2005
Name of Patentee SIOPTICAL, INC
Applicant Address 7540 Windsor Drive, Lower Level, Allentown, Pennsylvania 18195
Inventors:
# Inventor's Name Inventor's Address
1 PATEL, Vipulkumar 607 Falcongate Drive, Monmouth Junction, New Jersey 08852
2 GHIRON, Margaret ; 1875 Sherwood Road, Allentown, PA 18103
3 GOTHOSKAR, Prakash 6749 Windermere Court, Allentown, PA 18104
4 MONTGOMERY, Robert, Keith 810 Howe Street, Easton, Pennsylvania 18040
5 SHASTRI, Kalpendu; 5529 Willow Way, Orefield, Pennsylvania 18069
6 PATHAK, Soham 6099 Palomino Drive, Allentown, PA 18106
7 YANUSHEFSKI, Katherine, A 7487 Stein Road, Zionsville, PA 18092
PCT International Classification Number G02F
PCT International Application Number PCT/US2004/012236
PCT International Filing date 2004-04-21
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 60/464, 491 2003-04-21 U.S.A.
2 10/828,898 2004-04-21 U.S.A.