|Title of Invention||
"A SYSTEM FOR PRE-EMPTING LOW PRIORITY TRAFFIC WITH HIGH PRIORITY TRAFFIC TRANSMITTING DATA BY APPLYING A ONE-TIME PAD"
|Abstract||A method and system for pre-empting a low-priority traffic with high-priority traffic over a serial link utilizes specific codes to delimit a high-priority message embedded within a low-priority message. Reference Fig. : Fig. 3.|
|Full Text||The present invention relates to pre-empting low priority traffic with high-priority traffic transmitting data by applying a one-time pad.
In many systems, a dedicated link carries both low-priority and high-priority traffic.
Low-priority traffic can be lengthy and cause high-priority traffic to incur greater than
A software example of this is type of latency is interrupt processing for microprocessors.
An interrupt causes software to begin execution of an alternate code stream, thereby
delaying normal code processing.
A hardware example of this is the PCI Bus "Latency Timeout" protocol, where a central
arbiter can force a bus master to get off the shared bus to allow another master to
perform a transaction.
In both the software and hardware examples, the time to switch over to the interrupting
transaction can be arbitrary and significant. Accordingly, improved and faster techniques
for switching from low-priority to high-priority traffic on a dedicated link are required.
BRIEF SUMMARY OF THE INVENTION
In one embodiment of the invention, high-priority traffic immediately interrupts low-priority traffic and is embedded within a low-priority data stream.
In another embodiment of the invention, special codes in a transmitted date stream delimit the embedded high-priority traffic from the low-priority traffic. In another embodiment, the transceivers utilize 8B/10B encoding and the delimiting characters for an embedded high-priority data stream are specially designated K characters.
In another embodiment of the invention, if during transmission of low-priority traffic, it is required to transmit high-priority traffic, then transmission of low-priority traffic is paused. A special initial delimiting character is inserted into the data stream to identify the start of a high-priority traffic stream which is followed by the high-priority data stream. When the high-priority traffic transmission is complete a special terminal delimiting character is inserted into the data stream and transmission of the low-priority data stream continues from where it left off immediately after the special delimiting character.
Other features and advantages of the invention will be apparent from the following detailed description and appended drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. I is a block diagram of a system including ASICs coupled by a dedicated serial link:
Fig. 2 is a block diagram of an interface to the serial link:
Fig. 3 is a block diagram of an embodiment of the invention;
Fig. 4 is a flow chart of an embodiment of transmitter processing;
Fig. 5 is a flow chart of an embodiment of receiver side processing;
Fig. 6 is a high-level schematic diagram of a data stream utilizing an embodiment of the
Fig. 7 is a detailed schematic diagram of a data stream utilizing an embodiment of the
DETAILED DESCRIPTION OF THE INVENTION
Reference will now be made in detail to various embodiments of the invention. Examples of the these embodiments are illustrated in the accompanying drawings. While the invention will be described in conjunction with these embodiments, it will be understood that it is not intended to limit the invention to any embodiment. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. However, the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.
A first embodiment will now be described in the context of a supervisor ASIC (application specific integrated circuit), having an embedded microprocessor, coupled to port ASICs by a serial link, designed by the assignee of the present invention, depicted in Fig. 1. In Fig. 1, a supervisor ASIC 10 is coupled to three port ASICs 12a.b. and c bv a dedicated serial link 14.
Fig. 2 is a block diagram of the interface coupled to the serial link 14. The receiver 20 is coupled to a physical coding layer including (PCS) a PCS decoder 22 coupled to the serial link 14 to receive SI (signal in) and SICK (signal in clock) signals. The transmitter 24 is coupled to the PCS including a PCS encoder 26 to transmit SO (signal out) and SOCK (signal out clock) signals.
In this embodiment, a message is a single transaction that occurs over the dedicated link 14 and may have variable length up to 2 KBytes for frame transfers (including frame
data, message header, and frame check sequence (FCS)). A message is initiated by the Supervisor ASIC to convey part or all of a command to one Port ASIC or all the Port ASICs. The command and targeted Port ASICs are identified by the first byte of the message. Further bytes depend on the command type and may be written by either the Port ASIC or Supervisor ASIC.
An example will now be described where the low-priority message is a Frame Transfer, where the Supervisor ASIC 10 moves frames to or from Port ASICs without CPl intervention, and the high-priority message are a Direct Access messages used to control direct access to a Port ASIC's registers and RAM.
Long frame transactions take considerable time on the dedicated serial link. For example, in this embodiment, the maximum frame size is 1518 bytes, having 8bits/byte. and the data transfer rate on the dedicated serial link is I nsS/bit. Therefore the time to transfer this maximum-sized frame would be (1518*8) * 1 nS 12.144 uS. If the dedicated serial link were idle, a large number of register reads or writes could be accomplished in that time period, on the order of 10 or more. If a read is scheduled during a frame transaction then the read is pending until the frame transaction is completed. This pending read tends to stall the microprocessors* progress, so minimal latencies for these reads are desirable. If a register read is issued just after the beginning of a maximum frame size fetch, the read will be stalled for 12.144 uS which results in a significant loss of performance.
To minimize latencies, a mechanism for time sensitive accesses to preempt frame accesses has been developed. A time sensitive Direct has priority over a Frame Access (Frame Transmit Access, or Frame Receive Access). The time sensitive access will always win in arbitrating for an idle management interface, and will embed itself into a Frame Transmit Access or a Frame Receive Access in order to get onto the management interface.
The description of the process for embedding high-priority messages within low-priority messages will now be described. In this embodiment the dedicated link uses 8B/10B encoding/decoding, allowing access to both control and data characters. Thus the PCS encoder and decoder of Fig. 2 are an 8B/I0B encoder and an 8B/10B decoder. As is known by persons of skill in the art. the 8B/10B encoding format encodes 8-bit input data into 10-bit symbols for transmission. The 8-bit blocks are partitioned into 5-bit and 3-bit sub-blocks which are respectively encoded into 6-bit and 4-bit sub-blocks. A prefix of D or K is used to distinguish between data and special characters. A symbol is named by its prefix and the decimal values of its sub-blocks. For example. D3 1.1 is a
data symbol having a first sub-block of (I 1 11 I) which has a decimal value of 31 and a second sub-block of (100) having a decimal value of 1. Note that the LSB is on the left. The disparity of a block of data is defined as the difference between the number of ones and zeros in the block. A positive disparity reflects the excess of Is over 0s. Hach symbol may be encoded in two ways; a primary encoding with a positive disparity and an alternate encoding with a negative disparity. The encoder selects the disparity of the symbol to maintain a running disparity value between 1 and 1 to achieve the goals of maintaining transition density and limited run lengths.
In all SerDes units, after individual bit alignment has been established, the beginning and ending of each symbol being transmitted in a serial data stream must be determined because byte boundaries associated with the parallel data are lost during serialization. Accordingly, as described above, most SerDes units send a series of special characters known as commas.
All of these commas are unique characters within the 8B/10B code that begin with either a II00000XXX or 00lllllXXX. depending on disparity and individual K character rules. These versions are called primary (positive disparity) and alternate (negative-disparity) versions. These commas are sent in a predetermined fashion so that the clock recovery unit can locate the boundaries of the symbols being transmitted by a SerDes unit.
The K characters that include commas are K28.1. K.28.5. and K.28.7. As described above these K characters are transmitted as positive or negative disparity versions depending on the running disparity.
In this embodiment special characters are interpreted by the Physical Coding Layer (PCS) to delimit the beginning and end of an inserted message. These special characters are interpreted by the PCS to delimit and extract embedded high-priority messages from low-priority messages. Table 1 lists the special code groups used in this embodiment of the invention.
Because of the different control characters utilized by high versus low-priority traffic, high-priority traffic streams can be embedded into a low-priority stream by the transmitter. The receiver uses these control characters to extract the high-priority traffic from within the low-priority traffic.
The actions performed at the receiver and transmitter will now be described with reference the block diagram of Fig. 3 and to the flow charts of Figs. 4 and 5. Turning first to Fig. 3, a high-level block diagram of logic 30 for embedding and extracting high-priority data is depicted. A Frame Parallel Manager 32 provides frames to a Frame Tx buffer 34 and receives frames from a Frame Rx buffer 36. A Direct Parallel Manager 38 provides direct data to a Direct Tx buffer 40 and receives direct data from a Direct Rx buffer 42. A Serial Manager 44 has an internal interface connected to the Frame and Direct buffers and a Serial Interface having an input 46 and output 48 coupled to the serial data path (not shown). Internal side inputs are coupled to the outputs of the Frame Tx and Direct Tx buffers 34 and 40 and internal side outputs arc-coupled to the inputs of the Frame Rx and Direct Rx buffers 36 and 42. An Arbiter 50 is coupled to the Frame Tx and Direct Tx buffers 34 and 40 and to the internal outputs of the Serial Manager 44.
The operation of the system of Fig. 3 will now be described. The actions described below with reference to the flow chart can be controlled by state machines in the Arbiter 50. The state machines may be implemented as program code, stored on a computer readable medium, that is executed by a digital computer. The computer readable medium may include, among other things, magnetic media, optical media, electromagnetic fields encoding digital information, and so on.
Turning now to the transmission of data and referring to Fig. 4. if a low-priorit\ (l.P) message is being transmitted, the Serial Manager 44 transfers data from the Frame Fx Buffer 34 to the Serial Interface output line 48. If the Arbiter 50 detects that a high-
priority (HP) message is ready to be transmitted, then the Arbiter 50 controls the Serial
Manager 44 to pause the transmission of the LP message, insert the /P/ character into the
transmitted data stream, and immediately thereafter transfer the direct data of the IIP
message from the Direct Tx Buffer 40 to the Serial Interface output line 48. When the
Arbiter 50 detects that transmission of the HP message is complete then Arbiter 50
controls the Serial Manager 44 to insert the IQI character into the data stream and begin
transferring data from the Frame Tx buffer 34 to the Serial Interface output line 48. The
transmission of the LP message is then continued from the point where the pause took
Turning next to the receiving of data and referring to Fig. 5, during reception of LP data
the Serial Manager 44 transfers data from the Serial Interface input line 46 to the Frame
Rx buffer 36. If the Arbiter 50 detects a /P/ character in the received data stream then
receiving and storing of an LP message is paused and the Arbiter 50 controls the Serial
Manager 44 to transfer the received IIP data between the IYI and /Q/ character to the
Direct Rx buffer 42. Subsequent to the detection of the /Q/ character the Arbiter 50
controls the Serial Manager 44 to transfer data received on the input line 46 of the Serial
Interface to the Frame Rx buffer 36.
An example of embedding a high-priority data stream in a low-priority data stream is
depicted in Fig. 6. In this example. /S/ and /T/ characters delimit low-priority traffic; /P/
and /Q/ characters delimit high-priority traffic. /I/ represents an Idle character.
A more detailed example a data stream utilizing this embodiment of the invention is
depicted in Fig. 7. In this example the input to the supervisor ASIC is depicted in the
SI+/SI- data stream and the output from the supervisor ASIC is depicted in the SO'/SO-
At tl the supervisory ASIC 10 is transmitting a low-priority Transmit Frame Initiate
message when it receives a high-priority Direct Read Response, delimited by the /P/ and
IQI special characters, from one of the port ASICs 12.
At t2 the Supervisor ASIC immediately issues a high-priority Drain Buffer message.
delimited by the /P/and /Q/ special characters, so that a Port ASIC can reclaim the buffer
space used to insert the Direct Read Response Message. Note that the Drain Buffer
message is embedded in the low-priority Transmit Frame Imitate Message.
At t3 the supervisor ASIC follows the Drain Buffer message with a high-priority Direct
Write Initiate message, delimited by the IPI and IQI special characters, which is also
embedded in the original Transmit Frame Initiate message. At t4 the Supervisor ASIC
continues transmitting the low-priority Transmit Frame Initiate message. At t5 the
Supervisor ASIC receives Direct Write response from a Port ASIC and at t6 the Supervisor ASIC issues a Drain Buffer message.
As depicted in Fig. 6, each embedded message is delimited by the /P/ and /Q/ characters. Also, as depicted in Fig. 6. the latency between the receipt of the first byte of a direct message and the transmission of the first delimiting character of the response message is only one clock. Further, there is no delay between the transmission of the final delimiting character of the inserted high-priority data stream and transmission of the paused low-priority data stream.
Thus, in the described system the low-priority data stream doesn't get killed by continuing interruptions by high-priority messages. The low-priority data stream continues be transmitted during intervals between high-priority transmissions. The invention has now been describe with reference to the preferred embodiments. Alternatives and substitutions will now be apparent to persons of ordinary skill in the art. In particular, the 8B/10B decoding scheme is not critical to practicing the invention. Other decoding schemes are feasible that include control characters inserted into a data stream. Further, the particular message types utilized as examples are not critical to practicing the invention.
1. A system that pre-empts low-priority traffic with high-priority traffic over a dedicated link coupling a transmitter (24) to a receiver (20) having encoder (26) and decoder (22), the system comprising:
the transmitter (24), comprising:
a first buffer hereinafter referred to as HPTx buffer for holding high-priority data to be transferred;
a second buffer hereinafter referred to as LPTx buffer for holding low-priority data to be transferred; and
a transmitter controller (50), wherein the transmitter controller is configured to a) in response to receiving an indication that a read operation to be performed on a register or RAM is desired, pause transmission of the low-priority data from the LPTx puffer, b) transmit the high-priority data, delimited by an initial delimiting character and a terminal delimiting character, from the HPTx buffer over the dedicated serial link, and c) continue the transmission of the low-priority data from the point where the transmission of the low-priority data left off, wherein the low-priority data corresponds to a frame transfer, wherein the high-priority data corresponds to a message to control direct access to a register or RAM, and wherein the initial and terminal control characters are selected 8B/10B control characters.
the receiver (20), comprising:
a first buffer hereinafter referred to as HPRx buffer for holding high-priority data being received;
a second buffer hereinafter referred to as LPRx buffer for holding low-priority data being received; and
a receiver controller, having a) receiver data outputs coupled to the HPRx and LPRx buffers, and b) receiver data and control inputs, and wherein the receiver controller is configured to: a) store the low-priority received data stream in the LPRx buffer, b) upon detection of the initial delimiting control character, store the subsequently received high-priority data stream in the HPRx buffer until the detection of the terminal delimiting character, and c) upon detecting of the terminal delimiting character, store the received low-priority data in the LPRx buffer.
3. The system as claimed in Claim 1, wherein the transmitter controller has (a)
transmitter data inputs coupled to the HPTx and LPTx buffers, and (b) transmitter
data and control outputs,
wherein the transmitter comprises an encoder, wherein the encoder has (a) encoder data and control inputs coupled to the transmitter data and control outputs of the transmitter controller, wherein the encoder is configured to generate a control character based on data provided at the transmitter data output of the transmitter controller when the transmitter controller provides a control signal at the transmitter control output, and
wherein the transmitter controller is configured to: a) transmit the low-priority data from the LPTx buffer, b) pause transmission of the low-priority data, c) provide the control signal and a first data word encoding the initial delimiting control character prior to transmitting the high-priority data from the HPTx buffer, d) provide the control signal and a second data word encoding the terminal delimiting control signal, and e) transmit the low-priority data from the LPTx buffer from the point where transmission of the low-priority data left off.
4. The system as claimed in claim 3, wherein the encoder is an 8B/10B encoder.
5. The system as claimed in Claim 1, wherein the receiver comprises a decoder, wherein the decoder has a) decoder data and control outputs coupled to the receiver
data and control inputs of the receiver controller, wherein the decoder is configured to generate a control character based on data provided at the receiver data output of the receiver controller when the receiver controller provides a control signal at the receiver control output; and
wherein the receiver controller is configured to: a) store the low-priority received data stream in the LPRx buffer, b) upon detection of the initial delimiting control character provided by the decoder, store the subsequently received high-priority data stream in the HPRx buffer until the detection of the terminal delimiting character provided by the decoder, and c) upon detecting the terminal delimiting character, store the received low-priority data in the LPRx buffer.
6. The system as claimed in claim 5, wherein the decoder is an 8B/10B decoder.
7. A system for pre-empting low-priority traffic with high-priority traffic over a
dedicated link coupling a transmitter to a receiver as claimed in claim 1, the system
at the transmitter:
means for pausing transmission of a low-priority traffic data stream in
response to receiving an indication that a read operation to be performed on a
register or RAM is desired;
means for transmitting a first special delimiting character marking the
beginning of high-priority message data;
means for transmitting a high-priority traffic data stream over the dedicated
means for transmitting a second special delimiting character when
transmission of the high-priority traffic data stream is completed; and
means for continuing transmission of the low-priority data stream subsequent
to the transmission of the second special delimiting character,
wherein the low-priority data corresponds to a frame transfer,
wherein the high-priority data corresponds to a message to control direct access to a register or RAM, and wherein the first special delimiting character and the second special delimiting character are 8B/10B control characters.
8. The system as claimed in Claim 1, comprising: at the receiver:
means for receiving the low-priority data stream and storing the low-priority
data stream as low-priority message data in a first buffer;
means for, upon detecting the first special delimiting character, storing
subsequent data as high-priority message data in a second buffer until the
second special delimiting character is detected; and
means for storing data received subsequent to detecting the second special
delimiting character as low-priority message data in the first buffer.
9. The system as claimed in claim 1, comprising:
means for detecting whether the first special delimiting character is a first selected 8B/10B control character; and means for detecting whether the second special delimiting character is a second selected 8B/10B control character.
|Indian Patent Application Number||4020/DELNP/2005|
|PG Journal Number||13/2009|
|Date of Filing||07-Sep-2005|
|Name of Patentee||CISCO TECHNOLOGY, INC.,|
|Applicant Address||170 WEST TASMAN DRIVE, SAN JOSE, CA 95134-1706, USA.|
|PCT International Classification Number||H04L 12/64|
|PCT International Application Number||PCT/US2004/008244|
|PCT International Filing date||2004-03-17|