Title of Invention	"AN APPARATUS FOR GENERATING AND CHECKING ERROR DETECTION BITS"
Abstract	An apparatus for generating an error detection information bit sequence for determining a length of data sequence. The apparatus comprises a plurality of cascaded registers and a plurality of adders. During reception of the control information sequence, an operator generates the feedback bit sequence and provides the generated feedback bit sequence to the adders. After completion of receiving it, the operator sequentially adds a preset input bit to output bits of the final register and outputs the result. An initial value controller provides the registers with a selected one of two initial values.

Title of Invention

"AN APPARATUS FOR GENERATING AND CHECKING ERROR DETECTION BITS"

Abstract

An apparatus for generating an error detection information bit sequence for determining a length of data sequence. The apparatus comprises a plurality of cascaded registers and a plurality of adders. During reception of the control information sequence, an operator generates the feedback bit sequence and provides the generated feedback bit sequence to the adders. After completion of receiving it, the operator sequentially adds a preset input bit to output bits of the final register and outputs the result. An initial value controller provides the registers with a selected one of two initial values.

Full Text	[SPECIFICATION] [TITLE OF THE INVENTION] APPARATUS AND METHOD FOR TRANSMITTING/RECEIVING ERROR DETECTION INFORMATION IN A COMMUNICATION SYSTEM [BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 illustrates a structure of a packet data control channel in a mobile communication system to which the present invention is applied; FIG. 2 illustrates a structure of the error detection bit attacher shown in FIG. 1 according to the prior art; FIG. 3 illustrates a structure of a packet data control channel receiver according to the prior art; FIG. 4 illustrates lengths and positions of slots used when detecting a preamble by the receiver of FIG. 3; FIG. 5 illustrates a structure of an error detection information attacher according to an embodiment of the present invention; FIG. 6 illustrates a structure of a packet data control channel receiver according to an embodiment of the present invention; and FIG. 7 illustrates a structure of an apparatus for detecting an error in received bits according to an embodiment of the present invention. [DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT] [OBJECT OF THE INVENTION] [RELATED FIELD AND PRIOR ART OF THE INVENTION] The present invention relates generally to a communication system for packet data transmission, and in particular, to an apparatus and method for attaching error detection information to transmission information before transmission and reception of the transmission information. An IS-2000 CDMA (Code Division Multiple Access) mobile communication system, a typical mobile communication system, supports only a voice service. However, with the development of the communication technology and at the request of users, a future mobile communication system will support a data service as well as the voice service. A mobile communication system supporting a multimedia service including voice and data services provides the voice service to a plurality of users, using the same frequency band. Further, the mobile communication system supports the data service by TDM (Time Division Multiplexing) or TDM/CDM (Time Division Multiplexing/Code Division Multiplexing). The TDM is a technique for assigning one code within a time slot assigned to a specific user. The TDM/CDM is a technique in which a plurality of users simultaneously use one time slot. The users are identified through unique codes (e.g., orthogonal codes such as Walsh codes) assigned to the users. The mobile communication system includes a packet data channel (PDCH) for packet data transmission and a packet data control channel (PDCCH), e.g., secondary packet data control channel (SPDCCH), for efficient transmission of packet data. Packet data is transmitted over the packet data channel. Transmission of packet data on the air is performed in a physical layer packet (PLP) unit, and a length of the physical layer packet is varied at each transmission. The packet data control channel transmits a control information frame needed to allow a receiver to efficiently receive the packet data. A length of the control information frame is changed according to a length of the packet data. Therefore, the receiver can determine a varying length of the packet data by estimating a length of the control information frame. The length of the control information frame is estimated through blind slot detection (BSD). FIG. 1 illustrates a structure of a packet data control channel in a mobile communication system to which the present invention is applied. Referring to FIG. 1, a packet data control channel input sequence, or a control information transmitted over a packet data control channel, is assumed to have 13 bits per N slots (where N=l, 2, or 4). It should be noted that the number of bits included in the control information frame is not related to a length of the control information frame, and not limited to 13. A length of the control information frame transmitted over the packet data control channel depends upon a length of the packet data. For example, if the packet data has one of 1-slot length, 2-slot length, 4-slot length and 8-slot length, then the control information frame has a selected one of 1-slot length, 2-slot length and 4-slot length. For the packet data having a 1-slot length, a control information frame having a 1-slot length is transmitted. For the packet data having a 2-slot length, a control information frame having a 2-slot length is transmitted. For the packet data having a 4-slot length, a control information frame having a 4-slot length is transmitted. For the packet data having an 8-slot length, a control information frame having a 4-slot length is transmitted. The reason for transmitting a control information frame having a 4-slot length even for the packet data having an 8-slot length, is to prevent a preamble length from being excessively increased. Error detection bits are attached by an error detection bit attacher 110 to the control information frame transmitted over the packet data control channel. The error detection bit attacher 110 attaches the error detection bits to the control information frame so that a receiver can detect a transmission error on the control information frame. For example, the error detection bit attacher 110 attaches 8 error detection bits to the 13-bit control information frame and generates 21-bit control information. A CRC (Cyclic Redundancy Code) generator is a typical example of the error detection bit attacher 110. The CRC generator generates CRC information-attached information, by encoding input control information with CRC. If the number of redundancy bits generated by the CRC generator is increased, the capability of detecting a transmission error will be increased. However, the increase in number of the redundancy bits for the control information will reduce power efficiency. Therefore, 8 CRC bits are generally used for the error detection bits. A tail bit attacher 120 attaches tail bits to the control information output from the error detection bit attacher 110. A convolutional encoder 130 encodes the output of the tail bit attacher 120 with a convolutional code, and outputs coded symbols. For example, the tail bit attacher 120 attaches 8 tail bits all having 0's for convolutional encoding by the convolutional encoder 130, and outputs 29-bit information. The convolutional encoder 130 convolutional-encodes a control information frame with a 1-slot length at a coding rate 1/2, and a control information frame with a 2-slot length and a control information frame with a 4-slot length at a coding rate 1/4. The number of symbols in the control information frame convolutional-encoded at the coding rate 1/4 is two times larger than the number of symbols in the control information frame convolutional-encoded at the coding rate 1/2. A symbol repeater 140 repeatedly outputs the symbols obtained by convolutional encoding the control information frame with the 4-slot length so that the number of symbols obtained by convolutional encoding the control information frame with a 4-slot length is two times larger than the number of symbols obtained by convolutional encoding the control information frame with a 2-slot length. As a result, the symbol repeater 140 outputs 58N (where N=l, 2 or 4) symbols. A puncturer 150 punctures ION symbols among the output symbols of the symbol repeater 140 in order to minimize performance degradation and achieve proper rate matching. Therefore, the puncturer 150 outputs 48N symbols. An interleaver 160 interleaves the output symbols of the puncturer 150. The reason for using the interleaver 150 is to reduce a burst error probability by interleaving (or permuting) the order of symbols in order to solve the burst error problem caused by convolutional encoding. A bit reverse interleaver (BRI), a kind of block interleaver, can be used for the interleaver 160. The BRI increases an interval between adjacent symbols, such that the first half of the interleaved symbol sequence is comprised of even-numbered symbols and the second half of the interleaved symbol sequence is comprised of odd-numbered symbols. A modulator 170 modulates the symbols interleaved by the interleaver 160 by QPSK (Quadrature Phase Shift Keying) modulation, and generates modulated symbols for transmission. FIG. 2 illustrates a structure of the error detection bit attacher 110 shown in FIG. 1 according to the prior art. Illustrated in FIG. 2 is an example of a CRC generator for attaching 8 CRC bits to input control information. Referring to FIG. 2, the error detection bit attacher 110 includes a plurality of registers 211-218, a plurality of adders 221~224, switches SW1~SW3, and an initial value controller 230. The initial value controller 230 initializes values of the registers 211~218 to "1" when packet data with a length of 1, 2 and 4 slots is transmitted. In contrast, the initial value controller 230 initializes values of the registers 211~218 to "0" when packet data with a length of 8 slots is transmitted. Since both a length of the control information frame corresponding to the packet data with a 4-slot length and a length of the control information frame corresponding to the packet data with an 8-slot length are equally 4 slots, the receiver cannot recognize a length of the packet data although it estimates a length of the control information frame. Therefore, when the error bit detection attacher 110 generates redundant bits (or error detection bits) for a control information frame corresponding to the packet data with a 4-slot length and a control information frame corresponding to the packet data with an 8-slot length, the initial value controller 230 sets initial values of the registers 211~218 to different values as stated above, so that the receiver can recognize through decoding whether the packet data with a 4-slot length and the packet data with an 8-slot length have been transmitted. After the values of the registers 211~218 are initialized, a binary operation is performed by the output adder 225 between each bit of the input control information frame and a value obtained by right-shifting the values of the registers 211~218, and the operation result value is provided as output control information. During this operation, the switches SW1-SW3 are all switched to their upper terminals. After the above operation is performed on all bits of the 13-bit control information frame, the switches SW1-SW3 are switched to their lower terminals, so the switches SW1 and SW2 are provided with a value "0." Thereafter, 8 redundant bits are attached by shifting register values as many times as the number, 8, of the redundant bit. FIG. 3 illustrates a structure of a packet data control channel receiver according to the prior art, and FIG. 4 illustrates lengths and positions of slots used when detecting a control information frame by the receiver of FIG. 3. In particular, FIG. 3 illustrates a structure of a receiver for detecting a length of packet data by detecting a control information frame transmitted over a packet data control channel by BSD. The receiver corresponds to the packet data control channel transmitter in which a CRC generator is used as an error detection bit attacher. The receiver includes CRC checkers corresponding to the CRC generator in the transmitter. Referring to FIG. 3, the receiver includes 4 reception processing blocks 310-340 for detecting a length of packet data. The reception processing block 310 is a block for processing a control information frame with a 1-slot length corresponding to packet data with a 1-slot length, the reception processing block 320 is a block for processing a control information frame with a 2-slot length corresponding to packet data with a 2-slot length, the reception processing block 330 is a block for processing a control information frame with a 4-slot length corresponding to packet data with a 4-slot length, and the reception processing block 340 is a block for processing a control information frame with a 4-slot length corresponding to packet data with an 8-slot length. In the reception processing blocks 310~340, deinterleavers 312, 322, 332 and 342 perform deinterleaving as much as the corresponding slot lengths, and depuncturers 314, 324, 334 and 344 perform depuncturing according to the corresponding slot lengths. In the reception processing blocks 330 and 340 for the control information frame with the 4-slot length, symbol combiners 335 and 345 perform symbol combining on 2 adjacent symbols, which is a reverse operation of the symbol repetition performed by the symbol repeater 140 of FIG. 1. After the depuncturing is performed in the reception processing blocks 310 and 320 and the symbol combining is performed in the reception processing blocks 330 and 340, convolutional decoders 316, 326, 336 and 346 in the reception processing blocks 310~340 perform convolutional decoding. The convolutional decoder 316 for the control information frame with the 1-slot length convolutional-decodes an output of the depuncturer 314 at a coding rate 1/2. The convolutional decoder 326 for the control information frame with the 2-slot length convolutional-decodes an output of the depuncturer 324 at a coding rate 1/4. Likewise, the convolutional decoders 336 and 346 for the control information frame with the 4-slot length convolutional-decode outputs of the symbol combiners 335 and 345 at a coding rate 1/4, respectively. In final stages of the reception processing blocks 310~340, CRC checkers 318, 328, 338 and 348 are arranged. The CRC checkers 318, 328, 338 and 348 perform CRC checking on the symbols convolutional-decoded by the convolutional decoders 316, 326, 336 and 346, respectively. By the CRC checking by the CRC checkers 318, 328, 338 and 348, it is determined whether a CRC error exists in the control information frame transmitted from the transmitter. During the CRC checking, the CRC checkers 318, 328, 338 and 348 use the initial values "1" or "0" previously determined as described in conjunction with FIG. 2. That is, the CRC checker 318 detects a CRC error by setting an initial value of a decoder register to "1," the CRC checker 328 detects a CRC error by setting an initial value of a decoder register to "1," the CRC checker 338 detects a CRC error by setting an initial value of a decoder register to "1," and the CRC checker 348 detects a CRC error by setting an initial value of a decoder register to "0." A packet length detector 350 detects a length of packet data based on the reception processing results by the reception processing blocks 310~340. Here, the 4 reception processing blocks 310~340 can be realized with either physically separated reception processing blocks or a single reception processing block using different reception parameters. In the receiver of FIG. 3, as a result of CRC decoding, if three reception processing blocks have errors and one reception processing block has no error, it is judged that as much packet data as a length corresponding to the error-free reception processing block was transmitted. However, if it is reported that two or more reception processing blocks have no error or all reception processing blocks have no error, it is not possible to determine which control information frame was transmitted, resulting in a failure to receive packet data. The receiver that detects a control information frame by the BSD, has the following problems in a process of detecting a 2-slot control information frame and a 4-slot control information frame corresponding to 4-slot packet data. Referring again to FIG. 1, a 2-slot control information frame and a 4-slot control information frame corresponding to 4-slot packet data have the same CRC register's register initial value, and are encoded by a convolutional code with a coding rate 1/4. Next, the 4-slot control information frame undergoes symbol repetition, thus increasing twice in number of symbols, whereas the 2-slot control information frame does not undergo symbol repetition. Thereafter, a coded symbol sequence of the 2-slot control information frame and a coded symbol sequence of the 4-slot control information frame undergo puncturing and interleaving. When the 4-slot control information frame undergoes BRI interleaving, although the 2-slot control information frame and the 4-slot control information frame have different puncturing patterns, a considerable part of the symbol-repeated information is separately inserted in the first two slots and the last two slots. Therefore, if the reception processing block 320 for the 2-slot control information frame, illustrated in FIG. 3, receives the 4-slot control information frame transmitted, it is judged that the 4-slot control information frame was correctly received with no CRC error. For example, when the 4-slot control information frame is transmitted, the convolutional decoder 326 in the reception processing block 320 for the 2-slot control information frame and the convolutional decoder 336 in the reception processing block 330 for the 4-slot control information frame generate the same number, 10000, of decoded symbols, i.e., the same CRC decoding results, at 2(1) and 4(1) of CRC success in a row 4(1) of SPDCCH (CRC) in Table 1 obtained by an experiment. Accordingly, it is judged during CRC decoding that there is no error. As a result, it is not possible to determine a length of the packet data. The same problem occurs even when the 2-slot control information frame is transmitted. When the 2-slot control information frame is transmitted, the reception processing block 330 for the 4-slot control information frame receives information on the 2-slot control information frame, combined with information on 2 previous slots or noises. Since an interleaving pattern and a puncturing patter for the 2-slot control information frame are similar to an interleaving pattern and a puncturing patter for the 4-slot control information frame, it is judged that there is no error, even when CRC decoding on the 2-slot control information frame is performed by the reception processing block 330 for the 4-slot control information frame. For example, when the 2-slot control information frame is transmitted, the convolutional decoder 326 in the reception processing block 320 for the 2-slot control information frame and the convolutional decoder 336 in the reception processing block 330 for the 4-slot control information frame generate the almost same number, 10000 and 7902, of decoded symbols, i.e., the almost same CRC decoding results, at 2(1) and 4(1) of CRC success in a row 2(1) of SPDCCH (CRC) in Table 1. Accordingly, it is judged during CRC decoding that there is no error. As a result, it is not possible to determine a length of the packet data. In addition, as the outputs of the convolutional decoders 326 and 336 are identical to each other, information bits of the received control information frame, for example, information bits indicating a user to which the control information frame was transmitted, or retransmission-relation information bits, are also equally received at the reception processing block 320 for the 2-slot control information frame and the reception processing block 330 for the 4-slot control information frame. Therefore, although the information bits in the control information frame are used, it is not possible to distinguish a slot length of the control information frame. As a result, it is not possible to determine a length of the packet data. Such a problem is shown in Table 1. Table 1 illustrates simulation results obtained by transmitting each of control information frames with a slot length of 1(1), 2(1), 4(1) and 4(0) 10,000 times in a noise-free state. Here, "1" and "0" in the parenthesis indicate initial values to which all registers in the CRC generator are initialized. The result values obtained through the computer simulation include a successful detection probability Pd, a false probability Pfa of recognizing an incorrect slot length as a correct slot length, a mis-probability Pm of mistaking a correct slot length for an incorrect slot length, and an error probability Pe, the sum of the false probability Pfa and the mis-probability Pm. It is noted in Table 1 that the error probability Pe in detecting a control information frame comprised of 2(1) slots and 4(1) slots is abnormally high. Table 1 (Table Removed) [SUBSTANTIAL MATTER OF THE INVENTION] It is, therefore, an object of the present invention to provide an apparatus and method for attaching error detection information to transmission information in a communication system. It is another object of the present invention to provide an apparatus and method for attaching corresponding error detection information to transmission information blocks having different lengths in a communication system. It is further another object of the present invention to provide an apparatus and method for attaching error detection information to control information of packet data in a communication system for transmitting the packet data. It is yet another object of the present invention to provide an apparatus and method for receiving control information of packet data and analyzing the received control information in a communication system for transmitting the packet data. It is still another object of the present invention to provide a control information frame transceiver apparatus and method for efficiently estimating a length of a control information frame transmitted over a packet data control channel by BSD (Blind Slot Detection) in a communication system for transmitting packet data. In accordance with an aspect of the present invention, there is provided an apparatus for attaching error detection information to first information or second information, in a communication system which encodes the first information with a first length at a predetermined coding rate before transmission, or encodes the second information with a second length being F times the first length at the predetermined coding rate before F-time repeated transmission. The apparatus comprises a plurality of cascaded registers, the number of the registers being identical to the number of bits in the error detection information, and a controller. The controller provides a first initial value for the first information or a second initial value for the second information according to a length of transmission information as a value for initializing the registers. The first initial value is different from the second initial value. The registers are initialized to corresponding initial values provided from the controller and generate the error detection information to be attached to the transmission information while sequentially shifting the initial values until transmission of the transmission information is completed. [CONSTRUCTION AND OPERATION OF THE INVENTION] A preferred embodiment of the present invention will be described herein below with reference to the accompanying drawings wherein like reference numerals designate like elements. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. In the following description, the present invention provides a packet data control channel transceiver for transmitting and receiving control information for controlling packet data in a mobile communication system for transmitting packet data. It will be assumed herein that the control information includes a control information frame (e.g., preamble) indicating a length of packet data, and the packet data control channel is a secondary packet data control channel (SPDCCH). A transmitter according to an embodiment of the present invention includes an error detection information attacher for attaching an information bit sequence for error detection to the control information before transmission so that a receiver can determine whether the transmitted control data is correctly received. In the embodiment of the present invention, a CRC (Cyclic Redundancy Code) generator is typically used as the error detection information attacher. A receiver according to an embodiment of the present invention is a BSD (Blind Slot Detection) receiver for receiving control data transmitted from the transmitter and determining a length of packet data based on the received control data. The transmitter and the receiver according to an embodiment of the present invention can be applied not only to the mobile communication system but also to a communication system for transmitting control information indicating a length of data transmitted for efficient transmission of the data. In order to distinguish control information frames with different lengths caused by the structural problem of the conventional packet data control channel, a preferred embodiment of the present invention provides an improved CRC generator and a BSD receiver for correcting an error generated in a control information frame received by BSD. The embodiment of the present invention sets different register initial values of the CRC generator not only in control information frames with the same length but also in control information frames with different lengths, thus to correct an error generated in a control information frame received by BSD. That is, although the outputs of the convolutional decoders become identical to one another in the reception processing blocks for the control information frames with different lengths of FIG. 3, the embodiment differently sets register initial values of the CRC generator so that only one reception processing block can judge that the CRC decoder has no error, thereby making it possible to determine a length of a control information frame. FIG. 5 illustrates a structure of an error detection information attacher according to an embodiment of the present invention. The error detection information attacher constitutes the error detection bit attacher 110 of FIG. 1, and corresponds to the CRC generator illustrated in FIG. 2. The CRC generator of FIG. 2 differently sets register initial values thereof only when control information frames have the same length, i.e., when a control information frame for 4-slot packet data and a control information frame for 8-slot packet data both have a length of 4 slots. However, the CRC generator according to the present invention sets different register initial values for control information frames of the control channel supporting packet data with different lengths regardless of a length of a control information frame. For example, when 8 error detection bits are attached to a control information frame, 8 registers constituting the CRC generator are arbitrarily set to "1" or "0." When the initial values are expressed in a decimal number, the 8 registers are set to a decimal initial value between 0 and 255 (=28-l). That is, if the number of registers constituting the CRC generator (or the number of redundant information bits for error detection) is defined as "m," initial values of the registers in the CRC generator can be set to a decimal value between 0 and 2m-l. For example, initial values Nl, N2, N3 and N4 of registers in the CRC generator, to be used when transmitting a 1-slot control information frame for 1-slot packet data, a 2-slot control information frame for 2-slot packet data, a 4-slot control information frame for 4-slot packet data, and a 4-slot control information frame for 8-slot packet data, respectively, can be set to a value between 0 and 255. Here, Nl, N2, N3 and N4 can be set to different values. Alternatively, Nl can be set to the same value as N2, N3 or N4. This is because it is allowable to set only the N2 and N3, which were at issue in the conventional CRC generator, to different values. Of course, the N1-N4 values may be set to a fixed value. Referring to FIG. 5, the error detection information attacher according to an embodiment of the present invention includes a plurality of registers 211-218, a plurality of adders 221~225, switches SW1~SW3, and an initial value controller 400. The initial value controller 400 initializes values of the registers 211-218 to Nl when packet data with a 1-slot length is transmitted. The initial value controller 400 initializes values of the registers 211-218 to N2 when packet data with a 2-slot length is transmitted. The initial value controller 400 initializes values of the registers 211-218 to N3 when packet data with a 4-slot length is transmitted. The initial value controller 400 initializes values of the registers 211-218 to N4 when packet data with an 8-slot length is transmitted. After the values of the registers are initialized, a binary operation is performed by the output adder 225 between each bit of the input control information and a value finally obtained from the register 218 by right-shifting the values of the registers, and the operation result value is generated as output control information. During this operation, the switches SW1-SW3 are all switched to their upper terminals. After the above operation is performed on all bits of the 13-bit control information, the switches SW1-SW3 are switched to their lower terminals, so the switches SWl and SW2 are provided with a value "0." Thereafter, 8 redundant bits are attached by shifting register values as many times as the number, 8, of the redundant bit. The error detection information attacher according to an embodiment of the present invention is designed to solve the problems of the conventional CRC generator. That is, even when a control information frame with a 2-slot length indicating transmission of packet data with a 2-slot length is transmitted and a control information frame with a 4-slot length indicating transmission of packet data with a 4-slot length is transmitted, the receiver can detect a length of a control information frame and a length of the transmitted packet data through normal error detection. Therefore, the error detection information attacher will be described with reference to FIGs. 1 and 5. In a communication system which encodes (or convolutional-encodes) first information with a first length (e.g., packet data with a 2-slot length) at a predetermined coding rate (e.g., a coding rate 1/4) before transmission, or encodes second information with a second length being F times the first length (e.g., packet data with a 4-slot length) at the predetermined coding rate before F-time repeated transmission, the error detection information attacher according to an embodiment of the present invention attaches error detection information to the first information or the second information. The error detection information attacher includes the initial value controller 400 and an error detection information generator. The error detection information generator is comprised of a plurality of registers 211~218, a plurality of adders 221~224, a first switch SWl, a second switch SW2, and a third switch SW3. The initial value controller 400 receives information on a length (N slots) of transmission packet data, and provides the registers 211~218 with proper initial values according to the information on a length of the transmission packet data. For example, the initial value controller 400 provides a first initial value during transmission of the first information and provides a second initial value during transmission of the second information. The first initial value and the second initial value are determined within a range of a value corresponding to the number of the error detection information bits. If the number of error detection information bits is defined as m, the first initial value and the second initial value are differently determined within a range of 2m-l. The error detection information generator includes a plurality of cascaded registers, the number of which is identical to the number of the error detection information bits. The error detection information generator initializes the registers to the corresponding initial values provided from the initial value controller before transmitting transmission information of the first information and the second information. The error detection information generator sequentially shifts the registers while transmitting the transmission information. In addition, the error detection information generator sequentially shifts the registers after completing transmission of the transmission information. At this point, an output value of the final register 218 is generated as the error detection information to be attached to the transmission information. The registers 211-218 include the initial register 211, intermediate registers 212-217 and the final register 218, each of which has a signal input terminal, a signal output terminal, and an initial value input terminal connected to receive an initial value from the initial value controller 400. The initial register 211, the intermediate registers 212~218 and the final register 218 are cascaded. Output values of the registers 211, 213, 214 and 217 corresponding to predetermined paths among the paths of the registers 211~218 are added to an output value of the output adder 225 or a preset value (e.g., "0") by the adders 221~224, respectively, and then provided to their succeeding registers 212, 214, 215 and 218. Positions of the adders 221~224 are so determined as to satisfy a predefined generator polynomial for generating CRC (Cyclic Redundancy Check) information. When the transmission information is transmitted, the adder 225 in the error detection information generator adds each bit of the transmission information to the output value of the final register 218, and provides its output to the signal input terminal of the initial register 211. When transmission of the transmission information is completed, the output adder 225 adds the output value of the final register 218 to the preset value "0" and provides its output as the error detection information. For this operation, the switches SW1~SW3 are provided. The first switch SW1 has a first input terminal for receiving the transmission information, a second input terminal for receiving the preset value "0," and an output terminal connected to a first input terminal of the adder 225. The first switch SW1 selects the transmission information received through the first input terminal or the preset value "0" received through the second input terminal, and outputs the selected value through the output terminal. The second switch SW2 has a first input terminal connected to an output terminal of the adder 225, a second input terminal for receiving the preset value "0," and an output terminal connected to an input terminal of the initial register 211. The second switch SW2 selects the output of the adder 225 received through the first input terminal or the preset value "0" received through the second input terminal, and outputs the selected value through the output terminal. The third switch SW3 has a first input terminal connected to the output terminal of the first switch, a second input terminal connected to the output terminal of the adder 225, and an output terminal for outputting the transmission information and the error detection information. The third switch SW3 selects the transmission information or the preset value "0" received through the first input terminal or the output of the adder 225 received through the second input terminal, and outputs the selected value through the output terminal. FIG. 6 illustrates a structure of a packet data control channel receiver according to an embodiment of the present invention. This receiver is identical in structure to the BSD receiver illustrated in FIG. 3, but different from the BSD receiver in that register initial values of the CRC generator are set by CRC checkers. That is, the receiver according to an embodiment of the present invention is characterized in that 4 reception processing blocks use different CRC generator register initial values when performing CRC checking. The receiver is based on BSD. Here, the "BSD" refers to a technique for detecting a length of transmitted packet data by estimating in a slot unit a received control information frame for the packet data transmitted from a transmitter. For example, as illustrated in FIG. 4, it is determined in a (k+3)th slot whether a 1-slot control information frame has been received, and it is determined in a (k+2)th slot whether a 2-slot control information frame has been successively received from the previous (k+3) slot. It is determined in a k slot whether a 4-slot control information frame for 4-slot packet data or a 4-slot control information frame for 8-slot packet data has been successively received from the previous (k+3)th slot, (k+2)th slot and (k+l)th slot. During the operation of detecting the control information frames, error detection information (CRC information) is checked, and initial values used for CRC checking on each control information frame are set to Nl, N2, N3 and N4 as described in conjunction with FIG. 5. Referring to FIG. 6, the receiver includes 4 reception processing blocks 510~540 in order to detect a length of packet data transmitted from the receiver. The reception processing blocks 510~540, after receiving an input signal, determines where a CRC error exists in the received input signal, thereby to determine a length of packet data. Here, the received input signal, comprised of demodulated soft decision values, is a control information frame having a length determined according to the number of information bits of packet data that can be transmitted by the transmitter. Here, a typical example of the information bits is 13-bit information on SPDCCH, and the 13-bit information includes 6-bit MAC (Medium Access Control) ID (Identifier), 2-bit ARQ (Automatic Response Request) channel ID, 3-bit encoder packet size, and 2-bit sub-packet ID. The reception processing block 510 is a block for processing a control information frame with a 1-slot length corresponding to packet data with a 1-slot length, the reception processing block 520 is a block for processing a control information frame with a 2-slot length corresponding to packet data with a 2-slot length, the reception processing block 530 is a block for processing a control information frame with a 4-slot length corresponding to packet data with a 4-slot length, and the reception processing block 540 is a block for processing a control information frame with a 4-slot length corresponding to packet data with an 8-slot length. In the reception processing blocks 510~540, deinterleavers 312, 322, 332 and 342 perform deinterleaving as much as the corresponding slot lengths, and depuncturers 314, 324, 334 and 344 perform depuncturing according to the corresponding slot lengths. In the reception processing blocks 530 and 540 for the control information frame with the 4-slot length, symbol combiners 335 and 345 perform symbol combining on 2 adjacent symbols, which is a reverse operation of the symbol repetition performed by the symbol repeater 140 of FIG. 1. After the depuncturing is performed in the reception processing blocks 510 and 520 and the symbol combining is performed in the reception processing blocks 530 and 540, convolutional decoders 316, 326, 336 and 346 in the reception processing blocks 510~540 perform convolutional decoding. The convolutional decoder 316 for the control information frame with the 1-slot length convolutional-decodes an output of the depuncturer 314 at a coding rate 1/2. The convolutional decoder 326 for the control information frame with the 2-slot length convolutional-decodes an output of the depuncturer 324 at a coding rate 1/4. Likewise, the convolutional decoders 336 and 346 for the control information frame with the 4-slot length convolutional-decode outputs of the symbol combiners 335 and 345 at a coding rate 1/4, respectively. In final stages of the reception processing blocks 510~540, CRC checkers 518, 528, 538 and 548 are arranged. The CRC checkers 518, 528, 538 and 548 perform CRC checking on the symbols convolutional-decoded by the convolutional decoders 316, 326, 336 and 346, respectively. By the CRC checking by the CRC checkers 318, 328, 338 and 348, it is determined whether a CRC error exists in the control information frame transmitted from the transmitter. Although separate CRC checkers are separately included in the reception processing blocks in FIG. 6, it would be obvious to those skilled in the art that the reception processing blocks can share a single CRC checker using different register initial values as illustrated in FIG. 7. During the CRC checking, the CRC checkers 518, 528, 538 and 548 use predetermined initial values provided from the initial value controller 400 as described in conjunction with FIG. 5. That is, the CRC checker 518 detects a CRC error by setting an initial value of a decoder register to Nl, the CRC checker 528 detects a CRC error by setting an initial value of a decoder register to N2, the CRC checker 538 detects a CRC error by setting an initial value of a decoder register to N3, and the CRC checker 548 detects a CRC error by setting an initial value of a decoder register to N4. A packet length detector 350 detects a length of packet data based on the reception processing results by the reception processing blocks 510~540. Here, the 4 reception processing blocks 510~540 can be realized with either physically separated reception processing blocks or a single reception processing block using different reception parameters. FIG. 7 illustrates a structure of an apparatus for detecting an error in received bits according to an embodiment of the present invention. The error detection apparatus corresponds to the error detection bit generator illustrated in FIG. 5, and has the same operation as the error detection bit generator except that received bits are applied to an input terminal of the first switch SW1. The error detection apparatus according to an embodiment of the present invention is designed to solve the problems of the conventional receiver. That is, even when a control information frame with a 2-slot length indicating transmission of packet data with a 2-slot length is received and a control information frame with a 4-slot length indicating transmission of packet data with a 4-slot length is received, the receiver can detect a length of a control information frame and a length of the transmitted packet data through normal error detection. Referring to FIG. 7, the error detection apparatus according to an embodiment of the present invention is designed to detect an error in received bits in the receiver which receives information transmitted from a transmitter which attaches, before transmission, error detection information to transmission information (e.g., a control information frame of packet data) of first information with a first length (e.g., a control information frame with a 2-slot length) or second information with a second length being F times (e.g., 2 times) the first length (e.g., a control information frame with a 4-slot length). The error detection apparatus includes a plurality of registers 561~568, an initial value controller 550, and an error decision block 580. The initial value controller 550 provides a first initial value for the first information and provides a second initial value for the second information in order to initialize the registers. The provided initial values are determined according to a length (N slots) of the packet data. Preferably, the first initial value and the second initial value are determined within a range of a value corresponding to the number of the attached error detection information bits. The registers 561~568, the number of which is identical to the number of the attached error detection information bits, are cascaded and initialized to corresponding initial values provided from the initial value controller 550. In addition, the registers 561~568 generates error detection information (for example, CRC information) while sequentially shifting the initial values until the first information or the second information contained in the reception information has been received. After the first information or the second information has been received, the error decision block 580 compares the generated error detection information with the attached error detection information contained in the reception information, thus to determine whether an error exists in the received bits. That is, the error decision block 580 decides that no error exists in the received bits, if the generated error detection information is identical to the attached error detection information. Otherwise, if the generated error detection information is not identical to the attached error detection information, the error decision block 580 decides that an error exists in the received bits. As described above, in the error detection apparatus of FIG. 7, the initial value controller 550 operates according to a length of the packet data. When first 13 bits of the received bits transmitted from the transmitter are completely received, the switches SW1~SW3 are switched to their lower terminals, so the switches SW1 and SW2 are provided with the preset input bit "0." Thereafter, 8 error detection bits (or redundant bits) are generated by shifting register values as many times as the number, 8, of the error detection bits. The error detection block 580 compares error detection bits (attached by the transmitter) included in the received bits with newly generated error detection bits. The error detection block 580 decides that no error exists in the received bits, if the error detection bits included in the received bits are identical to the newly generated error detection bits. However, if the error detection bits included in the received bits are not identical to the newly generated error detection bits, the error detection block 580 decides that an error exists in the received bits. Although the initial value controller 550 and the error detection block 580 are separately constructed in this embodiment, the elements may be realized with a single controller. Table 2 illustrates simulation results obtained by transmitting each of control information frames with a slot length of 1(2), 2(4), 4(255) and 4(0) 10,000 times in a noise-free state. Here, numerals in the parenthesis represent initial values of the CRC generator in decimal. In the simulation, the register initial value is set to Nl=2, for a control information frame with a 1-slot length. The register initial value is set to N2=4, for a control information frame with a 2-slot length. The register initial value is set to N3=255, for a control information frame with a 4-slot length corresponding to packet data with a 4-slot length. The register initial value is set to N4=0, for a control information frame with a 4-slot length corresponding to packet data with an 8-slot length. The result values obtained through the computer simulation include a successful detection probability Pd, a false probability Pfa, a mis-probability Pm, and an error probability Pe, the sum of the false probability Pfa and the mis-probability Pm. It is noted in Table 2 that the error probability Pe in detecting a control information frame comprised of 2(4) slots and 4(255) slots is abnormally high as shown in Table 1. Table 2 (Table Removed) While the invention has been shown and described with reference to a certain preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. [EFFECTS OF THE INVENTION] As described above, the mobile communication system for transmitting packet data sets different CRC generator register initial values not only in control information frames with the same length but also in control information frames with different lengths in transmitting and receiving signals on the packet data control channel, making it possible to solve a problem that an error is generated during reception of a control information frame by BSD. WE CLAIM: 1. An apparatus for generating error detection bits in a communication system that transmits data having a 1-slot length, a 2-slot length, or a 4-slot length through a data channel, the apparatus comprising: an error detection bit attaching device adapted to generate error detection bits for control information using an initial value corresponding to a length of the control information from among first, second and third initial values, attach the error detection bits to the control information, and output the control information with the attached error detection bits, the first initial value corresponding to a 1-slot length, the second initial value corresponding to a 2-slot length and being equal to the first initial value, and the third initial value corresponding to a 4-slot length and being different from the second initial value; and a transmitting device adapted to transmit over a control channel control data that includes the control information and the error detection bits. wherein the error detection bit attaching device comprises: a plurality of shift registers, the number of which corresponds to a length of the error detection bits, connected in series to each other; a plurality of adders adapted to add feedback bits to bits of the output values of the shift registers input through an input path, and output , the bits with the added feedback bits through an output path, the address positioned among the shift registers according to a generator polynomial an operator adapted to generate the feedback bits by sequentially adding bits of a final shift register in the series of the plurality of shift registers to the bits of the control information during the input of the control information, provide the generated feedback bits to the adders and the initial register in the sequence of the shift registers , and output the error detection bits by sequentially adding a first preset bit to the bits of the final shift registers when the input of the control information is completed; and an initial value controller adapted to store the first to third initial values and provide bits of one initial value selected according to the length of the control information to the shift registers . 2. The apparatus as claimed in claim 1, wherein the control information has the same length as that of the data. 3. The apparatus as claimed in claim 1 wherein the operator comprises: a first switch adapted to selectively output, one of the bits of the control information and the first preset bit; an output adder adapted to add the bits of the final shift register to an output of the first switch; a second switch adapted to selectively provide one of a second preset bit and an output of the output adder as the feedback bits to the plurality of adders and the initial register in the sequence of the shift registers; and a third switch adapted to selectively output one of the control information and the output of the output adder as the error detection bits 4. The apparatus as claimed in claim 3, wherein the first switch adapts to output the bits of the control information during the input of the control information, and output, the first preset bit when the input of the control information is completed. 5. The apparatus as claimed in claim 4 wherein the second switch adapts to provide, the output of the output adder to the plurality of adders and the initial register during the input of the control information, and provide, the second preset bit to the adders and the initial register when the input of the control information is completed. 6. The apparatus as claimed in claim 1, wherein the first preset bit has a value of "0". 7. The apparatus as claimed in claim 3, wherein each of the first and second preset bits has a value of "0". 8. The apparatus as claimed in claim 4, wherein the first preset bit has a value of "0". 9. The apparatus as claimed in claim 5, wherein the second preset bit has a value of "0". 10. The apparatus as claimed in claim 5, wherein the third switch adapts to output the bits of the control information during the input of the control information, and output the error detection bits when the input of the control information is completed. 11. The apparatus for checking error detection bits for control information in a communication system which transmits a data having a 1-slot length, a 2-slot length, or a 4-slot length through a data channel, the apparatus comprising: a receiving device adapted to receive control data including control information representing information related to the data and error detection bits attached to the control information through a control channel; and an error detection bit checking device adapted to check the error detection bits by receiving the control data as an input and using an initial value corresponding to length of the control information from among first, second and third initial values, the first initial value corresponding to an 1-slot length, the second initial value corresponding to a 2-slot length and being equal to the first initial value, and the third initial value corresponding to a 4- slot length and being different from the second initial value. wherein the error detection bit checking device comprises: a plurality of shift registers, the number of which corresponds to a length of the error detection bits, connected in series to each other; a plurality of adders adapted to add feedback bits to bits of the output values of the shift registers inputted through an input path, and output the bits with the added feedback bits through an output path, the adders being positioned among the shift registers according to generator polynomial; an operator adapted to generate the feedback bits by sequentially adding bits of a final shift register in the series of the plurality of shift registers to the bits of the control information during the input of the control information, provide the generated feedback bits to the adders and the initial register in the sequence of the shift registers, and detect the error detection bits by sequentially adding a first preset bit to the bits of the final shift register when the input of the control information is completed; an initial value controller adapted to store the first to third initial values and provide bits of one initial value selected according to length of the control information to the shift registers; and an error determining module for determining if the control information is erroneous by comparing the received error detection bits with the detected error detection bits. 12. The apparatus as claimed in claim 11 wherein the control information has the same length as that of the data.

Full Text

[SPECIFICATION]
[TITLE OF THE INVENTION]
APPARATUS AND METHOD FOR TRANSMITTING/RECEIVING
ERROR DETECTION INFORMATION IN A COMMUNICATION SYSTEM
[BRIEF DESCRIPTION OF THE DRAWINGS]
FIG. 1 illustrates a structure of a packet data control channel in a mobile communication system to which the present invention is applied;
FIG. 2 illustrates a structure of the error detection bit attacher shown in FIG. 1 according to the prior art;
FIG. 3 illustrates a structure of a packet data control channel receiver according to the prior art;
FIG. 4 illustrates lengths and positions of slots used when detecting a preamble by the receiver of FIG. 3;
FIG. 5 illustrates a structure of an error detection information attacher according to an embodiment of the present invention;
FIG. 6 illustrates a structure of a packet data control channel receiver according to an embodiment of the present invention; and
FIG. 7 illustrates a structure of an apparatus for detecting an error in received bits according to an embodiment of the present invention.
[DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT]
[OBJECT OF THE INVENTION]
[RELATED FIELD AND PRIOR ART OF THE INVENTION]
The present invention relates generally to a communication system for packet data transmission, and in particular, to an apparatus and method for attaching error detection information to transmission information before transmission and reception of the transmission information.
An IS-2000 CDMA (Code Division Multiple Access) mobile

communication system, a typical mobile communication system, supports only a voice service. However, with the development of the communication technology and at the request of users, a future mobile communication system will support a data service as well as the voice service.
A mobile communication system supporting a multimedia service including voice and data services provides the voice service to a plurality of users, using the same frequency band. Further, the mobile communication system supports the data service by TDM (Time Division Multiplexing) or TDM/CDM (Time Division Multiplexing/Code Division Multiplexing). The TDM is a technique for assigning one code within a time slot assigned to a specific user. The TDM/CDM is a technique in which a plurality of users simultaneously use one time slot. The users are identified through unique codes (e.g., orthogonal codes such as Walsh codes) assigned to the users.
The mobile communication system includes a packet data channel (PDCH) for packet data transmission and a packet data control channel (PDCCH), e.g., secondary packet data control channel (SPDCCH), for efficient transmission of packet data. Packet data is transmitted over the packet data channel. Transmission of packet data on the air is performed in a physical layer packet (PLP) unit, and a length of the physical layer packet is varied at each transmission. The packet data control channel transmits a control information frame needed to allow a receiver to efficiently receive the packet data. A length of the control information frame is changed according to a length of the packet data. Therefore, the receiver can determine a varying length of the packet data by estimating a length of the control information frame. The length of the control information frame is estimated through blind slot detection (BSD).
FIG. 1 illustrates a structure of a packet data control channel in a mobile communication system to which the present invention is applied.

Referring to FIG. 1, a packet data control channel input sequence, or a control information transmitted over a packet data control channel, is assumed to have 13 bits per N slots (where N=l, 2, or 4). It should be noted that the number of bits included in the control information frame is not related to a length of the control information frame, and not limited to 13. A length of the control information frame transmitted over the packet data control channel depends upon a length of the packet data. For example, if the packet data has one of 1-slot length, 2-slot length, 4-slot length and 8-slot length, then the control information frame has a selected one of 1-slot length, 2-slot length and 4-slot length. For the packet data having a 1-slot length, a control information frame having a 1-slot length is transmitted. For the packet data having a 2-slot length, a control information frame having a 2-slot length is transmitted. For the packet data having a 4-slot length, a control information frame having a 4-slot length is transmitted. For the packet data having an 8-slot length, a control information frame having a 4-slot length is transmitted. The reason for transmitting a control information frame having a 4-slot length even for the packet data having an 8-slot length, is to prevent a preamble length from being excessively increased.
Error detection bits are attached by an error detection bit attacher 110 to the control information frame transmitted over the packet data control channel. The error detection bit attacher 110 attaches the error detection bits to the control information frame so that a receiver can detect a transmission error on the control information frame. For example, the error detection bit attacher 110 attaches 8 error detection bits to the 13-bit control information frame and generates 21-bit control information. A CRC (Cyclic Redundancy Code) generator is a typical example of the error detection bit attacher 110. The CRC generator generates CRC information-attached information, by encoding input control information with CRC. If the number of redundancy bits generated by the CRC generator is increased, the capability of detecting a transmission error will be increased.

However, the increase in number of the redundancy bits for the control information will reduce power efficiency. Therefore, 8 CRC bits are generally used for the error detection bits.
A tail bit attacher 120 attaches tail bits to the control information output from the error detection bit attacher 110. A convolutional encoder 130 encodes the output of the tail bit attacher 120 with a convolutional code, and outputs coded symbols. For example, the tail bit attacher 120 attaches 8 tail bits all having 0's for convolutional encoding by the convolutional encoder 130, and outputs 29-bit information. The convolutional encoder 130 convolutional-encodes a control information frame with a 1-slot length at a coding rate 1/2, and a control information frame with a 2-slot length and a control information frame with a 4-slot length at a coding rate 1/4. The number of symbols in the control information frame convolutional-encoded at the coding rate 1/4 is two times larger than the number of symbols in the control information frame convolutional-encoded at the coding rate 1/2. A symbol repeater 140 repeatedly outputs the symbols obtained by convolutional encoding the control information frame with the 4-slot length so that the number of symbols obtained by convolutional encoding the control information frame with a 4-slot length is two times larger than the number of symbols obtained by convolutional encoding the control information frame with a 2-slot length. As a result, the symbol repeater 140 outputs 58N (where N=l, 2 or 4) symbols.
A puncturer 150 punctures ION symbols among the output symbols of the symbol repeater 140 in order to minimize performance degradation and achieve proper rate matching. Therefore, the puncturer 150 outputs 48N symbols. An interleaver 160 interleaves the output symbols of the puncturer 150. The reason for using the interleaver 150 is to reduce a burst error probability by interleaving (or permuting) the order of symbols in order to solve the burst error problem caused by convolutional encoding. A bit reverse interleaver (BRI), a

kind of block interleaver, can be used for the interleaver 160. The BRI increases an interval between adjacent symbols, such that the first half of the interleaved symbol sequence is comprised of even-numbered symbols and the second half of the interleaved symbol sequence is comprised of odd-numbered symbols. A modulator 170 modulates the symbols interleaved by the interleaver 160 by QPSK (Quadrature Phase Shift Keying) modulation, and generates modulated symbols for transmission.
FIG. 2 illustrates a structure of the error detection bit attacher 110 shown in FIG. 1 according to the prior art. Illustrated in FIG. 2 is an example of a CRC generator for attaching 8 CRC bits to input control information.
Referring to FIG. 2, the error detection bit attacher 110 includes a plurality of registers 211-218, a plurality of adders 221~224, switches SW1~SW3, and an initial value controller 230. The initial value controller 230 initializes values of the registers 211~218 to "1" when packet data with a length of 1, 2 and 4 slots is transmitted. In contrast, the initial value controller 230 initializes values of the registers 211~218 to "0" when packet data with a length of 8 slots is transmitted. Since both a length of the control information frame corresponding to the packet data with a 4-slot length and a length of the control information frame corresponding to the packet data with an 8-slot length are equally 4 slots, the receiver cannot recognize a length of the packet data although it estimates a length of the control information frame. Therefore, when the error bit detection attacher 110 generates redundant bits (or error detection bits) for a control information frame corresponding to the packet data with a 4-slot length and a control information frame corresponding to the packet data with an 8-slot length, the initial value controller 230 sets initial values of the registers 211~218 to different values as stated above, so that the receiver can recognize through decoding whether the packet data with a 4-slot length and the packet data with an

8-slot length have been transmitted. After the values of the registers 211~218 are initialized, a binary operation is performed by the output adder 225 between each bit of the input control information frame and a value obtained by right-shifting the values of the registers 211~218, and the operation result value is provided as output control information. During this operation, the switches SW1-SW3 are all switched to their upper terminals. After the above operation is performed on all bits of the 13-bit control information frame, the switches SW1-SW3 are switched to their lower terminals, so the switches SW1 and SW2 are provided with a value "0." Thereafter, 8 redundant bits are attached by shifting register values as many times as the number, 8, of the redundant bit.
FIG. 3 illustrates a structure of a packet data control channel receiver according to the prior art, and FIG. 4 illustrates lengths and positions of slots used when detecting a control information frame by the receiver of FIG. 3. In particular, FIG. 3 illustrates a structure of a receiver for detecting a length of packet data by detecting a control information frame transmitted over a packet data control channel by BSD. The receiver corresponds to the packet data control channel transmitter in which a CRC generator is used as an error detection bit attacher. The receiver includes CRC checkers corresponding to the CRC generator in the transmitter.
Referring to FIG. 3, the receiver includes 4 reception processing blocks 310-340 for detecting a length of packet data. The reception processing block 310 is a block for processing a control information frame with a 1-slot length corresponding to packet data with a 1-slot length, the reception processing block 320 is a block for processing a control information frame with a 2-slot length corresponding to packet data with a 2-slot length, the reception processing block 330 is a block for processing a control information frame with a 4-slot length corresponding to packet data with a 4-slot length, and the reception processing

block 340 is a block for processing a control information frame with a 4-slot length corresponding to packet data with an 8-slot length.
In the reception processing blocks 310~340, deinterleavers 312, 322, 332 and 342 perform deinterleaving as much as the corresponding slot lengths, and depuncturers 314, 324, 334 and 344 perform depuncturing according to the corresponding slot lengths. In the reception processing blocks 330 and 340 for the control information frame with the 4-slot length, symbol combiners 335 and 345 perform symbol combining on 2 adjacent symbols, which is a reverse operation of the symbol repetition performed by the symbol repeater 140 of FIG. 1. After the depuncturing is performed in the reception processing blocks 310 and 320 and the symbol combining is performed in the reception processing blocks 330 and 340, convolutional decoders 316, 326, 336 and 346 in the reception processing blocks 310~340 perform convolutional decoding. The convolutional decoder 316 for the control information frame with the 1-slot length convolutional-decodes an output of the depuncturer 314 at a coding rate 1/2. The convolutional decoder 326 for the control information frame with the 2-slot length convolutional-decodes an output of the depuncturer 324 at a coding rate 1/4. Likewise, the convolutional decoders 336 and 346 for the control information frame with the 4-slot length convolutional-decode outputs of the symbol combiners 335 and 345 at a coding rate 1/4, respectively. In final stages of the reception processing blocks 310~340, CRC checkers 318, 328, 338 and 348 are arranged. The CRC checkers 318, 328, 338 and 348 perform CRC checking on the symbols convolutional-decoded by the convolutional decoders 316, 326, 336 and 346, respectively. By the CRC checking by the CRC checkers 318, 328, 338 and 348, it is determined whether a CRC error exists in the control information frame transmitted from the transmitter. During the CRC checking, the CRC checkers 318, 328, 338 and 348 use the initial values "1" or "0" previously determined as described in conjunction with FIG. 2. That is, the CRC

checker 318 detects a CRC error by setting an initial value of a decoder register to "1," the CRC checker 328 detects a CRC error by setting an initial value of a decoder register to "1," the CRC checker 338 detects a CRC error by setting an initial value of a decoder register to "1," and the CRC checker 348 detects a CRC error by setting an initial value of a decoder register to "0." A packet length detector 350 detects a length of packet data based on the reception processing results by the reception processing blocks 310~340. Here, the 4 reception processing blocks 310~340 can be realized with either physically separated reception processing blocks or a single reception processing block using different reception parameters.
In the receiver of FIG. 3, as a result of CRC decoding, if three reception processing blocks have errors and one reception processing block has no error, it is judged that as much packet data as a length corresponding to the error-free reception processing block was transmitted. However, if it is reported that two or more reception processing blocks have no error or all reception processing blocks have no error, it is not possible to determine which control information frame was transmitted, resulting in a failure to receive packet data.
The receiver that detects a control information frame by the BSD, has the following problems in a process of detecting a 2-slot control information frame and a 4-slot control information frame corresponding to 4-slot packet data.
Referring again to FIG. 1, a 2-slot control information frame and a 4-slot control information frame corresponding to 4-slot packet data have the same CRC register's register initial value, and are encoded by a convolutional code with a coding rate 1/4. Next, the 4-slot control information frame undergoes symbol repetition, thus increasing twice in number of symbols, whereas the 2-slot control information frame does not undergo symbol repetition. Thereafter, a

coded symbol sequence of the 2-slot control information frame and a coded symbol sequence of the 4-slot control information frame undergo puncturing and interleaving.
When the 4-slot control information frame undergoes BRI interleaving, although the 2-slot control information frame and the 4-slot control information frame have different puncturing patterns, a considerable part of the symbol-repeated information is separately inserted in the first two slots and the last two slots. Therefore, if the reception processing block 320 for the 2-slot control information frame, illustrated in FIG. 3, receives the 4-slot control information frame transmitted, it is judged that the 4-slot control information frame was correctly received with no CRC error. For example, when the 4-slot control information frame is transmitted, the convolutional decoder 326 in the reception processing block 320 for the 2-slot control information frame and the convolutional decoder 336 in the reception processing block 330 for the 4-slot control information frame generate the same number, 10000, of decoded symbols, i.e., the same CRC decoding results, at 2(1) and 4(1) of CRC success in a row 4(1) of SPDCCH (CRC) in Table 1 obtained by an experiment. Accordingly, it is judged during CRC decoding that there is no error. As a result, it is not possible to determine a length of the packet data.
The same problem occurs even when the 2-slot control information frame is transmitted. When the 2-slot control information frame is transmitted, the reception processing block 330 for the 4-slot control information frame receives information on the 2-slot control information frame, combined with information on 2 previous slots or noises. Since an interleaving pattern and a puncturing patter for the 2-slot control information frame are similar to an interleaving pattern and a puncturing patter for the 4-slot control information frame, it is judged that there is no error, even when CRC decoding on the 2-slot control information frame is performed by the reception processing block 330 for

the 4-slot control information frame. For example, when the 2-slot control information frame is transmitted, the convolutional decoder 326 in the reception processing block 320 for the 2-slot control information frame and the convolutional decoder 336 in the reception processing block 330 for the 4-slot control information frame generate the almost same number, 10000 and 7902, of decoded symbols, i.e., the almost same CRC decoding results, at 2(1) and 4(1) of CRC success in a row 2(1) of SPDCCH (CRC) in Table 1. Accordingly, it is judged during CRC decoding that there is no error. As a result, it is not possible to determine a length of the packet data.
In addition, as the outputs of the convolutional decoders 326 and 336 are identical to each other, information bits of the received control information frame, for example, information bits indicating a user to which the control information frame was transmitted, or retransmission-relation information bits, are also equally received at the reception processing block 320 for the 2-slot control information frame and the reception processing block 330 for the 4-slot control information frame. Therefore, although the information bits in the control information frame are used, it is not possible to distinguish a slot length of the control information frame. As a result, it is not possible to determine a length of the packet data.
Such a problem is shown in Table 1. Table 1 illustrates simulation results obtained by transmitting each of control information frames with a slot length of 1(1), 2(1), 4(1) and 4(0) 10,000 times in a noise-free state. Here, "1" and "0" in the parenthesis indicate initial values to which all registers in the CRC generator are initialized. The result values obtained through the computer simulation include a successful detection probability Pd, a false probability Pfa of recognizing an incorrect slot length as a correct slot length, a mis-probability Pm of mistaking a correct slot length for an incorrect slot length, and an error probability Pe, the sum of the false probability Pfa and the mis-probability Pm. It

is noted in Table 1 that the error probability Pe in detecting a control information frame comprised of 2(1) slots and 4(1) slots is abnormally high.
Table 1

(Table Removed)
[SUBSTANTIAL MATTER OF THE INVENTION]
It is, therefore, an object of the present invention to provide an apparatus and method for attaching error detection information to transmission information in a communication system.
It is another object of the present invention to provide an apparatus and method for attaching corresponding error detection information to transmission information blocks having different lengths in a communication system.
It is further another object of the present invention to provide an apparatus and method for attaching error detection information to control
information of packet data in a communication system for transmitting the packet data.
It is yet another object of the present invention to provide an apparatus and method for receiving control information of packet data and analyzing the received control information in a communication system for transmitting the packet data.
It is still another object of the present invention to provide a control information frame transceiver apparatus and method for efficiently estimating a length of a control information frame transmitted over a packet data control channel by BSD (Blind Slot Detection) in a communication system for transmitting packet data.
In accordance with an aspect of the present invention, there is provided an apparatus for attaching error detection information to first information or second information, in a communication system which encodes the first information with a first length at a predetermined coding rate before transmission, or encodes the second information with a second length being F times the first length at the predetermined coding rate before F-time repeated transmission. The apparatus comprises a plurality of cascaded registers, the number of the registers being identical to the number of bits in the error detection information, and a controller. The controller provides a first initial value for the first information or a second initial value for the second information according to a length of transmission information as a value for initializing the registers. The first initial value is different from the second initial value. The registers are initialized to corresponding initial values provided from the controller and generate the error detection information to be attached to the transmission information while sequentially shifting the initial values until transmission of the transmission information is completed.
[CONSTRUCTION AND OPERATION OF THE INVENTION]
A preferred embodiment of the present invention will be described herein below with reference to the accompanying drawings wherein like reference numerals designate like elements. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.
In the following description, the present invention provides a packet data control channel transceiver for transmitting and receiving control information for controlling packet data in a mobile communication system for transmitting packet data. It will be assumed herein that the control information includes a control information frame (e.g., preamble) indicating a length of packet data, and the packet data control channel is a secondary packet data control channel (SPDCCH). A transmitter according to an embodiment of the present invention includes an error detection information attacher for attaching an information bit sequence for error detection to the control information before transmission so that a receiver can determine whether the transmitted control data is correctly received. In the embodiment of the present invention, a CRC (Cyclic Redundancy Code) generator is typically used as the error detection information attacher. A receiver according to an embodiment of the present invention is a BSD (Blind Slot Detection) receiver for receiving control data transmitted from the transmitter and determining a length of packet data based on the received control data. The transmitter and the receiver according to an embodiment of the present invention can be applied not only to the mobile communication system but also to a communication system for transmitting control information indicating a length of data transmitted for efficient transmission of the data.
In order to distinguish control information frames with different lengths caused by the structural problem of the conventional packet data control channel,

a preferred embodiment of the present invention provides an improved CRC generator and a BSD receiver for correcting an error generated in a control information frame received by BSD. The embodiment of the present invention sets different register initial values of the CRC generator not only in control information frames with the same length but also in control information frames with different lengths, thus to correct an error generated in a control information frame received by BSD. That is, although the outputs of the convolutional decoders become identical to one another in the reception processing blocks for the control information frames with different lengths of FIG. 3, the embodiment differently sets register initial values of the CRC generator so that only one reception processing block can judge that the CRC decoder has no error, thereby making it possible to determine a length of a control information frame.
FIG. 5 illustrates a structure of an error detection information attacher according to an embodiment of the present invention. The error detection information attacher constitutes the error detection bit attacher 110 of FIG. 1, and corresponds to the CRC generator illustrated in FIG. 2. The CRC generator of FIG. 2 differently sets register initial values thereof only when control information frames have the same length, i.e., when a control information frame for 4-slot packet data and a control information frame for 8-slot packet data both have a length of 4 slots. However, the CRC generator according to the present invention sets different register initial values for control information frames of the control channel supporting packet data with different lengths regardless of a length of a control information frame. For example, when 8 error detection bits are attached to a control information frame, 8 registers constituting the CRC generator are arbitrarily set to "1" or "0." When the initial values are expressed in a decimal number, the 8 registers are set to a decimal initial value between 0 and 255 (=28-l). That is, if the number of registers constituting the CRC generator (or the number of redundant information bits for error detection) is defined as "m," initial values of the registers in the CRC generator can be set to a decimal value

between 0 and 2m-l. For example, initial values Nl, N2, N3 and N4 of registers in the CRC generator, to be used when transmitting a 1-slot control information frame for 1-slot packet data, a 2-slot control information frame for 2-slot packet data, a 4-slot control information frame for 4-slot packet data, and a 4-slot control information frame for 8-slot packet data, respectively, can be set to a value between 0 and 255. Here, Nl, N2, N3 and N4 can be set to different values. Alternatively, Nl can be set to the same value as N2, N3 or N4. This is because it is allowable to set only the N2 and N3, which were at issue in the conventional CRC generator, to different values. Of course, the N1-N4 values may be set to a fixed value.
Referring to FIG. 5, the error detection information attacher according to an embodiment of the present invention includes a plurality of registers 211-218, a plurality of adders 221~225, switches SW1~SW3, and an initial value controller 400. The initial value controller 400 initializes values of the registers 211-218 to Nl when packet data with a 1-slot length is transmitted. The initial value controller 400 initializes values of the registers 211-218 to N2 when packet data with a 2-slot length is transmitted. The initial value controller 400 initializes values of the registers 211-218 to N3 when packet data with a 4-slot length is transmitted. The initial value controller 400 initializes values of the registers 211-218 to N4 when packet data with an 8-slot length is transmitted.
After the values of the registers are initialized, a binary operation is performed by the output adder 225 between each bit of the input control information and a value finally obtained from the register 218 by right-shifting the values of the registers, and the operation result value is generated as output control information. During this operation, the switches SW1-SW3 are all switched to their upper terminals. After the above operation is performed on all bits of the 13-bit control information, the switches SW1-SW3 are switched to

their lower terminals, so the switches SWl and SW2 are provided with a value "0." Thereafter, 8 redundant bits are attached by shifting register values as many times as the number, 8, of the redundant bit.
The error detection information attacher according to an embodiment of the present invention is designed to solve the problems of the conventional CRC generator. That is, even when a control information frame with a 2-slot length indicating transmission of packet data with a 2-slot length is transmitted and a control information frame with a 4-slot length indicating transmission of packet data with a 4-slot length is transmitted, the receiver can detect a length of a control information frame and a length of the transmitted packet data through normal error detection. Therefore, the error detection information attacher will be described with reference to FIGs. 1 and 5.
In a communication system which encodes (or convolutional-encodes) first information with a first length (e.g., packet data with a 2-slot length) at a predetermined coding rate (e.g., a coding rate 1/4) before transmission, or encodes second information with a second length being F times the first length (e.g., packet data with a 4-slot length) at the predetermined coding rate before F-time repeated transmission, the error detection information attacher according to an embodiment of the present invention attaches error detection information to the first information or the second information. The error detection information attacher includes the initial value controller 400 and an error detection information generator. The error detection information generator is comprised of a plurality of registers 211~218, a plurality of adders 221~224, a first switch SWl, a second switch SW2, and a third switch SW3.
The initial value controller 400 receives information on a length (N slots) of transmission packet data, and provides the registers 211~218 with proper

initial values according to the information on a length of the transmission packet data. For example, the initial value controller 400 provides a first initial value during transmission of the first information and provides a second initial value during transmission of the second information. The first initial value and the second initial value are determined within a range of a value corresponding to the number of the error detection information bits. If the number of error detection information bits is defined as m, the first initial value and the second initial value are differently determined within a range of 2m-l.
The error detection information generator includes a plurality of cascaded registers, the number of which is identical to the number of the error detection information bits. The error detection information generator initializes the registers to the corresponding initial values provided from the initial value controller before transmitting transmission information of the first information and the second information. The error detection information generator sequentially shifts the registers while transmitting the transmission information. In addition, the error detection information generator sequentially shifts the registers after completing transmission of the transmission information. At this point, an output value of the final register 218 is generated as the error detection information to be attached to the transmission information.
The registers 211-218 include the initial register 211, intermediate registers 212-217 and the final register 218, each of which has a signal input terminal, a signal output terminal, and an initial value input terminal connected to receive an initial value from the initial value controller 400. The initial register 211, the intermediate registers 212~218 and the final register 218 are cascaded. Output values of the registers 211, 213, 214 and 217 corresponding to predetermined paths among the paths of the registers 211~218 are added to an output value of the output adder 225 or a preset value (e.g., "0") by the adders

221~224, respectively, and then provided to their succeeding registers 212, 214, 215 and 218. Positions of the adders 221~224 are so determined as to satisfy a predefined generator polynomial for generating CRC (Cyclic Redundancy Check) information.
When the transmission information is transmitted, the adder 225 in the error detection information generator adds each bit of the transmission information to the output value of the final register 218, and provides its output to the signal input terminal of the initial register 211. When transmission of the transmission information is completed, the output adder 225 adds the output value of the final register 218 to the preset value "0" and provides its output as the error detection information. For this operation, the switches SW1~SW3 are provided.
The first switch SW1 has a first input terminal for receiving the transmission information, a second input terminal for receiving the preset value "0," and an output terminal connected to a first input terminal of the adder 225. The first switch SW1 selects the transmission information received through the first input terminal or the preset value "0" received through the second input terminal, and outputs the selected value through the output terminal. The second switch SW2 has a first input terminal connected to an output terminal of the adder 225, a second input terminal for receiving the preset value "0," and an output terminal connected to an input terminal of the initial register 211. The second switch SW2 selects the output of the adder 225 received through the first input terminal or the preset value "0" received through the second input terminal, and outputs the selected value through the output terminal. The third switch SW3 has a first input terminal connected to the output terminal of the first switch, a second input terminal connected to the output terminal of the adder 225, and an output terminal for outputting the transmission information and the error

detection information. The third switch SW3 selects the transmission information or the preset value "0" received through the first input terminal or the output of the adder 225 received through the second input terminal, and outputs the selected value through the output terminal.
FIG. 6 illustrates a structure of a packet data control channel receiver according to an embodiment of the present invention. This receiver is identical in structure to the BSD receiver illustrated in FIG. 3, but different from the BSD receiver in that register initial values of the CRC generator are set by CRC checkers. That is, the receiver according to an embodiment of the present invention is characterized in that 4 reception processing blocks use different CRC generator register initial values when performing CRC checking. The receiver is based on BSD. Here, the "BSD" refers to a technique for detecting a length of transmitted packet data by estimating in a slot unit a received control information frame for the packet data transmitted from a transmitter. For example, as illustrated in FIG. 4, it is determined in a (k+3)th slot whether a 1-slot control information frame has been received, and it is determined in a (k+2)th slot whether a 2-slot control information frame has been successively received from the previous (k+3) slot. It is determined in a k slot whether a 4-slot control information frame for 4-slot packet data or a 4-slot control information frame for 8-slot packet data has been successively received from the previous (k+3)th slot, (k+2)th slot and (k+l)th slot. During the operation of detecting the control information frames, error detection information (CRC information) is checked, and initial values used for CRC checking on each control information frame are set to Nl, N2, N3 and N4 as described in conjunction with FIG. 5.
Referring to FIG. 6, the receiver includes 4 reception processing blocks 510~540 in order to detect a length of packet data transmitted from the receiver. The reception processing blocks 510~540, after receiving an input signal,

determines where a CRC error exists in the received input signal, thereby to determine a length of packet data. Here, the received input signal, comprised of demodulated soft decision values, is a control information frame having a length determined according to the number of information bits of packet data that can be transmitted by the transmitter. Here, a typical example of the information bits is 13-bit information on SPDCCH, and the 13-bit information includes 6-bit MAC (Medium Access Control) ID (Identifier), 2-bit ARQ (Automatic Response Request) channel ID, 3-bit encoder packet size, and 2-bit sub-packet ID. The reception processing block 510 is a block for processing a control information frame with a 1-slot length corresponding to packet data with a 1-slot length, the reception processing block 520 is a block for processing a control information frame with a 2-slot length corresponding to packet data with a 2-slot length, the reception processing block 530 is a block for processing a control information frame with a 4-slot length corresponding to packet data with a 4-slot length, and the reception processing block 540 is a block for processing a control information frame with a 4-slot length corresponding to packet data with an 8-slot length. In the reception processing blocks 510~540, deinterleavers 312, 322, 332 and 342 perform deinterleaving as much as the corresponding slot lengths, and depuncturers 314, 324, 334 and 344 perform depuncturing according to the corresponding slot lengths. In the reception processing blocks 530 and 540 for the control information frame with the 4-slot length, symbol combiners 335 and 345 perform symbol combining on 2 adjacent symbols, which is a reverse operation of the symbol repetition performed by the symbol repeater 140 of FIG. 1. After the depuncturing is performed in the reception processing blocks 510 and 520 and the symbol combining is performed in the reception processing blocks 530 and 540, convolutional decoders 316, 326, 336 and 346 in the reception processing blocks 510~540 perform convolutional decoding. The convolutional decoder 316 for the control information frame with the 1-slot length convolutional-decodes an output of the depuncturer 314 at a coding rate 1/2. The

convolutional decoder 326 for the control information frame with the 2-slot length convolutional-decodes an output of the depuncturer 324 at a coding rate 1/4. Likewise, the convolutional decoders 336 and 346 for the control information frame with the 4-slot length convolutional-decode outputs of the symbol combiners 335 and 345 at a coding rate 1/4, respectively.
In final stages of the reception processing blocks 510~540, CRC checkers 518, 528, 538 and 548 are arranged. The CRC checkers 518, 528, 538 and 548 perform CRC checking on the symbols convolutional-decoded by the convolutional decoders 316, 326, 336 and 346, respectively. By the CRC checking by the CRC checkers 318, 328, 338 and 348, it is determined whether a CRC error exists in the control information frame transmitted from the transmitter. Although separate CRC checkers are separately included in the reception processing blocks in FIG. 6, it would be obvious to those skilled in the art that the reception processing blocks can share a single CRC checker using different register initial values as illustrated in FIG. 7. During the CRC checking, the CRC checkers 518, 528, 538 and 548 use predetermined initial values provided from the initial value controller 400 as described in conjunction with FIG. 5. That is, the CRC checker 518 detects a CRC error by setting an initial value of a decoder register to Nl, the CRC checker 528 detects a CRC error by setting an initial value of a decoder register to N2, the CRC checker 538 detects a CRC error by setting an initial value of a decoder register to N3, and the CRC checker 548 detects a CRC error by setting an initial value of a decoder register to N4. A packet length detector 350 detects a length of packet data based on the reception processing results by the reception processing blocks 510~540. Here, the 4 reception processing blocks 510~540 can be realized with either physically separated reception processing blocks or a single reception processing block using different reception parameters.

FIG. 7 illustrates a structure of an apparatus for detecting an error in received bits according to an embodiment of the present invention. The error detection apparatus corresponds to the error detection bit generator illustrated in FIG. 5, and has the same operation as the error detection bit generator except that received bits are applied to an input terminal of the first switch SW1. The error detection apparatus according to an embodiment of the present invention is designed to solve the problems of the conventional receiver. That is, even when a control information frame with a 2-slot length indicating transmission of packet data with a 2-slot length is received and a control information frame with a 4-slot length indicating transmission of packet data with a 4-slot length is received, the receiver can detect a length of a control information frame and a length of the transmitted packet data through normal error detection.
Referring to FIG. 7, the error detection apparatus according to an embodiment of the present invention is designed to detect an error in received bits in the receiver which receives information transmitted from a transmitter which attaches, before transmission, error detection information to transmission information (e.g., a control information frame of packet data) of first information with a first length (e.g., a control information frame with a 2-slot length) or second information with a second length being F times (e.g., 2 times) the first length (e.g., a control information frame with a 4-slot length). The error detection apparatus includes a plurality of registers 561~568, an initial value controller 550, and an error decision block 580.
The initial value controller 550 provides a first initial value for the first information and provides a second initial value for the second information in order to initialize the registers. The provided initial values are determined according to a length (N slots) of the packet data. Preferably, the first initial value and the second initial value are determined within a range of a value corresponding to the number of the attached error detection information bits.

The registers 561~568, the number of which is identical to the number of the attached error detection information bits, are cascaded and initialized to corresponding initial values provided from the initial value controller 550. In addition, the registers 561~568 generates error detection information (for example, CRC information) while sequentially shifting the initial values until the first information or the second information contained in the reception information has been received.
After the first information or the second information has been received, the error decision block 580 compares the generated error detection information with the attached error detection information contained in the reception information, thus to determine whether an error exists in the received bits. That is, the error decision block 580 decides that no error exists in the received bits, if the generated error detection information is identical to the attached error detection information. Otherwise, if the generated error detection information is not identical to the attached error detection information, the error decision block 580 decides that an error exists in the received bits.
As described above, in the error detection apparatus of FIG. 7, the initial value controller 550 operates according to a length of the packet data. When first 13 bits of the received bits transmitted from the transmitter are completely received, the switches SW1~SW3 are switched to their lower terminals, so the switches SW1 and SW2 are provided with the preset input bit "0." Thereafter, 8 error detection bits (or redundant bits) are generated by shifting register values as many times as the number, 8, of the error detection bits. The error detection block 580 compares error detection bits (attached by the transmitter) included in the received bits with newly generated error detection bits. The error detection block 580 decides that no error exists in the received bits, if the error detection bits

included in the received bits are identical to the newly generated error detection bits. However, if the error detection bits included in the received bits are not identical to the newly generated error detection bits, the error detection block 580 decides that an error exists in the received bits. Although the initial value controller 550 and the error detection block 580 are separately constructed in this embodiment, the elements may be realized with a single controller.
Table 2 illustrates simulation results obtained by transmitting each of control information frames with a slot length of 1(2), 2(4), 4(255) and 4(0) 10,000 times in a noise-free state. Here, numerals in the parenthesis represent initial values of the CRC generator in decimal. In the simulation, the register initial value is set to Nl=2, for a control information frame with a 1-slot length. The register initial value is set to N2=4, for a control information frame with a 2-slot length. The register initial value is set to N3=255, for a control information frame with a 4-slot length corresponding to packet data with a 4-slot length. The register initial value is set to N4=0, for a control information frame with a 4-slot length corresponding to packet data with an 8-slot length. The result values obtained through the computer simulation include a successful detection probability Pd, a false probability Pfa, a mis-probability Pm, and an error probability Pe, the sum of the false probability Pfa and the mis-probability Pm. It is noted in Table 2 that the error probability Pe in detecting a control information frame comprised of 2(4) slots and 4(255) slots is abnormally high as shown in Table 1.
Table 2

(Table Removed)

While the invention has been shown and described with reference to a certain preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
[EFFECTS OF THE INVENTION]
As described above, the mobile communication system for transmitting packet data sets different CRC generator register initial values not only in control information frames with the same length but also in control information frames with different lengths in transmitting and receiving signals on the packet data control channel, making it possible to solve a problem that an error is generated during reception of a control information frame by BSD.

WE CLAIM:
1. An apparatus for generating error detection bits in a communication system that
transmits data having a 1-slot length, a 2-slot length, or a 4-slot length through a data
channel, the apparatus comprising:
an error detection bit attaching device adapted to generate error detection bits for control information using an initial value corresponding to a length of the control information from among first, second and third initial values, attach the error detection bits to the control information, and output the control information with the attached error detection bits, the first initial value corresponding to a 1-slot length, the second initial value corresponding to a 2-slot length and being equal to the first initial value, and the third initial value corresponding to a 4-slot length and being different from the second initial value; and
a transmitting device adapted to transmit over a control channel control data that includes the control information and the error detection bits.
wherein the error detection bit attaching device comprises:
a plurality of shift registers, the number of which corresponds to a length of the error detection bits, connected in series to each other;
a plurality of adders adapted to add feedback bits to bits of the output values of the shift registers input through an input path, and output , the bits with the added feedback bits through an output path, the address positioned among the shift registers according to a generator polynomial
an operator adapted to generate the feedback bits by sequentially adding bits of a final shift register in the series of the plurality of shift registers to the bits of the control information during the input of the control information, provide the generated feedback bits to the adders and the initial register in the sequence of the shift registers , and output the error detection bits by sequentially adding a first preset bit to the bits of the final shift registers when the input of the control information is completed; and
an initial value controller adapted to store the first to third initial values and provide bits of one initial value selected according to the length of the control information to the shift registers .
2. The apparatus as claimed in claim 1, wherein the control information has the same length as that of the data.
3. The apparatus as claimed in claim 1 wherein the operator comprises:
a first switch adapted to selectively output, one of the bits of the control information and the first preset bit;
an output adder adapted to add the bits of the final shift register to an output of the first switch;

a second switch adapted to selectively provide one of a second preset bit and an output of the output adder as the feedback bits to the plurality of adders and the initial register in the sequence of the shift registers; and
a third switch adapted to selectively output one of the control information and the output of the output adder as the error detection bits
4. The apparatus as claimed in claim 3, wherein the first switch adapts to output the bits of the control information during the input of the control information, and output, the first preset bit when the input of the control information is completed.
5. The apparatus as claimed in claim 4 wherein the second switch adapts to provide, the output of the output adder to the plurality of adders and the initial register during the input of the control information, and provide, the second preset bit to the adders and the initial register when the input of the control information is completed.

6. The apparatus as claimed in claim 1, wherein the first preset bit has a value of "0".
7. The apparatus as claimed in claim 3, wherein each of the first and second preset bits has a value of "0".
8. The apparatus as claimed in claim 4, wherein the first preset bit has a value of "0".
9. The apparatus as claimed in claim 5, wherein the second preset bit has a value of
"0".
10. The apparatus as claimed in claim 5, wherein the third switch adapts to output the
bits of the control information during the input of the control information, and output
the error detection bits when the input of the control information is completed.
11. The apparatus for checking error detection bits for control information in a communication system which transmits a data having a 1-slot length, a 2-slot length, or a 4-slot length through a data channel, the apparatus comprising:
a receiving device adapted to receive control data including control information representing information related to the data and error detection bits attached to the control information through a control channel; and
an error detection bit checking device adapted to check the error detection bits by receiving the control data as an input and using an initial value corresponding to length of the control information from among first, second and third initial values, the first initial value corresponding to an 1-slot length, the second initial value corresponding to a 2-slot length and being equal to the first initial value, and the third initial value corresponding to a 4- slot length and being different from the second initial value.
wherein the error detection bit checking device comprises:
a plurality of shift registers, the number of which corresponds to a length of the error detection bits, connected in series to each other;
a plurality of adders adapted to add feedback bits to bits of the output values of the shift registers inputted through an input path, and output the bits with the added

feedback bits through an output path, the adders being positioned among the shift registers according to generator polynomial;
an operator adapted to generate the feedback bits by sequentially adding bits of a final shift register in the series of the plurality of shift registers to the bits of the control information during the input of the control information,
provide the generated feedback bits to the adders and the initial register in the sequence of the shift registers, and detect the error detection bits by sequentially adding a first preset bit to the bits of the final shift register when the input of the control information is completed;
an initial value controller adapted to store the first to third initial values and provide bits of one initial value selected according to length of the control information to the shift registers; and
an error determining module for determining if the control information is erroneous by comparing the received error detection bits with the detected error detection bits.
12. The apparatus as claimed in claim 11 wherein the control information has the
same length as that of the data.

Documents:

3393-DELNP-2004-Abstract-(05-08-2008).pdf

3393-DELNP-2004-Abstract-(08-08-2008).pdf

3393-DELNP-2004-Abstract-(27-08-2008).pdf

3393-delnp-2004-abstract.pdf

3393-DELNP-2004-Assignment-(29-07-2008).pdf

3393-DELNP-2004-Claims-(05-08-2008).pdf

3393-DELNP-2004-Claims-(08-08-2008).pdf

3393-DELNP-2004-Claims-(18-03-2008).pdf

3393-DELNP-2004-Claims-(27-08-2008).pdf

3393-DELNP-2004-Claims-(28-08-2008).pdf

3393-delnp-2004-claims.pdf

3393-DELNP-2004-Correspondence-Others-(05-08-2008).pdf

3393-DELNP-2004-Correspondence-Others-(07-08-2008).pdf

3393-DELNP-2004-Correspondence-Others-(08-08-2008).pdf

3393-DELNP-2004-Correspondence-Others-(18-03-2008).pdf

3393-DELNP-2004-Correspondence-Others-(26-08-2008).pdf

3393-DELNP-2004-Correspondence-Others-(27-08-2008).pdf

3393-DELNP-2004-Correspondence-Others-(28-08-2008).pdf

3393-DELNP-2004-Correspondence-Others-(29-07-2008).pdf

3393-delnp-2004-correspondence-others.pdf

3393-DELNP-2004-Description (Complete)-(08-08-2008).pdf

3393-DELNP-2004-Description (Complete)-(27-08-2008).pdf

3393-DELNP-2004-Description (Complete)-(28-08-2008).pdf

3393-delnp-2004-description (complete)-05-08-2008.pdf

3393-delnp-2004-description (complete)-18-03-2008.pdf

3393-delnp-2004-description (complete).pdf

3393-delnp-2004-drawings.pdf

3393-DELNP-2004-Form-1-(27-08-2008).pdf

3393-delnp-2004-form-1.pdf

3393-delnp-2004-form-18.pdf

3393-DELNP-2004-Form-2-(18-03-2008).pdf

3393-DELNP-2004-Form-2-(27-08-2008).pdf

3393-delnp-2004-form-2.pdf

3393-DELNP-2004-Form-3-(29-07-2008).pdf

3393-delnp-2004-form-3.pdf

3393-delnp-2004-form-5.pdf

3393-DELNP-2004-Other-Documents-(08-08-2008).pdf

3393-DELNP-2004-PA-(18-03-2008).pdf

3393-DELNP-2004-PCT-304-(29-07-2008).pdf

3393-DELNP-2004-Petition-137-(26-08-2008).pdf

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Patent Number

224133

Indian Patent Application Number

3393/DELNP/2004

PG Journal Number

42/2008

Publication Date

17-Oct-2008

Grant Date

30-Sep-2008

Date of Filing

01-Nov-2004

Name of Patentee

SAMSUNG ELECTRONICS CO., LTD

Applicant Address

416, MAETAN-DONG, PALDAL-GU, SUWON-SHI, KYUNGKI-DO, REPUBLIC OF KOREA.

Inventors:

#	Inventor's Name	Inventor's Address
1	DONG-HEE KIM	565, SHINDAEBANG-DONG TONGAK-GU, SEOUL, REPUBLIC OF KOREA
2	HO-KYU CHOI	#1201-303, KUMI-DONG, PUNDANG-GU, SUNGNAM-SHI,KYONGGI-DO, REPUBLIC OF KOREA
3	YOUN-SUN KIM	63, TAECHI 3-DONG, KANGNAM-GU, SEOUL, REPUBLIC OF KOREA
4	HWAN-JOON KWON	MIDO MANSION, #1-203, TUNCHON 2-DONG, KANGDONG-GU, SEOUL, REPUBLIC OF KOREA

PCT International Classification Number

H04L 1/00

PCT International Application Number

PCT/KR02/01999

PCT International Filing date

2002-10-25

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	66904/2001	2001-10-29	Republic of Korea