Title of Invention

A METHOD OF DEPOSITING AN AMORPHOUS-SIC: H BARRIER LAYER ON A LOW K DIELECTRIC MATERIAL LAYER

Abstract A method of depositing an amorphous-SiC:H barrier layer on a low k dielectric material layer coated on a Si substrate, the method comprising exposing the low k dielectric material layer to hot wire chemical vapour deposition (HWCVD) using a mixture of silane (SiH4) and acetylene (C2H2) gases at a temperature of 200 to 300°C and pressure of 100 to 200 mTorr .
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THE PATENTS ACT, 1970 (39 of 1970)
As amended by the Patents (Amendment) Act, 2005
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As amended by the Patents (Amendment) Rules, 2005
COMPLETE SPECIFICATION (See section 10 and rule 13)
TITLE OF THE INVENTION
A method of depositing an amorphous-SiC :H barrier layer on a low k dielectric material layer

APPLICANTS
Name
Nationality
Address
INVENTORS
Names
Nationality
Address

Indian Institute of Technology, Bombay
an autonomous research and educational
institution established in India by a special
Act of the Parliament of the Republic of India
under the Institutes of Technology Act 1961
Powai, Mumbai 400076, Maharashtra, India
Dusane Onkar Rajiv, Kumbhar Anil Alka and Singh Kumar Sunil
all Indian Nationals
all of Indian Institute of Technology, Bombay
Powai, Mumbai 400076, Maharashtra, India

PREAMBLE TO THE DESCRIPTION
The following specification particularly describes the nature of this invention and the manner in which it is to be performed :

FIELD OF INVENTION
This invention relates to a method of depositing an amorphous-SiC:H barrier layer on a
low k dielectric material layer.
This invention also relates to a composite layer comprising a low k dielectric material layer and an amorphous-SiC:H barrier layer deposited on the dielectric material layer by the above method.
BACKGROUND OF INVENTION
During fabrication of integrated circuits, a Cu layer forming the contacts is deposited on a low dielectric material layer coated on a semiconductor material substrate. In order to reduce the RC time constant associated with the integrated circuits and to improve the frequency or speed of operation of the integrated circuits, it is essential that the dielectric constant (k) of the dielectric layer must be low. SiO2 is traditionally used as a dielectric layer. Due to the dielectric constant of the Si02 layer being high (about 4), the speed of operation of the integrated circuits is reduced. Therefore, attempts are being made to develop dielectric materials of low k value for use in the manufacture of integrated circuits. Hydrogen silsesquioxane (HSQ) [chemical formula (Hsi03/2)2n, where n = 3-8] with a dielectric constant k~2.9+0.05 is a recently developed low k dielectric material for use in the manufacture of integrated circuits. Diffusion of Cu is a serious problem associated with Si, Si02 and Si based low-k materials in that this gives rise to increased leakage current and interferes with the performance of the integrated circuits.
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US Patent 6,593,653 describes a silicon carbon nitride (SiCN) barrier layer to prevent Cu diffusion into the dielectric layer. This barrier layer is deposited by PECVD (Plasma Enhanced Chemical Vapour Deposition) or HDPCVD (High Density Plasma Chemical Vapour Deposition) using SiH4, CH4, and NH3. The SiCN layer has a high dielectric constant between 5.3 and 6.3 thereby reducing the speed of operation of the integrated circuits. US Patent 5,818,071 describes a silicon carbide layer as a barrier layer to prevent diffusion of metal atoms between adjacent conductors separated by a dielectric material. This barrier layer is deposited by techniques like PECVD and also has a high dielectric constant (~ 3.5) thereby reducing the speed of operation of the integrated circuits. US Patent 6,287,990 describes a method and apparatus for depositing a low dielectric constant film by the reaction of an organosilane or organosiloxane compound and an oxidizing gas at a low RF power level of 10-250 W. US Patent 6,939,797 describes an advanced back-end-of-line (BEOL) metallization structure that includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by PECVD. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon containing dielectric material having a dielectric constant of less than about 4 and a continuous hard mask layer overlying the ILD that is preferably formed of silicon nitride or carbide. US Patent 6,887,783 describes an advanced back-end-of-line (BEOL) metallization structure which includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by HDPCVD, and the second cap layer is formed of a dielectric material preferably deposited by PECVD. It is reported in semiconductor Fabtech-11 edition that a-SiCH (hydrogenated amorphous silicon carbon) barrier layer deposited by
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PECVD and having k25 nm.
All the above prior art processes employ the plasma deposition technique which require RF generators and impedance matching circuits. Therefore, the processes are expensive and difficult to carry out. Besides, the plasma deposition gives rise to increased surface roughness of the dielectric layer due to damages caused by ion and electron bombardment and induced charge. Prior art patents like US 6287990 also use hazardous chemicals and patents like US 6939797 and 6887783 employ bilayers thereby increasing material cost, processing time and overall cost.
OBJECTS OF INVENTION
An object of the invention is to provide a method of depositing an amorphous-SiC:H barrier layer on a low k dielectric material layer, which method is simple and convenient to carry out and cost effective.
Another object of the invention is to provide a method of depositing an amorphous-SiC:H barrier layer on a low k dielectric material layer, which method gives rise to a composite layer comprising the low k dielectric material layer and a barrier layer having reduced leakage current.
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Another object of the invention is to provide a method of depositing an amorphous-SiC:H barrier layer on a low k dielectric material layer, which method gives rise to a composite layer comprising the low k dielectric material layer and a barrier layer having low dielectric constant.
Another object of the invention is to provide a method of depositing an amorphous-SiC:H barrier layer on a low k dielectric material layer, which method produces a barrier layer of reduced thickness thereby reducing cost.
DETAILED DESCRIPTION OF INVENTION
According to the invention there is provided a method of depositing an amorphous-SiC:H barrier layer on a low k dielectric material layer coated on a Si substrate, the method comprising exposing the low k dielectric material layer to hot wire chemical vapour deposition (HWCVD) using a mixture of silane (S1H4) and acetylene (C2H2) gases at a temperature of 200 to 300°C and pressure of 100 to200mTorr.
According to an embodiment, the method comprises depositing the amorphous-SiC: H on the low k dielectric material layer coated on the Si substrate by HWCVD by heating a tungsten wire at 1700 to 1900°C.
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Preferably the method comprises depositing the amorphous-SiC: H barrier layer on a low k dielectric material layer comprising hydrogen silsesquioxane (HSQ) coated on the Si substrate.
According to the invention there is also provided a composite layer comprising a low dielectric material layer coated on a Si substrate and an amorphous-SiC: H layer deposited on the dielectric material layer by the method described above.
Preferably the low k dielectric material layer comprises hydrogen silsesquioxane (HSQ) coated on the Si substrate. Preferably, the amorphous-SiC:H layer is of 10 nm thickness. Preferably, the substrate is crystalline Si.
According to the invention the barrier layer on the dielectric material layer is deposited by HWCVD which eliminates the use of RF generators and impedance matching circuits thereby rendering the process simple and convenient to carry out and cost effective. The process of the invention does not damage the dielectric layer, as it does not generate ions and electrons or induced charge. It has been found that a barrier layer of l0nm is adequate and sufficient to prevent Cu diffusion into the dielectric material layer thereby reducing cost of the barrier layer. The composite layer of the dielectric material layer and barrier layer has reduced leakage current and low dielectric constant. Therefore, integrated circuits fabricated using the composite layer will have reduced RC time constant and improved frequency or speed of operation.
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The following examples are illustrative of the invention but not limitative of the scope thereof.
Example 1
Flowable oxide (Fox-14) from Dow Corning which is also called hydrogen silsesquioxane (HSQ) was spin coated on c-Si substrate to a thickness of 200 nm. The coating was baked sequentially on a hot plate at 150°C, 250°C and 350°C for 1 minute followed by furnace cured at 400°C for one hour in nitrogen atmosphere. HSQ coating had a low dielectric constant of 2.85 as measured by a C-V meter.
Amorphous-SiC:H barrier layers were deposited on HSQ coated substrates by the following procedure:
HSQ coated c-Si substrate was mounted on the substrate holder of a Hot Wire Chemical Vapour Deposition (HWCVD) chamber and the chamber was evacuated to 10"6 Ton-base pressure. The substrate temperature was maintained at 250°C and the wire temperature at 1800°C and silane (SiH4) and acetylene (C2H2) gases were passed into the chamber at a flow rate of 2 and 3 seem (standard cubic centimeter per minute) respectively. The chamber pressure was maintained at 100 mTorr during deposition. Deposition was carried out for 2, 5 and 10 mins in order to get thickness of 17, 42 and 84nm for the amorphous-SiC:H barrier layers on different dielectric layers respectively.
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Following this, the substrates were allowed to cool down to room temperature and removed from the chamber.
The substrates deposited with the barrier layers were loaded into a physical vapour deposition (PVD) chamber and the chamber was evacuated to 10" Torr. Aluminum was evaporated on the uncoated side of the substrates through a physical mask to serve as a bottom contact. Cu was evaporated on the barrier layer on the coated side of the substrates through a physical mask to form dots (1mm diameter) of Cu and serve as a top contact. The substrates were sintered at 420°C in nitrogen ambient to have a good ohmic contact. The dielectric constant and leakage current of the substrates were measured for the different thickness of the amorphous-SiC:H layers. The dielectric constant of the HSQ/a-SiC:H layers increased from 3 to 3.3 with increase in amorphous-SiC:H thickness as shown in Fig 1 of the accompanying drawings. The lower the thickness of the dielectric layer, the lower the dielectric constant. The leakage current density decreased by ~ 2 orders of magnitude with the application of the amorphous-SiC:H barrier layer irrespective of its thickness as shown in Fig 2 of the accompanying drawings.
Example 2
200 nm thick HSQ layers were coated on c-Si substrates as described in Example 1. 20 nm barrier layers of amorphous-SiC:H were deposited on the HSQ layers of the above substrates by HWCVD followed by l00nm thick Cu by physical vapour deposition (PVD). 200nm HSQ layer was deposited on the Cu of the substrates by spin coating.
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The substrates were sintered at 400°C for l h in N2 ambient. Secondary Ion Mass Spectroscopy (SIMS) analysis of the substrates was carried out to determine the extent of Cu+ diffusion into the HSQ on one side and into the composite amorphous-SiC:H/HSQ layer on the other. It was found that copper diffused into HSQ layers to a large extent while copper diffusion was restricted in the composite amorphous-SiC:H/HSQ layers as seen in Fig 3 of the accompanying drawings. The copper diffused to about 8 nm of the amorphous-SiC:H layer and did not diffuse into the dielectric at all. It was therefore, concluded that a barrier layer of l0nm was adequate and sufficient to restrict Cu penetration into the HSQ layer. At this low thickness the dielectric constant value is also low as seen Fig 1. This thickness requirement is significantly lower than that reported earlier namely 25nm in the Semiconductor Fabtech - 11th edition.
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We Claim:
1. A method of depositing an amorphous-SiC:H barrier layer on a low k dielectric material layer coated on a Si substrate, the method comprising exposing the low k dielectric material layer to hot wire chemical vapour deposition (HWCVD) using a mixture of silane (SiH4) and acetylene (C2H2) gases at a temperature of 200 to 300°C and pressure of 100 to 200 mTorr .
2. A method as claimed in claim 1, which comprises depositing the amorphous-SiC: H layer on a low k dielectric material layer comprising hydrogen silsesquioxane (HSQ) coated on the Si substrate.
3. A method as claimed in claim 2, wherein the amorphous-SiC: H layer is of 10 nm thickness.
4. A method as claimed in claim 2, wherein the substrate is crystalline Si.
5. A method as claimed in claim 1, which comprises depositing the amorphous-
SiC: H barrier layer on the low k dielectric material layer coated on the Si substrate by
HWCVD by heating a tungsten wire at 1700 to 1900°C.
6. A method as claimed in claim 5, which comprises depositing the amorphous-SiC:
H barrier layer on the low k dielectric material layer comprising hydrogen silsesquioxane
(HSQ) coated on the Si substrate.
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7. A method as claimed in claim 6, wherein the amorphous-SiC:H layer is of 10 nm thickness.
8. A method as claimed in claim 6, wherein the substrate is crystalline Si.

9. A composite layer comprising a low k dielectric material layer coated on a Si substrate and an amorphous-SiC:H layer deposited on the dielectric material layer by the method as claimed in claim 1.
10. A composite layer as claimed in claim 9, wherein the low k dielectric material layer comprises hydrogen silsesquioxane (HSQ) coated on the Si substrate.
11. A composite layer as claimed in claim 9, wherein the amorphous- SiC:H layer is l0nm thickness.
12. A composite layer as claimed in claim 9, wherein the substrate is crystalline Si.
13. A composite layer comprising a low k dielectric material layer coated on a Si substrate and an amorphous-SiC:H layer deposited on the dielectric material layer by the method as claimed in claim 5.
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14. A composite layer as claimed in claim 13, wherein the low k dielectric material layer comprises hydrogen silsesquioxane (HSQ) coated on the Si substrate.
15. A composite layer as claimed in claim 13, wherein the amorphous-SiC:H layer is of 10 run thickness.
16. A composite layer as claimed in claim 13, wherein the substrate is crystalline Si.
Dated this 2nd day of January 2006.
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Documents:

4-MUM-2006 -CORRESPONDENCE(14-07-2008).pdf

4-mum-2006-abstract(2-1-2006).doc

4-mum-2006-abstract(2-1-2006).pdf

4-mum-2006-claims(granted)-(2-1-2006).doc

4-mum-2006-claims(granted)-(2-1-2006).pdf

4-mum-2006-claims.doc

4-mum-2006-claims.pdf

4-mum-2006-correspondence(11-4-2008).pdf

4-MUM-2006-CORRESPONDENCE(IPO)(14-07-2008).pdf

4-mum-2006-correspondence(ipo)-(28-8-2008).pdf

4-mum-2006-correspondence-received.pdf

4-mum-2006-description (complete).pdf

4-mum-2006-drawing(2-1-2006).pdf

4-mum-2006-form 1(2-1-2006).pdf

4-mum-2006-form 1(22-2-2006).pdf

4-mum-2006-form 18(15-6-2006).pdf

4-mum-2006-form 2(granted)-(2-1-2006).doc

4-mum-2006-form 2(granted)-(2-1-2006).pdf

4-mum-2006-form 26(7-1-2006).pdf

4-mum-2006-form 3(2-1-2006).pdf

4-mum-2006-form 8(28-5-2007).pdf

4-mum-2006-form-1.pdf

4-mum-2006-form-2.doc

4-mum-2006-form-2.pdf

4-mum-2006-form-26.pdf

4-mum-2006-form-3.pdf

abstract1.jpg


Patent Number 223221
Indian Patent Application Number 4/MUM/2006
PG Journal Number 06/2009
Publication Date 06-Feb-2009
Grant Date 08-Sep-2008
Date of Filing 02-Jan-2006
Name of Patentee INDIAN INSTITUTE OF TECHNOLOGY BOMBAY
Applicant Address POWAI, MUMBAI-
Inventors:
# Inventor's Name Inventor's Address
1 DUSANE ONKAR RAJIV INDIAN INSTITUTE OF TECHNOLOGY BOMBAY POWAI, MUMBAI-400 076.
2 KUMBHAR ANIL ALKA INDIAN INSTITUTE OF TECHNOLOGY BOMBAY POWAI, MUMBAI 400 076
3 SINGH KUMAR SUNIL INDIAN INSTITUTE OF TECHNOLOGY BOMBAY POWAI, MUMBAI 400 076
PCT International Classification Number C23C16/30
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA