Title of Invention  "AN ANALOG TO DIGITAL CONVERTER IF COMPUTING ALL THE BITS IN PARALLEL AND SIMULTANEOUSLY WITHOUT" 

Abstract  An analog to digital converter computing all the bits in parallel and simultaneously without using any decoding means having an analog input and a digital output, comprising a sampling and holding block , a counter block, a multiplexer receiving the sample values from said sample and holding block, a delay mechanism connected to the output of said multiplexer to delay the signal passed by said multiplexer before being doubled; a doubler connected to the said delay circuit and multiplexer, doubling the said delayed signal to feed the said doubled output signal to the multiplexer , wherein the said multiplexer passes the said signal to the functional block depending upon the counter value; a functional block comprising a combination of nonlinear gain blocks, amplifiers and means for adding various signals generating the output bit. 
Full Text  The subject invention relates to an analog to digital converter, computing all the bits in parallel and simultaneously without using any decoding means The object of the subject application is to develop a system to be applied on a VLSI chip (integrated circuit) for many different implementations offering different degrees of tradeoff between speed and hardware requirement. Background of the invention: Signals in the real world are realvalued, or analog in nature, as the output of a pressure or temperature sensor, the amplitude of a speech signal, and the like . For example, the output voltage of a microphone may be 2 millivolts (mV) in response to a certain acoustic signal. Suppose that the output of the microphone ranges from a minimum of 0 mV to a maximum of 8 mV. The output of the microphone under consideration may typically be processed by some form of signal processing system. Most processing equipment today are digital in nature, and they work with signals which are binary valued. In a digital or binary representation, a signal is represented by a word, which is composed of a finite number of bits. The number of bits is termed as the word length, henceforth denoted by N. Since each bit in the word is either a 0 or a 1, the number of possible combinations is finite. The maximum number of possible binary numbers with N bits is equal to 2N. Since an infinite number of real values exist in a given analog range, the binary or digital representation is necessarily an approximate one. If, the output of the microphone may be represented by 3 bits. Let the three bits be denoted by V,, V2 and V3. The number represented by the 3 bits (in millivolts) is given by V1 + 2V2 + 4V3. In general, with N bits, the digital representation is equal to Σ N i=1 2i1. V, where the significance of VN is the highest (it is weighted by 2N1); this bit is termed as the Most Significant Bit (MSB). Conversely, V1 is termed as the Least Significant Bit (LSB). The problem of analogtodigital conversion is that of finding an Nbit binary word which best approximates a given analog value x, where N is an integer. An Analog to Digital Converter (ADC) for N bits has N output bits labeled V1 to VN, where each V; (i=1,2,... N) is either 0 or 1. Given an analog input whose value is denoted by a number x, the ADC is required to determine the values of V., to VN such that the error IΣN i=1 2 h1. V ils minimized. If N is chosen to be 3, then the following table gives the outputs of a 3bit ADC for different values of x. the range of values of x is assumed to be 0 to 8. (Table Removed) The existing methods of ADC as known conventionally includes flash converters, dualslope, ramp, sigmadelta, successive approximation, and the like. Presently, flash converters are the only known way of obtaining all the output bits in parallel. A Nbit flash converter requires of the order of 2N comparators. Let the input signal range from 0 to R. The range from 0 to R is divided into 2N levels. These comparators each output a 1 or 0 depending on whether the analog input x exceeds or is below the corresponding level. Decoding logic is made up of gates. Practical considerations limit the number of input (fanin) and fanout of each gate. As a result, the delay due to decoding logic increases as O (N Iog2 N) or faster. These conditions limit the word length of a flash converter. Since all the bits of a flash converter are obtained simultaneously, the time required to generate the output bits once the analog input has been presented is small. In the case of a flash converter, the hardware grows exponentially with the number of bits; the number of comparators required for a Nbit converter is 2N and additional decoding logic is required. Improved systems based on the flash converter use fewer comparators, where the number of comparators required can be written as 2KN, where K is a fraction between 0 and 1. In other words, the rate at which hardware requirements increases still is an exponential function of N. Other conventional approaches such as dualslope and successive approximation methods require considerably less hardware. However, in these methods, the bits cannot be computed in parallel. As a result, the time taken to generate the binary approximation, which is termed as the conversion time, is much higher than for a flash Analog to Digital Converter. The conversion time is closely related to the sampling rate that can be handled by the Analog to Digital Converter. This is the rate at which input samples are accepted. Obviously, the next sample cannot be taken up by the ADC until the previous one has been converted. In an another conventional frequency domain approach called sigmadelta conversion, the input signal is sampled at a high rate to achieve analog to digital conversion. The scheme requires the extensive use of filters and additional hardware. An additional drawback is the need for the circuitry to work at a high speed; typically much higher than the sampling rate. This also creates hurdles with regard to hardware or circuit realization of such methods. In order to overcome the drawbacks associated with the existing methods of analog to digital converter, the subject application has been devised, where all the bits can be computed in parallel or sequentially including the most significant bits, which can be computed along with other bits. The subject system relates to the computerization of all the output bits in parallel, where the input x lies between 0 and R. The most significant bit (MSB), i.e., VMSB is given by: VMSB = 1 ifx≥R/2 VMSB = 1 ifx VMSB1 = 1 if R/4 According to the present invention there is provided an analog to digital converter computing all the bits in parallel and simultaneously without using any decoding means having an analog input and a digital output, comprising: a sample and hold block for sampling the analog input signal and holding the sample values such as herein described; a counter block initialized having the initial counter value at 1 counting from 1  N; a multiplexer receiving the sample values from sample and holding means, wherein when the counter value is equal to 1, the multiplexer passes the input on line 1 to its output and the said multiplexer passes the input on Line 2 to its output, when the counter value is any number other than 1 and the output from multiplexer is fed to a functional block as well as to a delay block (circuit); a delay element connected to the output of said multiplexer to delay the signal passed by said multiplexer before being doubled; a doubler (103) connected to the said delay circuit and multiplexer, doubling the said delayed signal to feed the said doubled output signal to the multiplexer , wherein the said multiplexer passes one of its inputs to the functional block depending upon the counter value;  a functional block comprising a combination of nonlinear gain blocks. The amplifier used in the said analog to digital converter is linear or nonlinear circuit for weighted summation of inputs and the siad weighted summation of inputs are programmable gain amplifies and/or resistors and means for adding various signals. The means for adding various signals are operational amplifier based circuits or current mode circuits. The subject application may better be understood with reference to the accompanying drawings and various embodiments involved therein. However, the same are for illustrative purposes only and should note be constructed to restrict the scope of the invention. BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS Figure 1 depicts the computation of VMSB and VMSB..,, using the sine function. Figure 2 depicts the computation of VMSB and VMSB.i using pulse shaped functions. Figure 3 depicts the Schematic of the A/D converter based on the computation of VMSB and VMSB1 using the sine function. Figure 4 depicts the schematic of A/D converter based on the computation of VMSB and VMSB.! using pulse shaped functions. Figure 5 depicts the schematic using a single P() block. DETAILED DESCRIPTION OF THE INVENTION The computation of VMSB and VMSB.., in general is depicted in figure 1, depicting the formula as VMSBI = Sign [sin(πx/(R/2l+1)]. That is all the bits may be computed in parallel, where the MSB does not have to be computed before other bits are computed. Computing each bit requires a similar operation, which is the computation of the sin ( ) function. The input to the block computing the (MSBi)th bit is x. The bits may also be computed sequentially. Various alternatives can be obtained by any function which has the same period as it is not necessary to use the sin() function only. The bits may be obtained by using a function of the form VMSB.j = P[x/R/2')] where P(z) is a pulse shaped function which is periodic equal to 1, whose value is zero for the first half period and one for he second the second half. The functions for MSB and MSB1 are depicted in figure 2. The basic scheme allows for a very simple design and implementation in hardware. No decoding logic is required as in a flash converter. The various alternative embodiments may be obtained using the same function block, whether the sin() or P() block is used. The same function block may be utilized for all bits by introducing a delay and a doubler in a loop as shown in Fig. 5, thus requiring very little hardware. The input signal x is sampled and the sample values held by a sample andhold (S/H) block (101). Initially, the counter (106) is initialized to 1. When the counter value is equal to 1, the Multiplexer (MUX) (102) passes the input on line 1 to the P() block. Therefore, the sample is first passed to the P() block (105) as shown in the figure 5 and the MSB bit is generated. The sample is passed through a delay element (104) and a doubler (103) and is another input to a Multiplexer (MUX). This input is labeled as line 2. The counter is incremented by 1 after each bit is generated. Whenever the counter value is any number other than 1, the MUX passes the input on line 2 to the P() block. When the counter reading is 2, the P() block therefore gets the original sample, delayed by one unit delay, and doubled in value. The input to the P() block is thus a value 2x, delayed by one delay unit. The output of the P() block will now be P[2x/R], which is the same as P[x(R/2)], which in turn is nothing but the (MSBl)th bit. Similarly, after each successive bit, the P() block receives double the previous value as input and generates the next bit. The counter resets to 1 after N counts, i.e., after all bits have been generated. The main advantages of the proposed scheme is that all the bits are computed in parallel. The hardware required is much less than that of a flash converter. No decoding logic is required, as is needed in other known methods used conventionally. Moreover, as the hardware used is very simple, the working of the system is fast. Furthermore, the hardware in the proposed invention required grows linearly with the number of bits, i.e. a Nbit converter requires N blocks, each of a fixed size. The schematic of the subject application is highly amenable to realization on a VLSI chip (integrated circuit). The scheme allows for many different Moreover, as the hardware used is very simple, the working of the system is fast. Furthermore, the hardware in the proposed invention required grows linearly with the number of bits, i.e. a Nbit converter requires N blocks, each of a fixed size. The schematic of the subject application is highly amenable to realization on a VLSI chip (integrated circuit).The scheme allows for many different implementations offering different degrees of tradeoff between speed and hardware requirement. The subject application is a statement of invention, where several other alternative implementations of the pipelined version are possible as known to the person skilled in the art. Hence, the same should not be construed to restrict the scope of the invention. Reference la made to the copending Application No* 1047/DEL/2000. WE CLAIM: 1 An analog to digital converter computing all the bits in parallel and simultaneously without using any decoding means having an analog input and a digital output, comprising: a sample and hold block (101) for sampling the analog input signal and holding the sample values such as herein described; a counter block (106) initialized having the initial counter value at 1 counting from 1  N; a multiplexer (102) receiving the sample values from sample and holding means (101), wherein when the counter value is equal to 1, the multiplexer passes the input on line 1 to its output and the said multiplexer passes the input on Line 2 to its output, when the counter value is any number other than 1 and the output from multiplexer is fed to a functional block (105) as well as to a delay block (104) (circuit); a delay element connected to the output of said multiplexer to delay the signal passed by said multiplexer before being doubled; a doubler (103) connected to the said delay circuit and multiplexer, doubling the said delayed signal to feed the said doubled output signal to the multiplexer , wherein the said multiplexer passes one of its inputs to the functional block depending upon the counter value; a functional block comprising a combination of nonlinear gain blocks. 2. An analog to digital converter computing all the bits in parallel and simultaneously without using any decoding means having an analog input and a digital output, substantially as herein before disclosed with reference to the accompanying drawings. 

1047del2000correspondenceothers.pdf
1047del2000correspondencepo.pdf
1047del2000description (complete).pdf
1047del2000petition138.pdf
Patent Number  221506  

Indian Patent Application Number  1047/DEL/2000  
PG Journal Number  31/2008  
Publication Date  01Aug2008  
Grant Date  24Jun2008  
Date of Filing  23Nov2000  
Name of Patentee  THE INDIAN INSTITUTE OF TECHNOLOGY, DELHI (IITD)  
Applicant Address  HAUZ KHAS, NEW DELHI,110016, INDIA  
Inventors:


PCT International Classification Number  H03M 1/12  
PCT International Application Number  N/A  
PCT International Filing date  
PCT Conventions:
