| Title of Invention | "A METHOD AND APPARATUS FOR OPERATING A CLOCK RECOCVERY CIRCUT TO RECOVER A CLOCK SIGNAL FROM AN INPUT SIGNAL HAVING A VARIABLE BIT RATE" |
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| Abstract | A method for recovering a clock signal from an input signal "having a variable bit rate, said method being characterized in that it comprises the steps of: estimating a minimum time interval between transitions in the input signal; generating a first plurality of pulses corresponding respectively to transitions in the input signal; adjusting the duration of each of the first plurality of pulses based on the estimated minimum time interval and inputting into a narrow-band filter the adjusted first plurality of pulses; determining a center frequency of the narrow-band filter based on the generated minimum time interval; and extracting in the narrow-band filter the clock signal from the adjusted first plurality of pulses. |
| Full Text | The present invention relates to a method and apparatus for Recovering a Clock signal fromand input signal having a varaable fix rate. CROSS-REFERENCE TO RELATED APPLICATION Thisapplication claims the benifit U.S provisional Application no.60/067397,filed December 5,1997, the contents of which are hereby incorporated in theirentirety by reference. BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to recovering timing clock of signals in communication networks, and more particularly, to methods and apparatuses for recovering timing clock of variable bit rate signals in communication networks. Background of the Art High reliability networks, which handle diverse types of traffic from diverse sources, monitor and manage in the time domain the quelity of digital transmission. Failure to detect and correct transmission impairments results in unacceptable link error rates and unexpected network failures. Hence, networks must extract from a stream of transmitted data a clock signal to perform the necessary measurements and correct fot inevitable transmission degradation. AT. extracted clock signal is necessary to perform time domain measurements, such as eye-pattern opening and timing jitter. The extracted clock signal is also essential for distinguishing the individual data bits in the transmitted data stream prior to further processing, such as digital demultiplexing, protocol conversion, packet switching, and measurement of bit error rate (BER). Clock recovery has traditionally been regarded as a rat;: specific process, and as a result, conventional point-to-point transmission systems typically use only one or two line rates. Emerging nerwork technologies, for example photonic switching and Wavelength Division Multiplexing (WDM), however, have enabled complex optical network topologies, where links transport diverse types of traffic, such as Intsmet Protocol (IP), Asynchronous Transfer Mode (ATM), Fiberchar-nel, Synchronous Optical Network (SONET), and Gigabit Ethernet. Hence, thesu emerging networks must use clock recovery circuits that are adaptive to the variable rate of the transmitted data.A phase locked loop is one type of tracking filter often used in a clock recovery cijrcuit for extracting a clock signal from an input datei signai. Figure 1 illustrates ths primary components of a prior art clock recovery circuit 100, which includes a phase locked loop. The phase locked loop includes a phase comparator 120, a low pass filter 130, a stable voltage controlled oscillator 150 (VCO), and feedback loop 16:5. As shown, a Transition detector 110, for example a dual edge triggered one-shot, receives a non-return to zero (NRZ) input signal 155, and generates a single pulse of duration ?gD for each transition in input signal 155. The phase locked loop. whose passband frequency/ is centered on the bit rate frequency /bir of input signai 155, extracts the dock signal from the stream of pulses generated by transition detector 110. Phase comparator 120 compares the phase of the signal at the output of the phase locked loop with the stream of pulses, and generates a phase difference signal. Low pass filter 130 filters and amplifies the phase difference signal to generate a correction signal for adjusting the phase of VCO 150. For a variable bit rate NRZ input sigaaJ, two rate dependent parameters must be properly adjured in clock recovery circuit 100 for recovering an associated clock signal 160. One iate dependent parameter is the width teo of the pulses generated by transition detector 110, While input signal 155 generally does not contain anergy at its bit rate frequency f^, the series of pulses generated by transition detector \ 10 does contain energy at the bit rate frequency /Wl. The amount of energy at the bit rate frequency /hil is maximum when the width of the generated puises t80 equals l/(2/fbit). Th« center frequency of VCO 150 is the second rate dependent parameter, which must be properly sat to recover clock signal 160 from input signal 155. An active or piaasive stabilization signal 170 initially sets the center frequency of VCO 150 to a value fs in tha absence of a signal from phase ccmparator 120, Feedback loop 165 causes the center frequency of VCO 150 to shift from the initial frequency /, to the bit rats frequency /„, of input signal 155. VCO 150 will lock to the bit rate frequency />„ when its center frequency is close to ihe bit rate frequency friv When the center frequency of VCO 150 exactly equals the bit rats frequency /Ml, VCO 150 will phase lock to transitions in input signal 155. In addition to a phass locked loop, clock recovery circuits may also include a frequency locked loop for tuning the center frequency ft of VCO 150 to the bit rate frequency fbit, Figure 2 illustrates the basic components of a clock recovery circuit 200, which includes a transition detector 210, phase comparator 220, frequency comparator 260, low pass filter 230, and VCO 250. Frequency comparator 220 compares the stream of pulses generated by tranamon detector 210 with the output of VCO 250, and generates a locking signal that reflects the difference between the center frequency of VCO 250 and the bit rate frequency fbit, An adder 270 combines the locking sign&J with the output of phase comparator 220. Feedback loop 265 causes the center frequency of VCO 250 to shift from its initial value of/, to the bit rate frequency fbit, causing the locking signal to transition to zero. At this point, phase comparator 120 continues to control the center frequency and phase of VCO 250. The stream of pulses generated by transition detector 210 also contains at multiples of the hit rate frequency fbit, energy, whose relative amplitude increases as ted decreases. A.S a result, regular patterns in block coded input signals may produce both harmonics ami sub-harmonics of ihe bit rate frequency fbit, Accordingly, existing clock recovery circuits track the harmonics or sub-harjnonics of the input data signal when the cisnter frequency of VCO 250 is inappropriately set to a. multiple or the bit rate frequency fbit, Consequently, false locking may occur when a clock Recovery circuit searches for the bit rate frequency fbit, by sweeping the center frequency of VCO 250 across the harmonics. In addition, recurrent patterns in common block coded input data signals also increase the susceptibility of a clock recovery circuit to sub-harmonic locking. Although various techniques are known for sweeping the center frequency of VCO 250 to detemune the bit fate frequency /«„ these techniqi.es are too slow and/or lack sufficient accuracy for variable bit rate applications. One example of variable bit raw applications is Wavelength Division Multiplexing (WDM), where an input data signal can have a wide range of bit rates. In addition, the existing techniques cause a clock recovery circuit to readily lock to harmonics and sub-harmonics of the bit rate frequency fB Thus, it is desirable to have methods and apparatuses that do not have (he above-maationsc, and other disadvantages of the prior art clock recovery circuits for recovering a clock signal from a. variable bit raw input data signal. DESCRIPTION OF THE INVENTION Methods and apparatuses consistent with the present invention recover a clock signal of a variable bit rate data signal by estimating the minimum lime interval between transitions in the data signal, and based on the estimated minimum tima interval, datermining a center frequency of a narrow band filter that extracts the clock signal from the data signal. For example, a clock recovery circuit consistent with chs present invention extracts the clock signal from the variable bib rate data signal by estimating a minimum time interval between transitions in the data signal. The clock recovery circuit generates a plurality of pulses that correspond to transitions in the data signal, and adjusts the duration of each of the pulses basec on the estimated minimum time interval, The clock recovery circuit inputs into a narrow band filter the adjusted pulses, d«tsrmbes a center frequency of the narrow band filter basad on the estimated minimum time interval, and extracts in the narrow-band filter the clock signal from the adjusted pulses. Methods and apparatuses consistent with the invention sistimate che bit rate of a data signal independently of a primary phase locked loop and frequency locked loop. Such methods and apparatuses directly estimate the minimum rime interval between transitions in the data signal, and thus, eliminate the problems of harmonic and sub-harmonic locking thai the prior art clock recovery circuits exhibit in variable bit rate applications. The description of the invention and the following descr.ption for carrying out the best mode of the invention should noc restrict the scope of the claimed invention. Both provide examples and explanations to enable others to practice the invention. The accompanying drawings, which form part of the description for carrying out the best mode of the invention, show several embodiments of the invention, and together with the description, explain the principles of the invention. Accordingly there is provided a method for recovering a clock signal from an input signal having a variable bit rate, said method being characterized in that it comprises the steps of: estimating a minimum time interval between transitions in the input signal; generating a first plurality of pulses corresponding respectively to transitions in the input signal; adjusting the duration of each of the first plurality of pulses based on the estimated minimum time interval and inputting into a narrow-band filter the adjusted first plurality of pulses; determining a center frequency of the narrow-band filter based on the generated minimum time interval; and extracting in the narrow-band filter the clock signal from the adjusted first plurality of pulses. Accordingly there is provided an apparatus for recovering a clock signal from an input signal having a variable bit rate, said apparatus being characterized in that it comprises: a rate detector (301) for estimating a minimum time interval between transitions in the input signal; a transition detector (320) for generating a first plurality of pulses corresponding respectively to transitions in the input signal; a narrow-band filter (330) connected to said transition detector, and a rate selector (310) connected to said rate detector, said rate selector connected to said transition detector for adjusting, based on the -estimated minimum time interval, the duration of each of the first plurality of pulses, and connected to said narrow-band filter for determining a center frequency of the narrow-band filter that receives the adjusted first plurality of pulses from said transition detector, said narrow-band filter outputting the recovered clock signal. BRIEF DESCRIPTtOiV OF THE DRAWINGS In the Figures: Figure 1 is a block diagram of a prior an clock recovery circuit, which includes a phase Locked loop; Figure 2 is a block diagram of a prior an clock recovery circuit, which includes a frequency locked loop and a phase locked loop; Figure 3 is a block diagram of a variable bit rats: clock recovery circuit, in accordance with an embodiment of the invention; Figure 4 is a block diagram of a variable bit rate clock memory circuit. which includes a calibration means, in accordance with an embodiment of the invention; Fig. 5 is a circuit diagram of a forward rate dsteaor, which performs discrete interval pulse-width auto-correlation, in accordance with an embodiment of the invention: Figures 6a, 6b, 6c, 6d, and 6e illustrate riming diagrams of an input signal as it propagates through a set of delay segments, in accordance with an embodiment of the invention; Figure 7 is a circuit diagram of a delay segment, in accordance wich an embodiment of the: invention; Figure 8 is a block diagram of a forward rate detector, which performs continuous pulse.v,idth auto-correlation, in accordance with an •imbodiment of the invention; Figures 9a, 9b, 9c, and 9d illustrate the timing diagrams of an input signal, output of a ;ime interval generator, and output of an edge transition comparator, in accordance with an embodiment of the invention: Figure 10 is a circuit diagram of a minimum tmeival correlator, in accordance with an embodiment of the invention; Figure 11 illustrates an emitter coupled logic (ECL) implementation of a unipolar minimum interval corrslator, in accordance with an embodiment of the invention; Figures 12a, 12b, I2c, and 12d illustrate an analog implementation of a feedback circuit and associated signals in a forward rite detector, in accordanc* with an embodiment of the invention; Figures 13a, 13b, 13c, 13d, and 13e illustrate a digital implementation of a feedback circuit and associated signals in a forward rats detector, in accordance with an embodiment of the invention; and Figures 14a and 14b are block diagrams of implementations of a rate selector, in siccordance with two embodiments of the invention. BEST MODE FOR CARRYING OUT THE INVENTION Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. VARIABLE BIT RATE CLOCK RECOVERY Figure 3 is a block diagram of a variable bit rate clock recovery circuit 300, in accordance with an embodiment of the invention. Clock recovery circuit 300 comprises forward rate detector 301, rate selector 310, transition detector 320, and * narrow band filter :330. Clock recovery circuit 300 includes a programmable clock extraction path and a rate selection path. The clock extractioa pith includes transition detector 320 and rtiurow band filler 330. The rate selection patJb. includes forward rate detector 301 and rate selector 310. Transition detector 320 and forward rate detector 301 receive a variable bit rate input dsita signal 155. From input signal 155, transition detsctor 320 generates a pulse in response to sach transition in input signal 155. Likewise, forward rate detector 301 estimates the minimum time interval between transitions in input signal 155, and generates a race estimate signal RE. Rate selector 310 thaa converts tha rate estimate signal RE into control signals RS, and RS,, which set tie width τED of the pulses generated by transition detector 320 and the canter frequency /, of narrow band filter 330, respectively. Rate selector 310 may set τED and /, to. for example, I/(2 fbit} /ftu, respectively. When rate selector 310 sets the appropriateτED and fbit narrow band filter 330 extracts clock signal 160 from the stream of pulses. Rate estimate signal RE may be represented as follows: (Formula Removed) whore /Bjl ii the bit rate frequency of input signal 155 and Kτed Li either a constant or a slowly varying function of fbit The pulse width -ΤED fromthr transition detector 320 may be represented as follows: (Formula Removed) where Ked us a monotonic ftinction of control signal RSt. The csnter frequency ƒτ of the narrow band filter 330 may be represented as follows: (Formula Removed) where Kts is a monotonic function of control signal RS1,. In one embodiment, rate selector 31C) may perform a one-to-one mapping of rate estimate signal RE to predetermined values of τED and /, as follows: (Formula Removed) where G1 is a monotooic function of rate estimate signal RE and sacisfres the relation: (Formula Removed) where G, is a monotonic function of rate estimate signal RE and satisfies the following relation; (Formula Removed) In one embodiment. £ED and Kte may have an approximately linear dependence on rate sscimate signal RE1, whereas Kbit may be nearly constant, In this embodiment, the solutions to equations (5) and (7) may be represented as follows; (Formula Removed) where g11,g12,g21, and g11, are parameters, which may depend on temperature of the interval of rate estimate signal RE. Similarly, the factions e. (RE) and 2, (RE) may be slowly varying functions of rate estimate signal RE and temperature. The parameters g11,g12,g21,g22 and e: may be selected to satisfy for example, aquations (5) and '7). Alternatively, g, and c, may be set to zero, Figure 4 is a block diagram of variable bit rate clock recovery circuit 400, which includes a calibration means, in accordance with an embodiment of the invention, Clock recovery circuit 400 comprises forward rate datactor 301, rate selector 410, transition detector 320, and narrow band filter 330, selector 420, programmable calibration sourca 430, and response monitor 450. Calibration source 430 generates, for example, a "1010" signal pactem with predetermined bit rates /re,v for example, (1/m) * 2438 MHz, where m is a programmable imeger between I and 32, inclusive. Response monitor 450 generates a first control sijrna] at output 454, which controls the particular value of frequencyƒref from calibration source 430. Selector 420, which is controlled by calibration enable line 421, receives input signal 15S and calibration source 430 at input ports 422 and 424, respectively, Rate selector 410 accepts rate estimate RE from forward rate detector 301 and outputs control signal RS1 for controlling transition detector 320 and control signal AS: for controlling narrow band filter 330. Calibrate enable line 421 activates the calibrate mode, at which time selector 420 connects calibration source 430 to forward rate detector 301, while outputs 416 and 41 8 of rate selector 410 are ocked at their current values. This inhibits incidental changes in the clock extraction path, which includes transition detector 3 20 and narrow band fileter 330, Response monitor 450 receives at input 452 a rate estimaie signal RE from output 303 of forward race detector 301,in auto-calibrate mod:, respons monitor 450 compares rats estimate signal RE with each predetermined bit rate fet. Response monitor 450 generates, at output 456, a second control signal RM, which corresponds to che difference between rate estimate signal RE and a predetermined bit rateftet. Rate selector 410 receives control signal RM it parameter update input 412. and based on control signal FLM, adjusts, for example, its rate selection algorithm or entries in a look-up cable for setting control signals RS1and RS1 for example, raw selector 410 may use parameters g11,g12,g21,g22 and /or functions τ1 and τ1, to adjust mappings of G, and Gl in equations (8) and (9). DISCRETE FORWARD RATE DETECTOR The time interval between transitions in input signal 15: may be represented as ▲l=Tbit where n is an integer greater than or equal to I and tbil is the bit period of input signal 155. In other words, ƒbit is equal to the multiplicative inverse of bit rate frequency ƒbit of in.put signal 155. Forward rate detector 301 msy estimate the bic race in input signal 155 from a plurality of consecutive transitions in input signal 155, which would represent a set {n} of values for run length n. From this set of transitions, forward rate detector 301 may determine the minimum detected interval" between transitions Tmint, which may be represented as follows: (Formula Removed) M Furthermore, t^a rr.ay represent an unbiased estimate of the bit rite tbjr as follows: (Formula Removed) Digital signals such as input signal 155 may have randorr. bit patterns or may have prescribed bit patterns constrained by block coding, For a random sequence of bits, the discrete probability density for run length n is P(n) * 2 Delay segments S1-SN connect to each other in serial fashion, where each delay ssgment S1-SN successively delays by time the falling edge initiated by input signal 155, where S1-SN Depending upoa the embodiment, the particular values of t1, may differ between delay segments St*Sy. As shown in Figurs ,5, delay segments S-S; include rescttible falling edge triggered delay elements 510^510, and OR/NOR gates 520,-5203, respectively, Outputs ofeach edge triggered delay e.ements 510,-510, connect to a respective first input 5241,-5241 of OR/NOR gates 5201,-5201, The last delay segment SNt, however, includes delay element 514N and an inverter 580 instead of an OR/NOR gats. Buffer 560, which receives input signal 155, drives delay segment S1Delay / e- segment S1 includes delay element 510,, whose output 5141, is sensed by a first input to OR/NOR gate 5201, which includes complementary output 5261, and output 5281, Output 528, of OR/NOR gate 520, drives the naxt delay segment S,. Accordingly, che falling edge transition of input signal 155 passes consecutively through each of delay segments S1.-SN. Fcr example, delay element 5101, delays output 5281, of delay segment S1 by time t1 and delay elements 5101. and 5102 delay output 5281; of delay segment Sj by time t1-t2 Hence,, the total delay through k delay segments may be represented as Aii the input transition propagates through delay segments S,-S v, consecutive outputs 5281,5281 may transition from a high state to a low state, while the corresponding complementary outputs 5261,5261 and 584 may transition from a low state to a high suite. Each falling edge transition in input signal 155 initiates a series of pulses, which are then compared to the arrival of a subsequent rising transition in input signal 155. D-type flip-flops 530,-530N perform the comparison by latching the State of delayed outputs 5261,-526N and 584 upon the subsequent rising transition in input signal 155. R'S latches 5501-550N receive and store the state of D-type flip-flop outputs 5361-536N via "SET" inputs 5521,5521, respectively. Outputs 5561,-556N, of R-S latches 5501-550N connect to inputs 5951,-595Nof N-lina priority encoder 590, which generates at output 598 the binary equivalent of the number of active outputs 536,-536N. Clock input 542 of counter 540 connects to input signa. 155. Counter 540 generates at output 544 a pulse, which resets R.S latches 5501,-550N after a. preset number of transitions, for example 32, in input signal 155. High speed operation is achieved by partitioning the ne; time delays into small intervals: -TV, and simultaneously resetting each delay element 5101,510N via common control line 574 of buffer 570. Buffer 570 delays the simultaneous reset signal, such that the minimum hold-time requirement of D-type flip-flops 530,o30v is satisfied. Operation of forward rate dewctor 301 may be initiated on the rising edge transitions in input signal 155 as well as the falling adgs transitions in input signal 155. Forward rate: detector 301 may, for example, include a duplicate circuit, which is driven by an inverted replica of input signal 155, for sensing the length ofeach pulse in input signal 155 following a rising transition in input signal 155. Figures 6a-e illustrate timing diagrams of input signal 155 as it propagatas through delay segments S1-SN, in accordance with an embodiment of the invention. Figures 6a-c show a falling edge transition in input signal 155 as it propagates through delay segments S1,-SN. At the end of a pulse in input signal 155, the delayed edge may pass through a portion or all of delay segments S1,-SN, Because a pulse with the shortest duration in input signal 155 would pass through the fewest number of delay segments S1-SN output 528,. of the Kth delay segment SK is at a nigh state when the sum K of delay times T, satisfies the constraint ntbil ∑where tbit equals the i=l multiplicative inverse of the bit rate frequency fallof input signal 155. As shown in Figurss 6b-a, outputs 5281, and 5281, of delay segments S1, and 52,. respectively, are activated within the n-cbil period of input signal 155, whereas outputs 528; and 584 of delay segments S1 and 5N are not activated within that time period. The waveforms indicated by the dashed lines in Figurss 6d-e show the state of outputs 5281 and 584, respectively, foe an input pulse of longer duration. After a small number of transitions input signal 155, depending on the run length distribution P(n), a pulse with n = I appears in the input signal 135, after which "ime the stats of outputs 5561,-556N represents an upper and lower bound on tbil The state of outputs 5S6.-556W tracks increasing and decreasing values of-tbil when the pulses from counter 540, for example, occasionally reset R-S latches 5501,550N. Priority encoder 590 dsrivss at output 598 a binary representation of tbil from the state of outputs 5561,-556N, This binary representation of \, is rate estimate signal RE, which is uniquely determined by tbil, and the particular values of t1-tN The resolution of the estimate of tbil , may be improved by performing multiple scans with different combinations of values for Table 1 lisvjs several common line rates in. input signal 155 and the segmemal delays •:., which may be used to distinguish between the line rates. The first two columns list some common line rateSƒbil and the corresponding bit interval tbil for input signal 155, respectively. The third column, lists the net delays for distinguishing between consecutive rates, which is the average of tbil for two cansecutjve rates, K Since the net delay through 4 delay segments may be represented as ∑ tbil the i=l segmsntal delays tf represent the differences between the net delays listed in the third column. The sagmemal delays, which are listed in the fourth column and may be readily achisved, demonstrate the feasibility of discrete rate detector 301 for operating over a wide range of line rates. TABLE (Table Removed) DELAY SEGMENT Figure 7 is A circuit diagram of delay segment S, (shown in Figure 5), in accordance with an embodiment of the invention. Although Fig'ire 7 shows a circuit diagram of delay segment S2, generalization to delay segments S1, and S1-SN is readily apparent. High speed performance may be optimized by merging the threshold function found in a traditional implementation of delay circuit 5101 with OR/NOR gate 520: using a. gated differencial amplifier. Input 512, of delay segment S, drives the base of transistor O701, which serves as a voltage follower. The emitter of O707, and a programmable current source /704 connect to capacitor C704 at output 5141, through resistor R706. Current from the emitter of O102 rapidly charges C100 to a preset value while the currsnt firom I705 discharges C704 at a controlled rate. The voltage at output 514, is sensed by s, gated differential amplifier, which includesO720 and S722, bases of Q720 and Q721, connect to output S141 and to a reference voltage V700, respectively, The emitters of transistors O720 and O722 connect v.a node 730 ca a fixed currant source /710 The base of a gating transistor O725 connects to common control line 574 via second input 512,. The collector and emitter of Oll4 connect to output 526, and node 730, respectively. The amplifier has inverting and non-inverting outputs at outputs 526, and 528,, respectively. Output 528, which connects to the i:ollector of g,j:, is obtained from the voltage drop across R723. Output 5262, which connects to the collectors of O720 arid O724 is obtained from the voltage drop across R726. The value of reference V740 may 'be altered by positive feedback via control ndde 742, which connects to output ,5262 to provide threshold lavel hysteresis, A. voltage greater than that sat by reference V 740at either output 5142, of common control line 574 forces output 526, to a low state and output 528, to a high state. In the last delay segment S.,. the gating transistor corresponding to O724may be omitted. In the initial quiescent state, input 512, and common control line 574 may be at a high state, and output 526, may be at a low state. In this state, the high signal on input 512, controls Q702 to preset the voltage across capacitor C700. A high signal at common control line 574 activates O720 and forces output 5281 to drive the next delay segment S1 to a hig;h state even before the voltage on C704 reaches the preset value. When input signal 155 transitions from a high state to a low state, common control line 574 goas low and turns O724 off. The initial state is held by the preset voltage across C,0,, which controls 0720, Depending on the time constant of the preceding dalay segment S1, sjfid the duration of the low state, the voltage at input 5I21; may transition to a low state at some time after input signal 155 transitions from a high state to a low state. This turns 0701, off and allows C704 to be discharged by current from lnt. If the duration of the low state is still sufficient, the Voltage at output 514, drops below the reference voltage set by K740 and causes output 526, to transition to a high state amd the output 528, to transition to a low state. The tow state at output 528, activates the delay element 5101, in subsequent delay segment 53 The response time following detection of a threshold may be improved by a positive feedback from output 526, to slightly vary V740. The time delay associawd with delay segment S, is governed by the charge conservation at output 5143. The value of time delay t1, may be determined by the difference between the preset voltage across CTW, V,WSET, the value V740th of reference voltage V740when control 742 is ac a low stats, differential amplifier offset voltage V05th at the switching threshold, tha value of capacitor C,704, stray capacicanc*Cs associated with output 5142, current l708 base current /, of £„„, arid the charge &(l701) stored in the emitter of O702 This relationship may be represented as follows: (Formula Removed) The resolution of tie discrete rate detector depends on the selection of time delays t1-TV, which may be programmed, for example, through the value of current /7M for each corresponding delay segment S1-SN. CONTINUOUS FORWARD RATE DETECTOR Figure 8 is a block diagram of forward rate detector 301, which performs continuous pulse- width auto-correlation, in accordaace wttk an fimbodimsnt of the invention. As sho\vn, forward rate detector 301 comprises minimum interval correlator 840, fesciback circuit 830, and output 303, Output 303, whose value is rate estimate signal RE, receives output 836 of feedback circuit S30. Minimum interval correlator 840 includes a tunable (or programmable) edge-triggered time interval generator 810 and an edge transition corr.parator 820, Time interval generator 810 receives at inputs 812 and 816 input signal 155 and output 336 of feedback circuit 830, respectively. In response to a transition in input signal 1 55, time interval generator 310 generates at outpu; 8 14 a corresponding transition delayed by rime t, which is controlled by rate sstimats signal RE. Alternatively, in response to a transition in input signal 155, time interval generator 810 may generate at output 814 a corresponding set of transitions delayed by a set of timss t, which may have different values and are contrclled by rate estimate signal RE. The value oft is related to rate estimate signal RE through a known relationship T - t(RE). Time interval generator 810 may, for example, be implemented such thac the product of rate estimate signal RE and t(RE) is nearly constant to a fust order. Edge transition, comparator 820 receives at inputs 822 and 824 input signal 155 and output 814 of interval generator 810, respectively. Output 826 of edge transition comparator 820 generates a signal, which is monotonically related to the difference between t and tbil Edge transition comparator 820 generatas at output 826 a positive pulse when a subsequent transition in input signal 155 occurs before r time has elapsed. Output 826 is received by input 832 of feedback c .rcuit 530, which outputs rate estimate signal RE ai output 836 to adjust T, such that a prescribed rate of puls«s ire generated at output 826. The time constants within the feedback circuit 830 may be controlled via input 834 by the rate of transitions in input signal 155. The prescribed rate of pulses from output 826 may have a constant duty cycle. Alternatively, the prescribed rate tnay depend on the rate of transitions in input signal 151 tn one embodiment, the relationship berwesn the rate estimate signal RE and l/'t may, for example, be linear. Output 836 of feedback circuit 830 controls t via negative feedback to input 816 of interval generator 810, The negative feedback sees rate estimate signal RE such that t(RE) equals tbil Hence, bit rate frequency fbil of ., input signal 155 may be determined based on rate estimate signal RE since bit rate frequeacyƒbilis ne;iriy proportional to rate estimate signs! RE. In addition, to reduce noise in rate estimate signal RE, forward rate detector 301 may also include, for example, an analog; or digital means in feedback circuit S30 or rite selector 3 10 for filtering noise in rate estimate signal RE. In at;cordar.ce with another embodiment of the invention, forward rate detector 301 may estimate tbil using a. pulse width auto-cocrelatiun method. Figures 9a-d illustrate the timing diagrams of input signal 155, output 81 4 of time interval generator 810, output 826 of edge transition comparator 820, in accordance with this embodiment Figure 9e illustrates the distribution of values at output 826 for different values oft and an sirbitrary fixed value of tbil. Figure 9a shows input signal 155 with a transition occurring at time t0 and a subsequent transition at Af ttbil The transition att= 0 triggers tim* interval generator 810, whose output pulse is delayed by t. Three values of r are indicated by fait F, slow S, and aligned A. Figures 9b and 9c illustrate state of output 314 of time interval generator 810 for two different embodiments. Figure 9d illustrates state of output 826 of edge transition comparator 820 for the two embodiments. In the first embodiment, time interval generator 810 includes one or more reaettablc idge triggered delay elements, for example delay elements 5101,S10N shown in Figure 5 . As saown in Figure 9b, in this embodiment, time interval generator 810 generates at output 814 a pulse, which stairs after t time has elapsed and is reset by the next transition in input signal 155. In the second embodiment, time interval generator includes an edge triggered one«shot, which is described below in detail. As shown in Figure 9c, in this embodiment, time interval generator 810 generates at output 814 a single pulse starting at time at = 0, which has duration T. In both embodiments, if time t is set shorter than tbil, as indicated by F, the next transition in input signal 155 occurs at ttbil after T rime has elapsed, and output 826 is set to a low state. If time r is set to a longer duration than Tbll, as indicated by S, a subsequent transition in input signal 155 at ttbil occurs before t time has ekipsed, ajnd output 826 is set to a high state. There is perfect alignment between the pulse generated ac output 814 of time interval generator £10 and input signal 155 when t tbil as indicated by A, and a transition in input .signal 155 that occurs at TW| overlaps with t. Output 826 may be in a high or a low stai;e when there is perfect alignment. Transitions, in Input signal 155 that occur long after time t may be ignored since they may represent a run of bits u/iih ttbil and n a 2. Figure 9e illustrates the distribution of values assumed by output 326 for different values of ? and a given value of tbil This distribution represents the rransfsr function of minium interval correlator 840, which includes time interval generator 810 and edge transition detector 820. Based on statistical interpretation of relative frequency, the graph in Figure 9e also illustrates the mean value at output 826 that would be observed after many instances of transitions of input signal 155. THs graph in Figure 9e has a steep slope at ttbil which distinguishes be:ween conditions F and S. The shape of the transition between F and S may be determined by, for example, the distribution p(n) of run lengths n. Edge transition comparator 820 compares the interval between the trailing edge of input sigail 155 and output 814 of time interval general or 810, and via feedback circuit 8:10, adjusts t to th« value tbil ƒbit After the settling time of feedback circuit 830, the adjusted r represents an-estimate of Tbil. Hence, in this embodiment, harmonic locking does not occur because the estimated tbil is uniquely related to ƒbit MINIMUM INTERVAL CORRELATOR Figure 10 shows a circuit diagram of minimum interval :orralator 840 (shown in Figure 8), in accordance with an embodiment of the invention. In this embodiment, the response to falling edge transitions and rising edge transitions in input signal 155 are effectuated through two separate paths. Minimum interval correlator 840 is partitioned into a falling edge triggered minimum interval correlator 1090 and a rising edge triggered minimum interval correlator 1092, Minimum interval correlators 1090 and 1092 each perform the functions of time interval generator illO and transition comparator 820 shown in Figure 8. Minimum interval correlators 1090 and 1092 include outputs 826, and 8262, which collectively form output 826 of minimum interval correlator 840. Although minimum interval correlators 1090 and 1092 include separate outputs 826, and 826:, their respective inputs 302t and 3023 connect to input signal 151 Minimum interval correlator 1090 includes tion-invsrtinj' buffer 1010, capacitor C,fll|l programmable currant source 71016, comparator ID30, voltags referenca l^aj,, non-inverting; buffer 1050, and positive edge triggered D type flip-flop 1070. Minimum interval correlator 1092 includes inverting buffer 1023, capacitor C1028 programmable current source l1026 comparator 1040, voltage refsrence V-1008 inverting buffer 1060, and positive-edge triggered D-type flip-flap 1080. Input 302, svhich includes nodes 302; and 302,, recaives input signal 155. Node 3021 connects to non-inverting inputs 1011 and 1052 of buffers 1010 and 1050. respectively, in minimum interval correlator 1090. Output 101-- of buffer 1010 connects via node 1003 to capacitor C1018, programmable current sourca l1016. and input 1032 of comparator 1030. Reference input 1034 of comparator 1030 connects to voltage reference V1036. Output 1036 of comparator 1030 connects to D input 1072 of D-cype flip-flop 1070, whose clock input 1074 is driven by output 1054 of buffer 1050. Node 3022 connects to inverting inputs 1022 and 1062 of buffers 1020 and 1060, respectively, in minimum interval correlator 1092. Output 1024 of buffer 1020 connects via node 1004 to capacitor C1028, programmable current source l1025 and input 1042 of comparator 1040. Reference input 1044 of compsxator 1040 connects to voltage referencs V1028 Output 1046 of comparator 1040 connects to D input 1082 of D-cype flip-flop 1080, whose clock input 1084 is driven by output 1064 of buffer 1060. Outputs 1076 and 1086 of D-type flip-flops 1070 and l080 form output 826, and S26:, respectively, Programming inputs 1017 and 1027 control via inpur8l6 current sources /1014and l1026 respectively. The operations of minimum interval correlators 1090 and 1092 are similar except that sill processing is active on opposite transitions in inp'it signal 155. The operation of minimum interval correlator 1090 is as follows: Output port 10!4 assumes a low impedance state with a preset output level of V preset when input 1012 is at a high state, and assumes a high impedance stats when input 1012 is at a low state. For example, PPRESBr may be more positive than reference voltage V1033A high state in input signal 155 causes buffer 1010 to charge capacitor C1018 to Vpreset Whan the input signal 155 undergoes a transition from.a high to a low state, current flow from output 1014 of buffer 1010 is inhibited, and capacitor £101I is freely discharged by programmable current from l1016. If the duration of the low state in input signal 155 is sufficiently long, the voltage at node 1003 drops below the level set by V1038 and output 1036 of comparator 1030 transitions to a low state. D-type flip-flop 1070 captures via the rising edge transition at the output 1054 of buffer 1050 the state of output 1036 at time t =ntbilwhen input signal 155 undergoes a subsequent low to high transition. The "ime required for capacitor C1018 to discharge from VPRESET to V1018is t(l1016). Output 82(5, may be at a low state if t =t(l1016). and may be at i high state if t =t(l1016)- Output 826, may always be law when t tbil there may be small, values of run-length i for which output 826, may be at a1 high stats. Output 826, may, however, be a.t a low state for large n, Figure 9e shows the distribution of values of output 826, averaged over typical values of run-length n The time constant t(l1016) may be represented as follows: where P^ is the offset voltage at a threshold of comparator 103 3, C5 is ihe stray capacitance associated with node 1003, l4 is the input bias current of comparator 1030, and Oo-1014 (l1016)is the chargs removed by output 1014 when buifer 10 10 is aimed off. Similar operation occurs in minimum interval correlator 1092 for rising adge transitions in input signal 155. Outputs 826, and 826; indicate whethsr - is greater or less than Tait. In accordance with one embodiment, outputs 826, and 826, may be used to control T through /916 and /1026 using negative feedback. Rate estimate signal RE may be determined ftom the value of control signal 816 necessary to achieve t = tbil. Minimum interval correlator 1090 of Figure 10 constitutes one smbodimsnt of a unipolar minimum interval correlator, which is active on the fa ling edge of input signal 155. Unipolar minimum interval correlator 1090 may include a programmable gated delay, which includes buffer 1010, capacitor C1018current source /1017 comparator 1013, arid D-type flip-flop 1070. D-cype flip-flop 1070 may include two latches (not shown), which ars controlled by node 302, via clock input 1074, la one embodiment, ona of the latches in 1070 may be shared with the programmable gated delay to create a falling edge triggered non-retriggerable one-shoi:. By performing several latching and comparison operations in parallel, higher operating speeds may be achieved in this embodiment. Figure 1 1 illustrates an emitter coupled logic (ECL) implementation of unipolar minimum interval correlator 1090, in accordance with an embodiment of the invention, Unipolar minimum interval correlator 1090 comprises edge transition comparator 1 104 and falling-edge triggered non-retrtggerable one-shot 1 102. Edge transition comparator 1104 includes inverters 1110 and 1156. non-inverting buffer 1114, NOR gates 1130 and 1150, and node 1138, Node 1138 performs a wired-OR operation. Falling edgs triggered non-retriggerablc one-shot 1102 includes comparator 1160, timing capacitor C1164 programmable current sources /1016 and /1779, diodes D1175 and Dn1it reference voltages VREF and PCUMP. operational ampliiter 1170, NOR gates 1120 and 1140, mverter 1146, buffer 1124, and nodes 1128 and 1166. Nodes 1128 and 1166 each perform a wired-OR operation. Input 1111 of inverter 1110 and nods 1144 of one-shot 1102 receive input signal 155, The falling edge of input signal 155 triggers one-shot 1102 Co generate an output pulse of duration t(/IB,,j) at output 1127 of buffer 1124. Duration t is directly controlled by controlled current source /1016 or indirectly by inpui, 816 via control input 1017 to /1016 Output 1127 of buffer 1124 is at a high state in the reset state, and transitions to a low state during time ?. One-shot 1102 cannot be retriggered by a subsequent change i:n the state of input signal 155 until after both time t has elapsed and input signal 155 returns to a high state. Input node 1144 connects co input 1142 of NOR gate 1143 and input 1121 of NOR gate 1120, The open emitter output 1143 of NOR gate 114D connects via node 1128 to input i; 122 of NOR gate 1120, input 1147 of inverter 1146, and non-invening open eminsr output 1126 of buffer 1124. Output 1148 of inverter 1146 connects to input 1141 of NOR gate 1140 to create an R-S latch. A high state at node 1144 sets node 1128 to a low state when output 1126 is low, while a high state at output 1126 overrides input 1144 to set node 1128 to a high State. Output 1126 of buffer 1124 may be at a high state during time T. and may inhibit NOR gate 1120 from responding to changes in input signal 155. Open emitter output 1123 of NOR gate 1120 connects via node ] 166 to the open emitter output of comparator 1160, capacitor C1164, and input 1125 of buffer 1124. Capacitor C1164 connects to non-inverting input 1161 of co-nparator 1160, the cathode of diode D1115 and programmable current source /1016. Output 1173 of opamp 1170 drives the anode of diode D1175,. Opamp 1170 may be configured, for example, as a voltage follower with diode D1176 in the feedback loop between output 1173 and inverting input 1172. Diode D1176 may be biased at the same current density as D1175 by programmable current source/l175 Node 1179 controls current /l175, and node 1017 controls current /l117 Both control node 1017 and control nods 1179 connect to input 816. Inverting input 1162 of comparator 1160 connects to voltage source PREF. Non-inverting input 1174 of opamp 1170 connects to voltage source VCLAMP. leaning output 1127 of buffer \ 124, which is controlled by node 1166, forms the output of ons-shot 1102, and connects to input 1134 of gate 1130 in edge iransition comparator 1104, In the quiescent state, the input signal 155 and input nodi; 1144 may be in the high staie, nodes 1128 and 1166 may be in the low state, and the voltage at node 1165 may be held at ^CUM?- Whw the input node 1144 transitions to a low state due to a negative transition in input signal 155, output 1123 of NOR gate 1120 transitions to a high state. The coupling through capacitor C,,w forces node II65 to a high state. A positive feedback through comparator 1160 and C1165 holds nods 1166 at a high state until the voltage at node 1165 decreases to VREF When node 1166 transitions to a high state after input sig.ial 155 transitions to a low state, buffer 1124 drives node 1128 to a high state, activating a first latch, which includes inverter 1146 and NOR gats 1140, Output 1123 of NOFl gate 1120 may be subsequently inhibited when node 1128 transitions to a high state. The first latch continues to hold node U28 at a high state, and inhibits output 1:. 23, which may only be reset after node 1166 transitions to a low state at time -. The first latch is reset to a low state through NOR gate 1140 when both node 1166 rsturns'to a low state and input signal 155 transitions to a high state, restoring one-shot 1102 to the quiescent state. The voltage on capacitor C1112 has sufficient time to reach steady state since one-shot 1102 triggers only on the falling edge transitions. The pulse duration ? may be related to the capacitor dischiirge current /. by conservation of charge at node 118J. This relationship may be rs presented as follows: (Formula Removed) where C5 is the stray capacitance associated with node 1165 and O1 is the charge stored m diode D1175 Vl166 represents the rising voltage waveform at 1166 after the falling transition m input signal 155 triggers one-shot 1102. ' In accordance with an embodiment of the invention, the parameters associated with comparator 1160 are as follows: /, is the input bias currant, V05this the input offset at threshold smd A Oth is the input charge required to swit:h comparator 1160. This expression shows that /1016 may be nearly proportional toyƒbitwhen t - tbit Non-invenng buffer 1114 receives output 1112 of the inverter It 10, which matches the turn-on, delay of one-shot 1102. NOR gate 1130 compares outputs 1116 and 1127 of buffer 1114 and one-shot 1102, respectively. Open jmitter output 1136 of NOR gate 1130 may be a current pulse, which may, for example, he a function of the time interval beween the subsequent rising edge in inpuc signal 155 and the rising edge of output 1127 of one-shot 1102 after delay time t. Node 1138 transitions to a high state when input signal 155 transitions to a high state while output 1127 of one-shot 1102 is at a low state. NOR gate 1150 and inverter 1156 connect to each other to form a second latch, which is activated by a high state at node 1128. If node 1138 is raised sufficiently high, :hen feedback loop around gate 1150 and inverter 1156 holds node 1138 at a high state until input signal -155 transitions to a low state and output 1H6 of gate 1114, which connects to NOR gate 1150, transitions to a high state. The relationship between the current pulse from output 1136 of gaie 1130 and T - tbit may be represented as follows: Charge O0 -1136 in the current pulse from gate 1130 is proportional to 7 t- tbit - £Tgale, where ξtgale is a fixed fraction of the nominal gate response-time. The probability that node 1138 may be set to a high state depends on 2o,in« through a 'function Fgale (Oo-1115), whose characteristics ,ire shown in Figure 9e. The average tim accordance with an embodiment of the invention. In this embodiment, feedback circuit 830 comprises a summation circuit 1210, a low pass fiUei 1220, a differencial amplifier 1230, and i reference voltage V250. Low pass filter 1220 includes an output 1224, and differential amplifier 1230 includes an output 1236. Figures 12b-d illustrate a change in bit rate of input signal 155, change la low-pass filter output 1224, and change in amplifier output 1236. Feedback circuit 830 receives at nodes 832, and 832}, which collectively form input 832, outputs i)26, and 826,, respectively, of minimum interval correlator 840. Node 832; connects, to input 1212 of summation circuit 1210, and Node 832, connect to summation circuit input 1214, Low pass filter 1220 filters output 1216 of summation circuit 1210, which is applied to non-inverting input 1232 of differential amplifier 12.30, Reference voltage V1250 connects to inverting input 1234 of differential amplifier 1230, Output 1236 of amplifier 1230 form;: feedback circuit output 836, Inputs 1212 and 1214 of summation 1210 receive nodes 132, and 33 22 pulses from outputs 826, and 825j of unipolar minimum interval correlators 1090 and 1092, respectively, when -e,,., Figure I2b illustrates an increase in bit rateƒbit of inpur signal 155 fromƒbit to /we >/biu occurring at time t- 0. The change in the bit rate is detscted by minimum interval correlator 840, which generates a change in the rate of pulses chat appear at .inputs 1212 sind 1214 of summation 1210 and consequently at output 1216. The level at output 1224 for t 0 at output 1216 generates a transient change in output 1224. The implified signal appearing at output 1236 changes until period ? of time interval generator 810 settle* to a new value of l/ƒbit. Minimum interval correlator 840 may generate an output pulse when isolated "ones" and "zeroes' occur in input signal 135. Input 1212, which is connected to falling edge transition comparator output 826, via node 332,, may be active following high-to-low transitions in Input signal IS5, The probability that output 816, transitions to a high state following an isolated "zero" may be represented by F(t Tbll), as shown in Figure 9e. Let po(n) and P1(n) denote the distribution of run lengths n for consecutive "zeroes" and "ones," respectively, in input signal 151 The probability that an isolated "zero" occurs following a high-to-low transition is therefore P,,0 = 1). The occurrence rate of isolated "zeroes" may be represented as follows: rate of isolated 0 - -=- where noand n1 represent the average length for a run of "zeroes" and "ones," respectively, The average time interval that output 826, remains at a high state prior to a subsequent high-to-low transition can be represented as follows: persistence time = (n1 + (, n0)tbit The holding property of the edge transition detector 820 may be represented by parameter (. In an tmbodiment where minimum interval correlator 1090 includes D-type flip-flop 1070, £ may equal 1. Alternatively , in an smbodiraent where minimum interval correlator 1090 includes falling edge triggered non-retriijgerable one-shot 1 102, C may equal 0. If the durations of consecutive runs are independent, the average value of input 1212 may be represented as follows; V1212- (rate of isolated 0) x f(t - tbit) x (persistence time) An analogous expression to equation 13 applies to input 1214 of rising edge transition comparator output 826j. The filtered output 1224 may be represented as follows: In accordance with an embodiment, the average value V1224 of low-pass filter output 1224 may be used to control t using a negative feedback. The sriali-signai gain has the desirable feature that it Is independent of Tbil. DIGITAL FEEDBACK CIRCUIT Figure 13a illustrates a digital implementation of feedback circuit 830, in accordance with an embodiment of the invention. In this embodiment, feedback circuit 830 comprises R-S latches 1310 and 1320, positive D-typ.s flip-flops 1330 aad 1340, AND gatss 1350 and 1360, N-stage up/down countsr 1 370, M-stage binary counter 1 390, and digital to analog converter (DAC) 1380. Up/down counter 1370 includes up-count clock (Clky) input 1372 and down-count clock (Clk0) input 1374 Figures I3b-e illustrate changes in bit rate/b(t of input signal 155, signal applied co Clky input 1372, signal applied to Clk0 input 1374, and analog output 1384 of DAC 1380, Feedback circuit 830 receives at inputs 832, and 832, outputs 826, and 826:, respectively, of minimum interval correlator 840. Input 834 of faedback circuit 830 receives input signal 155. Node 832, connects to "set" input 13-12 of latch 1310, and node 832, connects to "set" input 1322 of latch 1320. Latch outputs 1 3lfi and 1326 connect to inputs 1332 and 1342 of D-type flip-Gops 1330 and D40, respectively. Clock input 1392 of counter 1390 receives input signal t:iS via input 834. Terminal count (TC) output 1396 connects to "reset" inputs 1314 and 1324 of latches 1310 and 1320, respectively, Clock inputs 1334 and 1344 of D-type flip-flops 1330 and 1340 connect to the second stage (0,) output 1394 of counter 1390. AND gate 1 350 receives inputs from non-inverting outputs 1336 and 1346 of D-rype flip-flops 1330 and 1340, respectively, and TC output 1396 of counter 1390. AND gate 1360 receives inputs from inverting outputs 1338 and 1348 of D-rype flip-flops 1330 and 1.340, respectively, and TC output 1396 of cojnter 1390. Output 1358 of AND gate 1350 connects to Clky input 1372, and output 1368 of AND gate 1360 connects :o ClkD input 1374. In one embodiment, up/down counter 1370 generates a parallel binary word, which is monotonically related to the difference between the number of pulses applied to Clky input 1372 and Clk0 input (374. In andther embodiment, up/down counter 1370 generates a parallel binary signal representing a successive approximation for rate estimate signal RE using a succession of step sizes, which may, for example, vary with the pattern of pulses applied to Clku Input 1372 and Clkc input 1374. "Set" inputs 1312 and 1324 of latches 1310 and 1320 receive pulses from outputs 826, and 826,, respectively, of unipolar minimum interval correlators 1090 and 1092 when T > tbit is detected by edge transition comparator 820 via nodes 832, and 832,. A pulse generated by unipolar minimum interval correlator 1090, which is active on filling edge transitions in input signal 155, sets output 1316 to a high stats. Similarly, a pulse generated by unipolar minimum interval corelator 1092, which is active on rising edge transitions in input signal 155, sets ouipui: 1326 to a high state. Counter 1390 counts the number of transitions in input signal 155 modulo 2M. where A/equals, for example, 4. Second stage (Q^) output 1394 clocks D-cype flip-flops 1330 and 1340 oo, every fourth law-to-high transition in i.iput signal 155, storing the prevailing state of latches 1310 and 1320, respectively. TC output 1396 transitions to a high state following eacK 2M low-to-higb transitions in inpm: signal 155, and transitions to a low srate after the next low«to-high transition in input signal 153. The rising edge of TC output [396 may be near the canter of puJses fircim O1 output 1394, A high state on TC output 1396 enables AND gate outputs; 1358 and 1368, and resets latches 1310 and 1320 to a low state. Output 358 transitions to a high SUM when TC output i 396 is at a high stats if both D-ty;pe flip-flop non-inverting outputs 1336 and 1346 arc at a high state, advancing the state of up/down counter 1370 forward by one count. Output 1368 transitions to a high state whan TC output 1396 is at a high state if both D-type flip- flop inverting outputs 1338 and 1348 are ata high state, decreasing che state of up/down counter 1370 by one count. The state of up/down counter 1370 increases when both unipolar minimum interval correlators 1090 and 1C92 detect r > tbil, and decreases when neither unipolar minimum interval correlator 1090 and 1092 detect -r > tbitThe state of up/down counter 1370 holds whsn only onts of unipolar minimum interval correlators 1090 and 1092 detects t > tbit. The binary signal at up/down counter output 1376 may be used to control: using negative feedback. Feedback circuit 830 may generate a digital signal at output 836 using, for example, output 1376 of up/down counter 1370. Alternatively, feedback, circuit 830 may generate an Jinalog signal at output 836 using, for example, output 1384 of DAC U80, whose input 1382 connects to counter output 1376. Figure I3b illustrates an increase in bit ratsƒbit, of input signal 155 fromƒbit, to ƒbit>ƒbit at time l=0. negative feedback may hold period r of interval generator 810 close to l/ƒbit Minimum interval correlator 840 may detect the change in che bit rate, which results in a change in the rate of pulses iha appear at both latch inputs 1J12 and 1,324, The presence of pulses at both latch inputs 1312 and 1324 causes both, D-type flip-flop non-inverting outputs 1336 and 1316 to transition to a high state, toggling Clku input 1372 as shown in Figures 13c. In Figura 13d, CJk0 input 1374 is not toggled immediately after t = 0 since t > l^tii' Figure 13e dlustrates analog output 1384 of DAC 1380, .vhich is driven by digital words generated by up/down counter 1370 with, for exaraple, rnonotonic count states. In up/down counter 1370. upward counting proceeds while T > !/ƒbit and stops when t - l/ƒbit RATE SELECTOR Rate selector 310 tracks changes in the bit rate frequency of input signal 155 while rejecting cransient errors in the rate estimate signal RE, which may be caused by jircer and pattern dependent variation in input signal 155. Figures 14a,-b are block diagrams of implementations of rate selector 310, in accordance with two embodiments of the invention. In the first embodiment, which is shown in Figure 14a. rate selector 310 comprises a race translation 1402, which includes a function block 1410 and a. function block 1420. Rate translation 1402 may receive as input rate estimate signal R£, which is generated by discrete ratedetector 301 of Figure 5. The rati astimate signal RE may also be filtered prior to translation by 1402. In ch« second embodiment, which is shown in Figure 14b, rate selector 310 comprises rate translation 1402 and a rate estimate filter. The rate estimate filter includes a rate correction block 1430, adaptive filter 1440. filter control 1450, rate change detector 1460, expected rate comparator 1470, and summation 1480. Correction block 1430 receives at input 1432 rate estimate signal RE, which may be generated by, for example, continuous rate detector 301 of Figure 8, Adaptive filter 1440 receives at inpui 1442 output 1434 of rate correction block 1430. The output of filter 1440 may be applied as an alternative input to rate translation 1402. Rate translation block 1402 performs a direct one-to-or.e mapping of an estimated line rate into control signals AS1, and AS2, which appoar at output nodes 316 and 318, respectively, Input 1412 of function block 1410 and input 1422 of function block 1420 receive an estimate of the line rate, for example, rate estimate signal R£ from discrete rate detector 301 or output from adaptive filter 1430. Function block 1410 generates control signal AS, at node 316. Function block 1410 may implement, for sxampls, the firnctton implicitly represented by equation (5) or the relationship represented by equation (8). Function block 1420 generates control signal AS, at node 318. Function blgck 1420 may implement, for example, the function implicitly represented by equation (5) or the relationship represented by equation (8). • Several conventional techniques may be used to perfonr. the one-to-one mapping. For example, an analog computer may be used to convert the rate estimate signal R£ into coniiol signals AS, and AS:. Alternately, rate dewctor 301 or rate selector 310 may be implemented using an .VD converter whose binary outputs select an appropriate entry from a look-up table for control signals AS, and AS;. The look-up table nuy include rate specific parameters for TED and ƒe In yet another implementation, rate selector 310 may inc.ude a finite-state machine for converting a digitized rate estimate signal RE into control signals RS, and RS2 using, for example, an appropriate mapping algorithm. When used in conjunction with, for example, continuous rate dececror 301 of Figure 8, rate correction 1430 and adaptive filter 1440 may improve the accuracy of the lin« rate estimate, which is received by rate translation 1402. Rate estimate signal RE is applied to input 1432 of rate correction block 1430. Output 1434 from correction block 1430 goes to input 1442 of adaptive filter 1443, input 1462 of rate change detector 1460, and input 1472 of expecce.d rate comparator 1470. Input 1444 controls the response of filter 1440. Input signal 155 is also applied via node 114 to inputs 1464 and 1474 of rate change detector 1460 and expected rate comparator 1470, respectively. The rate at which operations are performed within rate change detector 1460 and expected rate comparator 1470 may, for example, be controlled by input signal 155 via input 314, Rate change detector 1460 includes output (466, and expected rate comparator 1470 includes output 1476, Outputs 1466 and 1476 are combined in summation 1480, and applied to input 1452 of filter control 1450. niter control 1450 includes output 1454, which is applied to input 1444 of adaptive filter 1440. Adaptive filter output: 1446 connects to inputs 1412 and 1422 of function blocks 1410 and 1420, respectively. Rate estimate signal RE appearing at input 312 of rats detector 301 may include predictable or measured error. Correction block 1430 may implement an algorithm, which compensates for predicted or measured discrepancy between the rate estimate signal RE and the bit rate of input signal 155, Adaptive fi.lter 1440 outputs a modified rate estimate ££.-, which depends on the current value of:'rate estimate signal Wand the current value's relationship to the past behavior of rate estimate signal HE. Considering the behavior of rate estimate signal RE and modified rate estimate signal RE? at a set of discrete times, the currant and past values of rate estimate signal RE may be represented by the set of values {RE,} while the corresponding values of modified raw estimate signal REF may be represented by the siet of values (R£fi}. Adaptive filter 1440 may, for example, construct modified rate estimate signal REF from rate estimate signal R.E using the fallowing relationship: where a1 and b1 are coefficients which may be programmed through input 1444 subject. Filter 1440, which includes an implementation of equation 15. reacts rapidly to changing rate estjnate signal RE when coefficient a, is large, .ind conversely, reacts slowly when coefficients a, are large for i>>1. Coefficients b, may be selected to affect persistent memory of a particular estimate. The constraint £ a{ * 1 may ' V* prevent bias in modified rate estimate signal REft while the cotistraint ∑b1 i avert instability. Coefficients a, and b, may be selected based on patterns in the variation of rate estimate signal R£ following a correction by rate correction 1430. Rate change detector 1460 may distinguish sraalJ or insignificant fluctuations in rate estimate sijjnal RE, which is applied to input 1462, frorr. rapid or significant changes in the corrected rate estimate. Rate change decector 1-60 may construct a histogram of rate change values, and compute the likelihood ttut a current race change is significantly different from rate changes in the recent past. The magnitude of output 1466 may reflect the magnitude or duration of a change in the current rate estimate relative to previous changes. The response time for performing rate change discrimination may be set by the rate of transitions at input 146 i. Expected rare comparator 1470 may compare the current rate estimate signal RE with known common line rates or previous values of (RE}', which have persisted for a significant time interval. The magnitude of output 1475 may reflect the proximity of rate estimate signal R£ to known rates or previous persistent rates. The response time for comparing rate estimate signal RE against expected rates may be set based on the rate or" transitions at input 1464. While it hail been illustrated and described what are at present considered to be preferred embodiments and methods of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the tru scope of the invention. In addition, many modifications may be made to adapt a particular element, technique or implementation to the teachings of the present invention without daparting from the central scope of the invention. Therefore, ic is intended that this invention not be limited co the particular embodiments and methods disclosed herein, but that the invention include all embodiment! failing within the scope of the appended claims. CLAIM:- 1. A method of operating a clock recovery circuit (300) to recover a clock signal from an input signal having a variable bit rate, said method being characterized in that it comprises the steps of: estimating a minimum time interval between transitions in the input signal by a rate detector (301); generating a first plurality of pulses corresponding respectively to transitions in the input signal by the transition detector (320); adjusting the duration of each of the first plurality of pulses based on the estimated minimum time interval and inputting into a narrow-band filter the adjusted first plurality of pulses by the rate selector (310); determining a center frequency of the narrow-band filter based on the generated minimum time interval by the narrow band filter (330); and extracting the clock signal from the adjusted first plurality of pulses by the narrow band filter (330). 2. The method performed by the said clock recovery circuit as claimed in claim 1, wherein the estimating step comprises the steps of: generating a second plurality of pulses that correlate to the transitions in the input signal by a programmable time interval generator (810); and adjusting the duration of each of the second plurality of pulses by the transition comparator (820), such that the minimum time intervals between the transitions in the input signal match the durations of the corresponding second plurality of pulses. 3. The method performed by the said clock recovery as claimed in claim 1, wherein the extracting step comprises the steps of: generating a phase correction signal proportional to a difference between a phase of the clock signal and a phase of the first plurality of pulses by the phase comparator (220); and adding the phase correction signal to a center frequency of an oscillator generating the clock signal by the phase adder. 4. The method performed by the said clock recovery circuit as claimed in any one of the preceding claims, wherein the adjusting step comprises the steps of: generating a voltage signal corresponding to the difference between the minimum time interval between transitions in the input signal and the duration of the corresponding second plurality of pulses by the said interval generator (810); and generating a current signal proportional to the voltage signal, wherein the current signal controls the durations of each of the second plurality of pulses by the frequency comparator. 5. The method performed by the said clock recovery circuit as claimed in claim 1, wherein the estimating step comprises the steps of: generating a set of delayed input signals by passing the input signal through a set of delay segments (SI-SN), wherein the set of delay segments delay the input signal based on a set of specific delay times generating a control signal based on a sum of the specific delay times that are less than the minimum time interval between transitions in the input signal by the set of latches (5501-550N). 6. The method performed by the said clock recovery circuit as claimed in claim 1, wherein the estimating step comprises the steps of: generating a set of delayed input signals by passing the input signal serially through a set of programmable delay segments, wherein the set of programmable delay segments delay the input signal based on a set of specific delay times; generating a control signal based on a sum of the specific delay times that are less than the minimum time interval between transitions in the input signal by the transition comparator (820). 7. The method performed by the said clock recovery circuit as claimed in claim 1, wherein the estimating step comprises the steps of: generating one or more delayed transitions by passing the input signal through a programmable time interval generator (810), wherein the delayed transitions are generated based on a set of delay time values, respectively; comparing transitions in the input signal with the generated delayed transitions by the said time interval generator, and adjusting one or more of the delay time values, such that one of the delay time values matches the minimum time interval between the transitions in the input signal by the said time interval genertor. 8. An apparatus for recovering a clock signal from an input signal having a variable bit rate, said apparatus being characterized in that it comprises: a rate detector (301) for estimating a minimum time interval between transitions in the input signal; a transition detector (320) for generating a first plurality of pulses corresponding respectively to transitions in the input signal; a narrow-band filter (330) connected to said transition detector, and a rate selector (310) connected to said rate detector, said rate selector connected to said transition detector for adjusting, based on the estimated minimum time interval, the duration of each of the first plurality of pulses, and connected to said narrow-band filter for determining a center frequency of the narrow-band filter that receives the adjusted first plurality of pulses from said transition detector, said narrow-band filter outputting the recovered clock signal. 9. The apparatus as claimed in claim 8, wherein said rate detector comprises: a set of delay segments (S1-SN) connected in series for generating a set of delayed input signals based on a set of specific delay times, respectively, and a set of latches (550i-550N) connected to the set of delay segments, respectively, for generating a control signal based on a sum of the specific delay times that are less than the minimum time interval between transitions in the input signal. 10. The apparatus as claimed in claim 8, wherein said rate detector comprises: a programmable time interval generator (810) for generating a set of delayed transitions based on a set of delay time values, respectively; and an edge transition comparator (820) connected to the programmable time interval generator for comparing the set of delayed transitions with transitions in the input signal and adjusting one or more the delay time values, such that one of the time delay values matches the minimum time interval between the transitions in the input signal. 11. The apparatus as claimed in claim 8, further comprising: a calibration source (430) for generating a calibration signal having a set of specific reference bit rates, wherein the rate detector estimates the reference bit rate of the calibration signal; and a response monitor (450) for determining differences between the specific reference bit rates and the estimated reference bit rate and for adjusting the rate selector until the one of the determined differences equals zero. 12. The apparatus as claimed in claim 8, wherein the rate detector comprises: an interval generator (810) for generating a second plurality of transitions that correlate to the transitions of the input signal; a transition comparator (820) for determining a difference between the duration of each of the second plurality of transitions and a time interval between teach of the transitions in the input signal; and a feedback means (830) for adjusting the duration of each of the second plurality of transitions until the determined difference equals zero. 13. The apparatus as claimed in claim 8, wherein the narrow-band filter comprises: a phase comparator for generating a phase correction signal proportional to a difference between a phase of the clock signal and a phase of the adjusted first plurality of pulses; and a first adder for adding the phase correction signal to a center frequency of an oscillator generating the clock signal. 14. The apparatus as claimed in claim 13, wherein the narrow-band filter further comprises: a frequency comparator for generating a frequency correction signal proportional to a difference between a frequency of the clock signal and a frequency of the adjusted first plurality of pulses; and a second adder for adding the frequency correction signal to a center frequency of the oscillator generating the clock signal. 15. The apparatus as claimed in claim 12, wherein the interval generator comprises: an edge triggered one-shot for generating a second plurality of pulses that correlate to the transitions in the input signal. 16. The apparatus as claimed in claim 12, wherein the interval generator comprises: one or more resettable edge triggered delay elements (510i-510N) for generating a second plurality of pulses that correlate to the transitions in the input signal. 17. A method for recovering a clock signal substantially as herein described with reference to the accompanying drawings and description. 18. An apparatus for recovering a clock signal substantially as herein described with reference to the accompanying drawings and description. |
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| Patent Number | 215102 | |||||||||
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| Indian Patent Application Number | 3665/DEL/1998 | |||||||||
| PG Journal Number | 10/2008 | |||||||||
| Publication Date | 07-Mar-2008 | |||||||||
| Grant Date | 21-Feb-2008 | |||||||||
| Date of Filing | 04-Dec-1998 | |||||||||
| Name of Patentee | TELECORDIA TECHNOLOGIES INC. | |||||||||
| Applicant Address | 445 SOUTH STREET, MORRISTOWN, NEW JERSEY 07960, UNITED STETE OF AMERICA. | |||||||||
Inventors:
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| PCT International Classification Number | H04L | |||||||||
| PCT International Application Number | N/A | |||||||||
| PCT International Filing date | ||||||||||
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