Title of Invention

"A DIGITAL PHASE-LOCKED LOOP AND A METHOD AND SYSTEM FOR CONTROLLING IT"

Abstract

A digital phase-locked loop comprises a numerically controlled oscillator (5) which is capable of generating a clock signal by dividing a system clock frequency by a factor determined by a control word, and a phase detector (2 ; 3) which is capable of generating the control signal and an response to a phase difference between the clock signal and an external reference signal so that the control word assumes a nominal value when the phase difference is numerically smaller than a given value, and may assume one or more other values when the phase difference is numerically greater than the given value. The loop moreover comprises means (7) which, when the phase difference is numerically greater than the given value, may modulate the control word. A corresponding method is also disclosed. The digital phase-locked loop may be used in a receiver system for a digital transmission system in connection with desyncronization of data signals.

Full Text

The invention relates to a digital phase-locked loop comprising a numerically controlled oscillator which is adapted to generate a clock signal by dividing a system clock frequency by a factor determined by a control word, and a phase detector which is adapted to generate the control word in response to a phase difference between the clock signal and an external reference signal, so that the control word assumes a nominal value when the phase difference is numerically smaller than a value given in advance, and may assume one or more other values when the phase difference is numerically greater than the given value. The invention also relates to a method of controlling such a digital phase-locked loop. Finally, the invention relates to a method of desynchronization in a receiver in a digital transmission system, wherein justification is performed by adding or removing one or more bits, as needed, in the transmitted bit flow on the transmission side when placing e.g. telephone calls in the transmission system and wherein the effect of the added and removed bits is smoothed in the receiver in the desynchronization, and wherein a digital phase-locked loop is used, as well as to a receiver circuit for use in this connection. Today, digital phase-locked loops are used in large numbers in digital circuits. An example of the use is in connection with pointer adjustments in digitally built telecommunications networks, such as e.g. SDH networks (Synchronous Digital Hierarchy). This type of network is based on one or more extremely stable clock signals. Not- withstanding that the network includes extremely stable references, differences between phase and frequency of the references may arise, e.g. as a consequence of tem¬perature effects on the corutiunications channels between the nodes of the network. The network eleirents in such a communications retwork must be capable of tolerating these not by varistions ir. phase and frequency without date in the form of communications signals being lost. This may be ensured by making pointer adjustnents comprising add¬ing or removing a number of bits or bytfrs in the data flow. A fracie structure is used whan transmitting data, so that data in th-s fonri of e.g. telephone calls have a special position in the frame,- while signals for controlling and monitoring the communication have another position in the frame. These signals arc called overheact signals. The structure of these overhead signals reserves a plurality of hytes, e.g. three bytes, which raay be used ir. connec¬tion with pointer adjustments and therefore do not con¬tain any other information. It is possible to fill some of these bytes with data proper in a transmitter in the network wher. additional data have to be added (negative pointer adjustment), or to insert on* or more empty bytes among the data proper when data are :c be removed (positive pointer adjustment), in order to conpensate for the* mentioned deviations in phase and frtoiency with re¬spect to tna other elements in the network When this form of compensation is used, the transferred signal will receive jitter. Jitter means that a digital signal briefly differs from its correct position in tine, or ir. other words a phase jump is imparted to it. Pointer adjustments may also occur in SDH network ele¬ments when a PDK system (Pltsioehronous Digital Hitrar- chy) Is to be inserted into the SDK frame structure. A frame structure frequently used for transport between the network elements in an SDK system is an 3TM-1 frame which has a bit frequency of 155 Mbits/sec and can transport 63 TU-12 signals, each having a bit frequency of 2 Mbits/sec. The STM-i frames are transmitted with 8 kHz. In the network elements where thass conpsasaCed (pointer adjusted) communications signals are received, e.g. in demultiplexers, it will be attempted to neutralize the effect of these adjustments by low-pass filtering the phase jumps which they have caused. This may be done e.g. by inputting the incoming data in a suffer with a jitter) clock signal derived fror. the data signal and then outputting them again with a stabilized clock .sig¬nal, which has been formed by feeding the jitter clock -signal through a phase-locked loop. This corresponds to low-pass filtering of the jitter effect, the phase varia¬tions between the inconing and the stabilized clock gig-nal being low-pass filtered in the phase-locked loop. Today, such a circuit is typically implented on a spe¬cial customer-designed integrated circuit/ e.g. an ASIC circuit. This means that, as far as possible, all subcir-euits must be realized without the use of analog compo¬nents, and the phase-locked loop will therefore prefer¬ably be implemented as a digital pha-se-lockcd loop (DPLL) . A digital phase-locked loop is usuailly based en a numerically controlled oscillator (NCO) and hag the draw¬back with respect to an analog phase-locked loop that the frequency of the emitted clock signal cannot vary con¬tinuously, but can only switch between -a plurality of discrete, values, as the clock signal is typically gener¬ated by division in discrete stages of an internal clock frequency for the customer-designed circuit. This neans that when the phase-locked loop adjusts e.g. in order to be able to compensate for a pointer adjust¬ment, the frequency of the NCO is changed to another dis-creta value, which is then used until the ttffeCE has been compensated, following which the NCO returns tc its original frequency. These frequency jumps are unsortunate for the following circuits, and it would therefore be de¬sirable if the size of the frequency jumps could be re¬duced, while then spending nore time on compensating the effect of a pointer adjustment. Such a circuit in which jitter is compensated ov xeaas of a digital chase-locked loop is known from us 5 479 457. The frequency of the numerically contrclled oscrllatorr can also here only switch between a numder of discrete values end also this circuit does, therefore, not avoid the unwanted frequency jumps. It .is known from US Pater.t 5 245 636 to reduce jitteer caused by pointer' adjitmenes by dlviding each phase jump into a plurality of ssialler phase jumps, which are then smcothed separately. Although this solution gives a cer¬tain reduction in the effect of the actual phase junip, it does not change The fact that when a digital phase-locked loop is usftd, a juiup will occur between di screte frequen¬cies. In a different: nontext (i.e. generation of a clock signal synchronized to -a- signal that is noduiatt-c by ASK) it is known from US 4 947 407 to let an NCO in a partly digital phase-lccfcad loop switch between two discrste frequencies controlled by a pulse signal whose duty cycle is regulated by neans of an analog feedback circuit. This known circuit is able to regulate the output frequency substantially continouily. However, this pcinciple cannot be used in a purely digital phase-locked loop in which the numerically controlled oscillator is controlled by a control word as it is the case in the present invention. Accordingly, an object of the invention is to provide a digital phase-locked loop of the type defined in the opening paragraph where the size of said frequency jumps may be reduced considerably, and where the loop may simultaneously be implemented exclusively by using digital components. This is achieved according to the invention in that the loop comprises means which, when the phase difference is numerically greater than the given value, are capable of modulating the control word so that said word assumes one of the one or more other values in subperiods, while it assumes the nominal value in intermediate periods. Accordingly, there is also provided a receiver system for use in digital transmission system and adapted to receive and desynchronize data signals in the form of a bit flow, wherein justification is performed by adding or removing, as needed, one or more bits in the transmitted bit flow on the transmission side when placing e.g. telephone calls in the transmission system, and wherein the receiver circuit is moreover adapted to smooth the effect of the added and removed bits in the desynchronization, and wherein the receiver system comprises a digital phase-locked loop as claimed in claim 1, having a numerically controlled oscillator (5) which is adapted to generate a clock signal by dividing a system clock frequency by a factor determined by a control word, and a phase detector (2;3) which is adapted to generate said control word in response to phase difference between said clock signal and a reference clock signal derived from the data signals received, so that the control word assumes a nominal value when said phase difference is numerically smaller than a value given in advance, and may assume one or more other values when the phase difference is numerically greater than the given value, wherein the digital phase-locked loop moreover comprises means (7) which, when the phase difference is numerically greater than the given value, may modulate the control word so that it assumes one of the one or more other values in subperiods, while it assumes the nominal value in intermediate periods. Thus, by just emitting the control word which means that the numerically controlled oscillator is to run with an other frequency than the nominal one for a fraction of the time, the oscillator will also just use the higher or lower frequency for a fraction of the time, while it will still use the nominal frequency for the rest of the time. This means in practice that the oscillator will emit a frequency which differs significantly less from the nominal frequency than the difference between two discrete adjacent frequencies. As stated in claim 2, in addition to the nominal value, the control word may expediently assume at least one other value when the phase difference indicates that the clock signal frequency is lower than the reference signal frequency, and at least one other value when the clock signal frequency is higher than the reference signal frequency. A particularly expedient enbodircent is obtained when/ as stated in'claim 3, the control word nay assume two values (•(•1, .+2) when the phase difference indicates that the clock signal frequency is lower than the reference signal frequency, and two values (-1, -2) wher. 'the clock signal frequency is higher than the reference signal frequency/ and wher. the modulation means ara adapted to modulate the control word only when it assumes the values (+lf -1) which correspond to the numerically smallest phase dif¬ference. This means that minor deviations nay be smoothed slowly, while great phase differences, which just occur very rarely, may be smoothed quickly, since/ otherwise, e.g. data would tend to be lost. When, like in clairr. 4, the modulation z.snns are adapted to modulate the control word with a pulse signal which has a fixed cycle time and a variable pulss width, a very flexible control is achieved. Further, as stated in claim 5, the digital phase-locked loop may comprise means for controlling the pulse width in response to said phase difference. This allows the size of the resulting fre¬quency jumps to be controlled ir. responss to the phase difference, so that a somewhat greater phase difference may be adjusted relatively more quickly thar. a smaller one. As mentioned, the invention also relates to a method of controlling such a digital phase-locked loop, wherein the control word is modulated as described above. In the method, too, this results in the generation of a fre¬quency in practice which differs considerably less iron the nominal frequency than, the difference between two discrete adjacent frequencies. This method is defined in claim 6. The irsv&ntior. rr.oreover relates to a method of desynchro-nization in a receiver in a digital transmission system, wherein the control word In a digital phase-locked loop is nodulated as described accve, ar.d to a corresponding receiver circuit. The method is defined in claiir. 7, and. the receiver circuit in claim' 3. When, in this connec¬tion., the control word is modulated as described above, it is ensured that pointer adjustments i" 6.g. an SDH system, may be sncothed without the graat frequency jumps which a digital phase-locked loop would otherwise in¬volve, and which might cause loss of data. In an expedient embodiment, which is defined in claiir. 9, » the receiver circuit comprises a buffer circuit adapted such that the_jreceived data signals may bs input in the buffer circuit by neans ofjthe reference c^.ock signal and be output again by means of said clock sicnal. The phase deteccor cf the digital phase locked loop is .formed by the buffer circuit, and the number of data signals, which are input in but not yet output froir. the buffer circuit, are vised as ar. indication of the phase difference between said clock signal and the reference clock signal. This obviates the need for a phase detector proper for compar¬ing the two clock signals. In connection with an SDH systen the buffer circuit may be constructed as ring buffer and be adapted to store 12 bytes, as stated in claim 10. Claims 11-14 define expedient embodiments which corre¬spond to rhose described above for the digital phase-locked loop. As stated in clain 15, the receiver circuit may comprise neans to generate the control word in response to a high¬est value of the number of data signals which are input but not output from the buffer circuit, measured over a period of time. This ensures stable ccrtrci, since fluc-tuaticns caused by brief, cganses in the fi..Iing degree of the buffer are obviated. As stated in claim 16, for use in an SDH system the nu¬ merically controlled oscillator may expediently be adapted to generate a clocic signal whose nominal fre¬ quency is 7. .112 MnZ. The invention will now be described ;c.ore fully below with reference to the drawing, in which fig. I shows a circuit ir. which the inventio may be ap¬ plied, , fig. 2 shows an alternative embodiment of the circuit of fig. 1, A fig. 3 shows how a filter may be constructed according tc the invention/ and - fig. 4 shows an example of a structure of 1 detector cir¬cuit for uss in connection with the invention. Fig. i shows a circuit .in which the invention may be ap¬plied in connection with unpacking and desynchronization of data signals in an SDH system. The circuit receives data signals, which may e.g. be so-celled TU-12 signals. In a denappir.g circuit 1. the tU-12 signals are unpacked to VC-12. signals, with concurrent separation of overhead signals from the data signals proper. Further, in the circuit 1, a clock signal is generated from the incoming data, a clock pulse being generated in principle for each data byze in the unpacked VC-12 signals. If pointer ad¬justments have been made on the transmitter side, this will appear from the overhead signals, and, depending on this, the circuit . 1 may therefore add oc -remove clock puises in the generated clock .signal, which tnerefore be¬comes irregular as the clock frequency will vary in. step with the addition or remcval of • clock pulses. This fre¬quency variation is called jitter. As will be described below, the circuit 1 rr.ay also be adaptec. to generate a multiframe reference signal of 2 kHz. . The unpacked VC-12 signals are input via «. data bus in a buffer 2 by means of the clock signal generated in the circuit 1 and possibly vitiated by jitter:, so that the input will take place at an uneven rates depending on pointer adjustments, if any. The data buffer 2 may be constructed as a ring buffer and may e.g. be of 12 bytes. To smooth the uneven rate, the jitter clock signal is passed through a phase-locked loop/ which, as shown in fig. 1, may consist of a phase detector 3, a filter 4 and a numerically controlled oscillator 5. As .a result/ a new clock slgna.1 appears on the output of the numerically controlled oscillator 5, having an approximately constant frequency which corresponds to the near, frequency of the jitter clock signal, and it is in connection with the generation of this smoothed clock signal that the inven¬tion may be applied. Smoothirg of the uneven rate of the data signals then takeAs p!.ace ir. that the data input in the buffer 2 are output fror. the buffer again by means of the smoothed clock signal. In the case of VC-12 signals, the smoothed clock signal will typically have a frequency of 264 kHz; but since the signals are usually to be processed bitwise subsequently, the output signal from. the numerically con¬trolled oscillator 5 will have a frequency eight times as high, viz. 2.112 MHz, which will then merely be divided by • factor of 8 before being used for output of data ' from the buffer 2. Then, as derationed/ the data signals may be further processed in subsequent circuits; but this is of. no importance to the invention and will therefore nor he described more fuliy. The phase detector 3 neasures the phase difference be¬tween the jitcer clock signal and the smoothed clock sig-na]', following which a control word, which controls the numerically controlled oscillator 5, is generated via the filter 4. The oscillator 5 may be implemented as a pro-grammable divider which, in response to the control word, is capable of dividing a system clock signal, which has a higher frequency, by a factor determined by the control word. The control word may e.g. assume the three values (-1, 0, +1. If a system clock signal o1: 19.44 MHz is used, the oscillator may be adapted to div:.de by a factor of 9.2C1545 corresponding to the desired frequency of 2.112 MHz whan the control word is 0. When the control word is -1, because the phase detector 3 has detected that the smoothed clock frequency is greater than the mean frequency of the jitter clock signal, the oscillator may divide by t factor of 9.204611 corresponding to a frequency of 2.111985 MHz. When the control word is. +1, the oscillator may correspondingly divide by a factor of 9.204482 corresponding to a frequency of 2.112015 MHz. Alternatively, the control word nay assumo the values {-2, -l, 0, + l, +1+2), said values -2 and +2 giving frequen¬cies which differ more frca the nominal frequency, ana being used when the phase detector detects greater devia¬tions from the near, frequency of the jitter clock signal. This may occur e.g. if frequent and great pointer adjust¬ments are tnaris because of errors in the system. As mentioned above, the buffer 2 may e.g. consist of 12 storage locations or bytes, each of the size of 8 bits and indexed by an address. The difference betwaan the ad¬dress to which input is performed and the address from which output is performed, indicates the filling degree of the buffer. This value of the filling degree is an in¬dication of the phase difference batweer. the two clock signals, and instead of comparing these ir. the phase de-tector 3, it will therefore suffice to feed a signal which indicates the filling degree of the buffer 2 frost the buffer to the filter 4. It may thus be said that the phase detector of the phase-locked loop is: formed by the buffer 2. This is shown .in fig. 2, which corresponds to fig. 1 in other respects. As mentioned before, it it may be desirable to be able to adjust the frequency of the numerically controlled oscil¬lator 5 in considerably smaller jumps than is possible with the above-mentioned frequencies. This is possible if the filter 4 is forzr.ad as shown in fig. 3. The value indicating the filling degree cf the buffer 2 is fed to a detector circuit 6. As the buffer contains 12 bytes, the filling degree ir.ay assume the values 0-12. The value 12 indicates that the buffer is completely filled, while the value C correspondingly indicates that the buffer is empty. It is intended that.the filling degree Is in the middle of the range, and the values 5-7 are therefore regarded as being the noraial ones. At these values, the detector circuit 6 will enit the control word 0 to indicate that the oscillator 5 may continue with a frequency of 2.112 MHz. The filling degree of the buffer will typically be changed when pointer adjustments occur, and the valua will be changed by 1 for each adjustment of one byta. If the buffer is closa to being filled, corraspending to the values 10-12, or close to being empty, corresponding to the values 6-2, fast adjustment must be performed/ and the detector circuit 6 will emit the control words -2 or +2 indicating that the numerically controlled oscillator 5 is to have either a smallest or a greatest frequency in order to bring the filling degree of the buffer back to a level about a mean filling degree as quickly as possible. In this case, a great frequency jump must be accepted/ since, otherwise, data will be lost owing to overflow in the buffer. So strong pointer adjustments, however, will just occur very rarely. Normally occurring pointer adjustments, however, will maximally cause the filling degree to assume the values i, 4 or 3, 9, and thare is thus no immediate risk of overflow in the buffer 2, for which reason very fast ad¬justment of the filling degree is not needed. The control word emitted by the detector circuit 6 will be -1 or +1 in this case; but instead cf feeding it di::ectly forwards to the oscillator 5, as described before, :.t is passed to a modulator' 7 in which it nay be modulated with a square wave signal from a pulse generator 9. The pulse generator 8 is controlled from a processor 9. The scfuare wave sig¬nal has a fixed cycle time of e.g. 256 msec, whereas the pulse width is variable in steps cf e.g. 1 msec. The square wave signal from the pulse generator 8 is applied to the modulation input cf the modulator and thus deter¬mines the control word emitted. When the square wave jig»-nal is high, the control word -1 or +1 is emitted, while the control word 0 is emitted instead in the pauses be¬tween the pulses. This means that the control word -1 or +1 win just be emitted for a fraction of the time, and the oscillator 5 will therefore use the higher or lower frequency also just for a fraction of the time, while it will continue to use the nominal frequency for the rest of the time. This means in practice that the oscillator will emit a frequency which differs considerably less from the nozai- . r.al frequency than the previously mentioned difference between two adjacent frequencies. For exarpie, the fre¬quency at the control word +1 may be selected hare in jumps of 1/256 of the difference between 2.111985 MHz and 7.112000 MHz. When the resulting frequency differs less from the ncT.ir.al one than before, the siroothing of a, pointer adjustment will take a longer tine than before, of coarse; but since pointer adjustnents .rormally do not occur very frequently, this will actually be quits expe¬dient. If, nevertheless, several adjustnerts should take place immediately after one another, the detector circuit 6 will emit the control word -2 or -2, as described be¬fore, and thereby provide for fast ad j us tment , thereby obviating overflow of the buffer. The pulse width of the square wave signal emitted fay the pulse generator 8 is controlled fron a processor 9, as mentioned. The processor nay merely be adapted to select a specific pulse width for each fillirg. degree. For example, the pulse width cay be selected a: 1 msec at the filling degree 4 or 8 to ensure that the compensatior. is extended over the greatest possible length of time, while a somewhat greater pulse width raay be selectee at the filling degree 3 or 9, thereby providing a somewhat faster adjustment toward the middle value:s. However, the processor 9 may also receive the overhead signals which are unpacked in the deaapping circuit 1, and thereby se¬lect an expedient pulse width in each individual situa¬tion on the basis of these signals as well as the filling Fig. 4 shows an example of how the detector circuit 6 may be constructed. It consists of a peak value detector 10 and a sample-and-hold circuit 11. The peak value detector 10 receives the signal which indicates the filling 'degree of the buffer 2, and it moreover receiver a nultiframe reference signal from the deir.apping circuit. I. The detec¬tor 10 detects the highest value of the filling degree over a period of the nultifrane reference, signal/ and this value is sa.rr.pied by the multifrane reference signal in the sample-and-hold circuit .11. The peek value detec¬tor 10 is reset while -the sample-and-hcId circuit 11 reads the peak value. The control v/crd emitted by the circuit 6 is thus determined by the highest filling de¬gree in each period for the multifrar.e reference signal. This provides for a more stable adjustnent Although a preferred enbodiineht of whe present invention has been described and shown, the invent:.en is not re¬stricted to it, but nay also be embodied in other ways. within the scope of the subject-natter def:.ned in the ap¬pended claims. WE CLAIM: 1. A digital phase-locked loop comprising a numerically controlled oscillator (5) which is adapted to generate a clock signal by dividing a system clock frequency by a factor determined by a control word, and a phase detector (2;3) which is adapted to generate said control word in response to a phase difference between said clock signal and an external reference signal, so that the control word assumes a nominal value when said phase difference is numerically smaller than a value given in advance, and may assume one or more other values when the phase difference is numerically greater than the given value, characterized in that the loop moreover comprises means (7) which, when the phase difference is numerically greater than the given value, are capable of modulating the control word, so that said word assumes one of the one or more other values in subperiods, while it assumes the nominal value in intermediate periods. 2. A digital phase-locked loop as claimed in claim 1, wherein the nominal value (0), the control word may assume at least one other value (+1) when the phase difference indicates that the clock signal frequency is lower than the reference signal frequency, and at least one other value (-1) when the clock signal frequency is higher than the reference signal frequency. 3. A digital phase-locked loop as claimed in claim 2, wherein the control word may assume two values (+1, +2) when the phase difference indicates that the clock signal frequency is lower than the reference signal frequency, and two values (-1, -2) when the clock signal frequency is higher than the reference signal frequency, and that said modulation means (7) are adapted to modulate the control word only when it assumes the values (+1, -1) which correspond to the numerically smallest phase difference. 4. A digital phase-locked loop as claimed in claims 1-3, wherein said modulation means (7) are adapted to modulate the control word with a pulse signal which has a fixed cycle time and a variable pulse width. 5. A digital phase-locked loop as claimed in claim 4, wherein it moreover comprises means (9) for controlling the pulse width in response to said phase difference. 6. A method of controlling a digital phase-locked loop, wherein a clock signal is generated by dividing a system clock frequency by a factor determined by a control word, and wherein said control word is generated in response to phase difference between said clock signal and an external reference signal, so that the control word assumes a nominal value when said phase difference is numerically smaller than a value given in advance, and may assume one or more other values when the phase difference is numerically greater than the given value, wherein the phase difference is numerically greater than the given value, the control word is modulated so that it assumes one of the one or more other values in subperiods, while it assumes the nominal value in intermediate periods. 7. The method as claimed in claim 6, wherein desynchronization takes place in a receiver in a digital transmission system, wherein justification is performed by adding or removing, as needed, one or more bits in the transmitted bit flow on the transmission side when placing e.g. telephone calls in the transmission system, and wherein the effect of the added or removed bits is smoothed in the receiver in the desynchronization. and wherein a clock signal is generated in a digital phase-locked loop as claimed in claim 1, in the receiver by dividing a system clock frequency by a factor determined by a control word, which is generated in response to a phase difference between said clock signal and an external reference signal, so that the control word assumes a nominal value when said phase difference is numerically smaller than a value given in advance, and may assume one or more other values when the phase difference is numerically greater than the given value, wherein when the phase difference is numerically greater than the given value, the control word is modulated so that it assumes one of the one or more other values in subperiods, while it assumes the nominal value in intermediate periods. 8. A system for use in digital transmission system comprising a digital phase-locked loop as claimed in claim 1 and adapted to receive and desynchronize data signals in the form of a bit flow, wherein justification is performed by adding or removing, as needed, one or more bits in the transmitted bit flow on the transmission side when placing e.g. telephone calls in the transmission system, and wherein the receiver circuit is moreover adapted to smooth the effect of the added and removed bits in the desynchronization, wherein the system has a numerically controlled oscillator (5) which is adapted to generate a clock signal by dividing a system clock frequency by a factor determined by a control word, and a phase detector (2;3) which is adapted to generate said control word in response to phase difference between said clock signal and a reference clock signal derived from the data signals received, so that the control word assumes a nominal value when said phase difference is numerically smaller than a value given in advance, and may assume one or more other values when the phase difference is numerically greater than the given value, wherein the digital phase-locked loop moreover comprises means (7) which, when the phase difference is numerically greater than the given value, may modulate the control word so that it assumes one of the one or more other values in subperiods, while it assumes the nominal value in intermediate periods. 9. A system as claimed in claim 8, wherein it comprises a buffer circuit (2) adapted such that the received data signals may be input in the buffer circuit by means of the reference clock signal and be output again by means of said clock signal, and that the phase detector of the digital phase-locked loop is formed by the buffer circuit (2), the number of data signals input in but not yet output from the buffer circuit (2) being used as an indication of the phase difference between said clock signal and the reference clock signal. 10. A system as claimed in claim 9, wherein the buffer circuit (2) is constructed as a ring buffer and is capable of storing 12 bytes. 11. A system as claimed in claim 9 or 10, wherein in addition to the nominal value (0), the control word may assume at least one other value (+1) when the phase difference indicates that the clock signal frequency is lower than the reference clock signal frequency, and at least one other value (-1) when the clock signal frequency is higher than the reference clock signal frequency. 12. A system as claimed in claim 11, wherein the control word may assume two values (+1, +2) when the phase difference indicates that the clock signal frequency is lower than the reference clock signal frequency, and two values (- 1, -2) when the clock signal frequency is higher than the reference clock signal frequency, and that said modulation means (7) are adapted to modulate the control word only when it assumes the values (+1, -1) which correspond to the numerically smallest phase difference. 13. A system as claimed in claims 8-12, wherein said modulation means (7) are adapted to modulate the control word with a pulse signal which has a fixed cycle time and a variable pulse width. 14. A system as claimed in claim 13, wherein moreover comprises means (9) to control the pulse width in response to said phase difference. 15. A system as claimed in claim 9, wherein it comprises means (10, 11) to generate the control word in response to a highest value of the number of data signals which are input but not yet output from the buffer circuit (2), measured over a period of time. 16. A system as claimed in claims 8-15, wherein the numerically controlled oscillator (5) is adapted to generate a clock signal whose nominal frequency is 2.112 MHz. 17. A digital phase-locked loop substantially as herein described with reference to the accompanying drawings.

Documents:

3731-del-1997-abstract.pdf

3731-del-1997-claims.pdf

3731-del-1997-correspondence-others.pdf

3731-del-1997-correspondence-po.pdf

3731-del-1997-description (complete).pdf

3731-del-1997-drawings.pdf

3731-del-1997-form-1.pdf

3731-del-1997-form-13.pdf

3731-del-1997-form-19.pdf

3731-del-1997-form-2.pdf

3731-del-1997-form-3.pdf

3731-del-1997-form-4.pdf

3731-del-1997-form-6.pdf

3731-del-1997-gpa.pdf

3731-del-1997-pct-210.pdf

3731-del-1997-pct-408.pdf

3731-del-1997-pct-409.pdf

3731-del-1997-pct-416.pdf

3731-del-1997-petition-138.pdf