Title of Invention

A METHOD FOR FABRICATING A NON-VOLATILE MEMORY CELL WITH A SEPARATE TUNNEL WINDOW.

Abstract

This invention relates to a method for fabricating a nonvolatile semiconductor memory cell with a separate tunnel window comprising the steps of forming a tunnel window cell (TF) with a tunnel zone (TS) , a tunnel layer (4), a tunnel window memory layer (T5) , a dielectric tunnel window layer (T6) and a tunnel window control electrode layer (T7); and forming a transistor memory cell (TZ) with a channel zone (KG), a gate layer (3), a memory layer (5 ) , a dielectric layer (6) and a control electrode layer (7); forming the transistor memory cell (TZ) and the tunnel window cell (TF) isolated from one another in active regions of a semiconductor substrate (100); forming a connecting region (VB) for conducting the tunnel window cell (TF) with the transistor memory cell (TZ) in an inactive region of the semiconductor substrate (100). Doping the tunnel 2one (TS) in an active region of the tunnel window cell (TF) subsequent to the forming of the tunnel layer (4).

Full Text

The present invention relates to a method for fabricating a non—volatile memory cell with a separate tunnel window and particularly a method for fabricating an EEPROM cell with a small space requirement and a high number of program/clear cycles. Rewritable non-volatile semiconductor memory cells are gaining increasing significance in high-density circuits because of their ability to store modifiable date in chip over a long time period without a voltage supply. It is possible to distinguish between EEPROMs, EPROMs an FLASH-EPROM memories, depending on the non-volatile semi conductor memory cells that are used. Figure 5 is a sectional view of a conventional EEPROM memory call SZ, which consists substantially of a tunnel window cell TF and a transistor memory cell T2- According to Figure 5, the transistor memory cell TZ consists of a relatively thick gate layer 3, which is relatively insensitive to leakage currents, an overlaying floating gate layer 5, a dielectric layer 6, and a control electrode layer 7. A charge which is embedded in the floating gate layer 5 determines the switching behavior of the corresponding field effect transistor, which is driven by way of source/drain 2 zones 1 and the control electrode layer 7. Far embedding the charges in the floating gate layer 5, the memory cell includes the tunnel window cell TF, which has substantially the same layer sequence as the transistor memory cell TZ, though there is an insulating layer consisting of a very thin tunnel layer 4 between a semiconductor substrate 100 and the floating gate layer 5. In the fabrication of this conventional EEPR0M memory cell S2, first an ion implantation is carried out in the region of the tunnel window cell TF for purposes of forming a homogenous tunnel zone 2'- Next, the insulating tunnel layer 4, i.e. gate layer 3, and the floating gate layer 5, dielectric layer 6, and control electrode layer 7 are applied. Lastly, in one (or more) additional ion implantations the source/drain zones 1 are formed in the semiconductor substrate 100 in self-aligning fashion with the aid of the memory cell SZ as the mask. This way, an extremely high-grade rewritable nan-volatile semiconductor memory cell is obtained, which has a very good endurance. The endurance refers to the number of program/clear cycles and is apprax. 106 cycles in conventional EEPROMs of this kind. 3 The disadvantage of these conventional EPROMs is the large area required for the memory cell SZ, for which reason they can be utilized in high—density circuits only under certain conditions. In contrast, FLASH-EPROM memory cells ahve an extraordinarily smal1 area requirement. Figure 6 represents a section of a conventional FLASH-EPROM memory cell, wherein a tunnel oxide layer 4, a floating gate layer 5, a dielectric layer 6 and a control electrode layer 7 are stacked on a semiconductor substrate 100. In order to form a tunnel zone in a tunnel window region TF' of the FLASH-EPROM memory cell, implantation zones 2 are formed in the semiconductor substrate 100 in self-aligning fashion with the aid of the stacked memory cell. Next, source/drain zones 1 are incorporated in the semiconductor substrate 100 in self-aligning fashion with the aid of the memory cell and additional auxi1iary layers or spacers 8. In this conventional FLASH-EPROM memory cell, as in the above described EEPR0M memory cell, a charge is implanted in the floating gate layer 5 by the injection of hot charge carriers and/or Fowler-Nordheim tunnels in the tunnel window region TF via the tunnel layer 4. The implanted charge carriers will subsequently determine the switching behavior of a transistor cell region TZ'. 4 Despite the significantly smaller area required by this conventional FLASH-EPROM memory cel1, this type of nonvolatile memory cell has a substantial disadvantage in that its endurance (i.e. the number of program/ clear cycles) is significantly poorer than that of the conventional EEPROM memory cell represented in Figure 5- Usually the enduranc of these FLASH-EPROM memory cells is approx. 103 cycles. A significant disadvantage of these rewritable conventional non-volatile memory cells is that they can be combined into a common integrated circuit only under certain conditions. This is particularly attributable to the fact that the implantation of the tunnel zone 2', which is carried out beforehand according to Figure 5, influences the thickness of the subsequent tunnel layer 4. In other words, given the utilization of the same fabrication process, a tunnel layer 4 for a tunnel window cell TF as represented in Figure 5 will have a different thickness than in the FLASHEPROM memory cell represented in Figure 6. Furthermore, the implantation zone 2' represented in Figure 5 is very sensitive to thermal post-processing, whereas the implantation zone 2 represented in Figure 6 is formed relatively late in the fabrication process. For these reasons, different program/clear voltages arise for the memory cells according to Figure 4 and Figure 5, which are formed in the same integrated circuit. 5 US 5,565,371 also describes a method for fabricating a nonvolatile semiconductor memory cell with a separate tunnel window, wherein the transistor memory cell is programmed by the injection of hot charge carriers, and the transistor memory cell is cleared via Fowler—Nordheim tunnels. The disadvantage of this is the extraorginarily large area requirement and the introduction of a number of nonstandard fabrication processes. It is therefore, impossible to combine this method with conventional methods. It is thus the object of the invention to design a method for fabricating a non—volatile semiconductor memory cell with a separate tunnel window, which reduces the area requirement of the memory cell while improving the endurance, given the utilization of standard fabrication processes. This object is inventively achieved by the measures of patent claim 1. Specifically by forming tunnel zones in the active region of the tunnel window cells subsequent to the formation of the tunnel layer, it is passible to create a non—volatile semiconductor memory cell which is equal to a conventional EEPROM cell with respect to its endurance, i.e. 6 program/clear cycles, but significantly improved with respect to its space requirements- Beyond this, a memory cell so fabricated can easily be realized in a common integrated circuit with conventional FLASH-EPROM cells using standard processes - The useful voltages (program/clear/read voltages) can be the same for a wide variety of forms of non-volatile semiconductor memory cells. The tunnel zones are formed by implantation in self-aligning fashion with the aid of at least one layer of the tunnel window cell. In particular, for high-denisity circuits with structural sizes 7 Expediently, a floating gate connecting region and a control electrode connecting reion are formed simultaneously with the appertaining floating gate layers and control electrode layers of the tunnel window cell and the transistor memory cell, thereby guaranteeing a further simplification of the fabrication process. Advantageous developments of the invention are characterized in the sub claims. Exemplifying embodiments of the invention will now be described with reference to the accompanying drawings: Figure 1: a sectional veiw of a non-volatile semiconductor memory cell with a separate tunnel window according to a first exemplifying embodiment; Figure 2: an enlarged sectional view of a tunnel window cell represented in Figure 1, in a first exemplifying embodiment; Figure 3: an enlarged sectional view of a tunnel window cell according to a second exemplifying embodiment. Figure 4: an enlarged sectional view of a tunnel window cell according to a third exemplifying embodiment; 8 Figure 5: a sectional view of an EEPROM memory cell according to the prior art; and Figure 6: a sectional view of a FLASH-EPR0M memory cell according to the prior art. Figure 1 represents a schematic sectional view of a nonvolatile semiconductor memory cell with a separate tunnel window according to a first exemplifying embodiment. Identical reference characters reference the same or similar layers or components as in Figures 5 and 6, and therefore detailed descriptions will be omitted. According to figure 1, a transistor memory cell TZ, a tunnel window cell TF and a connecting region VB are formed on a semiconductor substrate 100. The transistor memory cell TZ, the connecting region VB, and the tunnel window cell TF represent an actual memory cell SZ. The semiconductor substrate 100 expediently consists of Si , though it may also be a III—V compound semiconductor or some other semiconductor substrate. The memory cell SZ can be realized as a PMOS cell, an NMOS or a CMOS cell in the semiconductor substrate 100, whereby corresponding p troughs and/or n troughs are provided. 9 According to Figure 1 the transistor memory cell T2 consists of an insulating gate layer 3 such as thermally formed Si02. Over the gate layer 3 is a conductive floating gate layer 5 (poly-Si) for storing charges. In correspondence with the charges stored in the floating gate, a channel zone KG located beneath the gate layer 3 becomes conductive or nonconductive, whereby the logic information 0 or 1 can be respectively read during the reading of the memory cell SZ. A control electrode layer 7 which is insulated by a dielectric layer 6 from the floating gate 1;ayer 5 is provided for driving the transistor memory cell TZ or memory cell SZ. This way, the charge held in the floating gate layer 5 cannot drain off into the semiconductor substrate 100 or the control electrode layer 7. Situated at a remove from the transistor memory cell TZ in Figure 1 is a tunnel window cell TF, which communicates with the transistor memory cell TZ via a connecting region VB and which serves for writing/erasing by means of hot charge carrier injection and/or Fowler-Nordheim tunnels. 10 The tunnel window cell TF advantageously consists of the same layers as the transistor memory cell TZ, whereby only a tunnel layer 4 has a sufficiently small thickness for the tunneling. The tunnel layer 4 advantageously consists of a tunnel oxide layer such as SiO2 . An overlying tunnel window floating gate layer T5 expediently consists of the same material as the floating gate layer 5 of the transistor memory cell TZ and is insulated from the electrically conductive tunnel window control electrode layer T7 by a dielectric tunnel window layer T6. Like the dielectric layer 6, the dielectric tunnel window layer T6 consists of an 0N0 (oxide/nitride/oxide) layer sequence, though it can also consist of some other insulating dielectric layer. Like the control electrode layer 7 and the floating gate layer 5, the conductive tunnel window control electrode layer T7 and the conductive tunnel window floating gate layer T5 consist of poly-Si but may also consist of some other conductive and/or charge-storing material. 11 The connecting region VB usually consists of the same layer sequence as the transistor memory cell TZ or the tunnel window cell TF, whereby the control electrode layer 7 communicates with the tunnel window control electrode layer T7 via a control electrode connecting region VB7, and the floating gate layer 5 communicates with the tunnel window floating gate layer T5 via a floating gate connecting region VB5. But the control electrode connecting region 7 and the floating gate connection region 5 can also be realized by means of metallic conductive tracks and/or diffusion regions in the semiconductor substrate 100. What is essential to the invention is the mutually isolated formation of the transistor memory cell TZ and the tunnel window cell TF, which can be realized by a suitable etching and/or photolithography technique. The tunnel window cell TF can have a projection, a nose, or some other geometric structure given which a double-sided implantation can be accomplished by a tunnel implantation IT . 12 Accordingly, in Figure 1 a tunnel zone T6 is formed by a, tunnel implantation IT which is performed relatively late in the fabrication process and which corresponds to a tunnel implantation in simultaneously fabricated FLASH-EPROM memory cells. In this fashion, both the tunnel window cells TF of the memory cell SZ and the tunnel window areas of FLASH-EPROM memory cells which are produced in the same process (which are not included in the figure) can be formed. Because the tunnel layer 4 of the inventive memory cell SZ is preferably formed in the same fabrication step as a FLASH-EPROM memory cell (which is not included in the figure), the two memory cells have the same electrical program/clear characteristics, thereby reducing the area requirement and improving the enudranee. The method for producing the non—volatile semi-conductor memory cell will now be described in detail. First, active areas in the semiconductor substrate 100 are formed for the tunnel window cell TF and the transistor memory cell TZ by means of an STI (Shallow Trench Isolation) process. The emerging trenches are fi1led with a deposited SiO2 layer and then planarized. Similarly, a LOCOS process can be used for insulating the active regions. 13 Next, the gate layer 3 and the tunnel layer 4 are formed and correspondingly structured at the active regions of the transistor memory cell TZ and the tunnel window cell TF. Next, the floating gate layer 5, the dielectric layer 6, and the control electrode layer 7 are applied and structured, producing the sectional view represented in Figure 1. According to Figure 1, the STI layers are located in regions of the memory cell SZ which lie parallel to the sectional view that is represented in the figure, which regions are not represented. Similarly, the control electrode connecting region VB7 and the floating gate connection region VB5 reference the corresponding layers in a layer plane which is situated behind this sections (in spatial terms). In order to form the tunnelwindow cell TF and the transistor memory cell TZ, an etching of the layers 3,5,6 and 7, or respectively 4, T5, T6 and T7, is subsequently performed, producing the stack-shaped cells TF and TZ which are represented in Figure 1. In the subsequent tunnel implantation IT, an implantation zone 2 is formed in self—aligning fashion next to the stack-shaped tunnel window cell TF, whereby the tunnel zone TG is created under the tunnel layer 4 by scattering effects in a 14 subsequent source/drain implantation (which is not illustrated), source/drain zones 1 are then formed in self—aligning fashion between the tunnel window cell TF and on both sides of the transistor memory cell TZ [sic, p.9, 1.34] . In this process, the tunnel window cell can utilize an auxiliary layer or spacer, which is not illustrated. The source/drain zone 1 between the transistor memory cell TZ and the tunnel window cell TF thus creates contact both to the tunnel window cell TF and to the transistor memory cell TZ and serves both for reading and programming/erasing the memory cell SZ. Figure 2 represents an enlarged sectional view of the tunnel window cell TF represented in Figure 1 during a tunnel implantation step. According to Figure 2 a stack-shaped arrangement of the tunnel layer 4, the tunnel window floating gate layer T5, the dielectric tunnel window layer T6 and the tunnel window control electrode layer T7 is located ' on a-semiconductor substrate 100. After the structuring of this stack-shaped tunnel window cell TF, the actual tunnel implantation I is performed for purposes of forming the tunnel zone T6 under the 15 tunnel layer 4. In this process, an implantation zone 2 is formed on both sides in self-aligning fahsion with the aid of the stack-shaped tunnel window cell TF, in such a way that its ends touch beneath the tunnel layer 4, forming a homogenous tunnel zone TG. This technique for forming implantation zones 2 is possible particularly given Very small structural sizes under one µm, whereby scattering effects in the implantation are exploited to form the overlapping tunnel zones TG. For the implantation of n-zones, as is particularly wel1 suited, because it has a small depth of penetration and a relatively high diffusion. But Ph and/or Sb can also be utilized for doping. Similarly, p-dopants can be utilized to form p—zones, provided they exhibit sufficient scattering beneath the tunnel layer 4 and thereby create a sufficiently homogenous tunnel rigion TG. Alternatively to the perpendicular tunnel implantation IT , according to figure 3 a diagonal tunnel implantation ITs can also be performed, with the implantation into the region beneath the tunnel layer 4 occurring at an angle of 5 to 8 degrees. The implantation zone 2 is farmed in the semiconductor substrate 100 16 all the way into the region beneath the tunnel window cell TF acting as the mask from one side- A homogenous tunnel zone TG can also be generated beneath the tunnel layer 4 this way. Alternatively to the implantation I represented in Figure 3 which is slanted on one side, the tunnel implantation into the region under the tunnel layer 4 can also slant in form a number of sides (two). According to Figure 4, the tunnel implantation IT can also occur in such a way that the respective implantation zones 2 which are formed in the semiconductor substrate 100 do not touch, but rather extend only partly into the region under the tunnel layer 4. But the implantation zones 2 extend far enough under the tunnel layer that the space charge zones RLZ of the implantation zones 2 tough when an operating voltage (e.g. program/clear voltage of e.g. -10 V/+6 v) is applied, producing what is known as a punch—through effect, whereby a homogenous tunnel zone is formed under the tunnel 4. In this case also a memory cell is achieved which is distinguished by an improve endurance, i.e. a higher number of program/clear cycles. 17 According to the invention, the tunnel implantation IT is preferably performed utilising the entire tunnel window cell TF as the mask- But it is also possible to utilize only one of the layers in the tunnel window cell as the mask layer, or to utilize an additional mask layer in the form of a photosensitive resist layer and/or a hard-surface mask layer. LDD (Lightly Doped Drain) implantation or MD (Matrix Drain) Implantation is expediently utilised for the tunnel implantation IT , these being present in standard processes anyway. It is also possible to utilize a different layer sequence than that described above (e.g. SONOX), provided that it is possible to form a rewritable non-volatile semiconductor memory cell this way. 18 WE CLAIMS 1. Method for fabricating a non—volatile semiconductor memory cell with a separate tunnel window, comprising the steps of: farming a tunnel window cell (TF) with a tunnelzone (TG), a tunnel layer (4), a tunnel window memory layer (T5), a die-electric tunnel window layer (T6) and a tunnel window control electrode layer (T7); and forming a transistor memory cell (TZ) with a channel zone (KG), a gate layer (3), a memory layer (5), a dielectric layer (6) and a control electrode layer (7); forming the transistor memory cell (TZ) and the tunnel window cell (TF) isolated from one another in active regions of a semiconductor substrate (100); farming a connecting region (VB) for connecting the tunnel window cell (TF) with the transistor memory cell (TZ) in an inactive region of the semiconductor substrate (100); characterized by: doping the tunnel zone (TS) in an active region of the tunnel window cell (TF) subsequent to the forming of the tunnel layer (4). 19 2. Method as claimed in claim 1, wherein the step of forming the tunnel zone (TG) comprises forming implantation zones (2) in a self-aligned manner by using at least one layer of the tunnel window cell (TF) as mask. 3. Method as claimed in claim 2, comprising farming the implementation zones (2) by performing at least one implantation selected from the group of a vertical implantation and a horizontal implantation into a region under the tunnel layer (4). 4. Method as claimed in claim 2 or 3, wherein the forming of the tunnel zone (T8) is performed in such a way that the implantation zones (2) extend completely into the region under the tunnel layer (4). 5. Method as claimed in claim 2 or 3, wherein the forming of the tunnel zones (TS) is performed in such a way that space charge zones (RLZ) of the implantation zones (2) extend completely into the region under the tunnel layer (4) when an operating voltage is applied. 20 6. Method as claimed in one of claims 1 to 5, comprising the step of forming a memory layer connecting region (VB8) simultaneously with the memory layer (5) and the tunnel window memory layer (t5). 7. Method as claimed in one of claims 1 to 6, comprising the step of forming control electrode connecting region (VB7) simultaneously with the control electrode layer (7) and the tunnel window control electrode layer (T7). 8. Method as claimed in one of claims 1 to 7, comprising forming the tunnel zone (TG) by using an LDD implantation. 9. Method as claimed as claimed in one of claims 1 to 9, comprising an EEPROM memory cell configuration from the nonvolatile semiconductor memory cell. This invention relates to a method for fabricating a nonvolatile semiconductor memory cell with a separate tunnel window comprising the steps of forming a tunnel window cell (TF) with a tunnel zone (TS) , a tunnel layer (4), a tunnel window memory layer (T5) , a dielectric tunnel window layer (T6) and a tunnel window control electrode layer (T7); and forming a transistor memory cell (TZ) with a channel zone (KG), a gate layer (3), a memory layer (5 ) , a dielectric layer (6) and a control electrode layer (7); forming the transistor memory cell (TZ) and the tunnel window cell (TF) isolated from one another in active regions of a semiconductor substrate (100); forming a connecting region (VB) for conducting the tunnel window cell (TF) with the transistor memory cell (TZ) in an inactive region of the semiconductor substrate (100). Doping the tunnel 2one (TS) in an active region of the tunnel window cell (TF) subsequent to the forming of the tunnel layer (4).

Documents:

in-pct-2001-01312-kol abstract.pdf

in-pct-2001-01312-kol claims.pdf

in-pct-2001-01312-kol correspondence.pdf

in-pct-2001-01312-kol description(complete).pdf

in-pct-2001-01312-kol drawings.pdf

in-pct-2001-01312-kol form-1.pdf

in-pct-2001-01312-kol form-18.pdf

in-pct-2001-01312-kol form-2.pdf

in-pct-2001-01312-kol form-3.pdf

in-pct-2001-01312-kol form-5.pdf

in-pct-2001-01312-kol g.p.a.pdf

in-pct-2001-01312-kol letters patent.pdf

in-pct-2001-01312-kol priority document others.pdf

in-pct-2001-01312-kol reply f.e.r.pdf

IN-PCT-2001-1312-KOL-CORRESPONDENCE 1.1.pdf

IN-PCT-2001-1312-KOL-FORM 27 1.1.pdf

IN-PCT-2001-1312-KOL-FORM 27.pdf

IN-PCT-2001-1312-KOL-FORM-27-1.pdf

IN-PCT-2001-1312-KOL-FORM-27.pdf

in-pct-2001-1312-kol-granted-abstract.pdf

in-pct-2001-1312-kol-granted-claims.pdf

in-pct-2001-1312-kol-granted-description (complete).pdf

in-pct-2001-1312-kol-granted-drawings.pdf

in-pct-2001-1312-kol-granted-form 2.pdf

in-pct-2001-1312-kol-granted-specification.pdf

in-pct-2001-1312-kol-priority document.pdf