Title of Invention


Abstract Disclosed herein is a switched mode of power supplies having Phase-Modulated full- bridge converter is characterized in that Phase-Modulated full-bridge converter has left- right MOSFETs formation such that PMC to achieve ZVS down to light loads with minimum penalty on conduction losses such that only the left-leg transitions being critical from the ZVS view-point and for right-leg MOSFETs ZVS being achieved down to loads as low as 20% or less without any external inductor further such that all the switches being operable at 50% duty-ratio and one end of the external inductor is held constant and the other end is switched between the pre-determined limits resulting in that resultant current is triangular which reaches the positive and negative peaks exactly during the leftleg transitions thus effectively aiding zero voltage switching of left-leg MOSFETs.
Full Text

This invention pertains to the field of Electrical Technology. In general this invention relates to power supplies for electric devices and appliances. In particular this invention relates to a novel configuration for switched mode power supplies (SMPS). This invention further relates to a novel configuration for switched mode power supplies.
The present trend in switched mode power supplies (SMPS) is to switch at very high frequencies to meet the ever increasing demands on higher power-density. Switching frequencies in the range of 300kHz for the high-power SMPS and above 1 MHz for the low-power SMPS may soon become the standard. In order to fully exploit the advantages of high frequency switching, its adverse effects -mainly the higher switching losses and device stress during the transitions have to be overcome. Various soft-switching topologies based on LC resonant circuits, like the load-resonant converters and resonant-switch converters, are being used presently. They have many drawbacks compared to the conventional PWM topologies, chief among them being variable frequency operation, higher conduction losses and higher ratio of installed VA to output VA.
The Phase-Modulated full-bridge Converter (PMC) which may be classified as a resonant transition topology is recently gaining ground since it offers Zero-Voltage Switching (ZVS) under constant frequency operation. Also, by proper design the conduction losses and the ratio of installed VA to output VA can be made considerably less than the resonant topologies. Thanks to intense research over the past few years PMC is now well understood, and with good support available in terms of control, IC's, design documents etc. PMC promises to be the topology of choice for off-line SMPS especially at higher power ratings.

In order to achieve zero voltage switching at light loads the following two methods are being used presently.
1. An external inductor is added in series with the primary of the transformer.
2. Either a bigger transformer with large air gap or hence more magnetising current or an external inductor in parallel with the transformer primary is used.
The series inductor decreases the rate at which the primary reflected load current changes its polarity during the left-leg transition, hence increasing the amp-sec available for a given load. However larger series inductance increases the overlap period. The maximum effective duty-ratio as seen by the output is thus reduced. Hence to achieve output regulation the turns-ratio of the transformer has to be compromised with the following serious disadvantages:
1. the primary reflected load current is more thus increasing the switch current and the conduction losses.
2. the required VA rating of the transformer goes up.
3. the voltage stress across the output diodes increases in proportion to the transformer turns-ratio. Also the switching losses of the diodes increase.
The above problems become particularly severe with increasing frequency, since the overlap period becomes a significant portion of the total on-time.
The current through the parallel inductor is independent of the load. Also it does not affect the overlap period and hence desirable. However, the use of the parallel inductor has the following disadvantages.

1. The current remains at its peak value throughout the freewheeling interval contributing significantly to the conduction losses. It also increases the required rms current rating of the external inductor.
2. The current through the inductor passes through the right-leg MOSFETs where it is not needed to achieve ZVS. This results in higher conduction losses and also increases turn-off losses in the right-leg MOSFETs.
From the literature it can be seen that the optimum performance in terms of overall switch losses for PMC with either a series or parallel external inductor is obtained if the design is done to achieve ZVS for loads only above 70% to 80%.
However the Phase-modulated full-bridge converter known in the art has two major drawbacks as listed below and they form the subject matter of this patent claim.
1. The ZVS characteristics are load-dependent. Achieving ZVS at light loads is at the cost of significantly higher conduction losses.
2. The leakage inductance of the power transformer is purposely made higher in the phase-modulated converter in order to aid in ZVS. This large leakage inductance resonates with the junction capacitance of the output rectifiers resulting in high voltage stress across the rectifiers. This is a particularly severe problem for low output power supplies where Schottky diodes are used since they have high junction capacitance.
The object of the invention is to address the problem associated with prior art devices. The structural modifications effected in the prior art devices are primarily to overcome inherent problem in the existing prior art devices.

It is the primary object of the invention to contrive a novel phase modulated full bridge converter which achieves would overcome the drawback associated with conventional PMC. Namely voltage stress and the losses in the snubber resistor.
It is another object of the invention to contrive a circuit, which offer soft switching for the output rectifier diodes.
It is another object of the invention to contrive a circuit, which reduces switching losses associated with conventional Phase Modulated full bridge converter.
Other objects will be apparent from the ensuing descriptions.
Now the invention will be described in detail with reference to drawings accompanying the specifications wherein:
Fig. 1 Shows the circuit diagram of simplified schematic of Phase-Modulated converter.
Fig. 2 Shows the circuit illustrating the mechanism of loss and voltage stress.
Fig. 3 Shows the circuit diagram of diode snubber circuit presently used in Phase-Modulated Converter.
Fig. 4 Shows a circuit diagram of the Phase-Modulated full-bridge converter configuration according to invention.

The simplified schematic of the PMC is shown in Fig. 1. The capacitance shown across the MOSFETs are the combination of junction capacitance and any external capacitance added to reduce turn-off losses. Each of the four MOSFETs, S1 through S4, are operated at 50% duty-ratio which is the necessary condition for zero voltage switching. Regulation of the output voltage is achieved by varying the phase difference between VA and VB. A small time delay TD is given after a switch is turned off and before the complementary switch in the same leg is switched on. By design the capacitance across the MOSFET to be switched on should be completely discharged within the time delay so that the MOSFET turns on with zero volts across it.
This discharge is accomplished by the primary current which is predominantly the reflected load current and hence the dependence of ZVS characteristics on the load.
Referring to Fig. 2 of the drawing, it is clear that one of the major drawbacks of the phase-modulated full-bridge converter namely the high voltage stress and switching losses in the output rectifiers. The voltage stress is due to the resonance between the large leakage inductance (or any external series inductor) with the junction capacitance of the output rectifier. The switching loss is because the conventional PMC configurations do not offer soft-switching for the output rectifiers and each time the diode turns off, energy equal to 0.5 Cj V2sec is lost.
Consider Vsec to be positive. D1 conducts and CD2 is charged to 2*Vsec. When Vsec goes to OV, CD2 resonates with Lksec and reaches OV. It cannot go negative due to D2. Since the discharge is through LC resonance, it is lossless. When Vsec goes negative in the next half-cycle the current through D1 decreases and reaches zero eventually. At this point CD1 resonates with Lksec. Due to the high Q of the circuit the voltage across C D1 reaches close to twice the steady state value, i.e., 4*Vsec. When the resonance eventually dies down

due to the parasitic resistance CD1 settles at 2*Vsec, but in the process energy equal to CD1*Vsec is lost.
Since the values of both the leakage inductance and the junction capacitance are large, the frequency of ringing is not much higher than the converter switching frequency. Hence conventional RC snubber circuits placed across each diode result in high losses, hence are not practical. The snubber circuit usually employed in PMC is shown in Fig. 3. Here part of the energy stored in the leakage inductance is fed to the load through Rs. The main disadvantages of the circuit are:
1. the selection of the snubber components Cs and Rs is a compromise between the diode voltage stress and the losses in the snubber resistor. In practice, though the voltage stress and the switching losses are less than those with conventional snubber circuits, they are significantly higher than the minimum attainable.
2. the performance of the circuit is dependent on the operating point i.e.. input voltage and load. Therefore the design has to be done for the worst case condition.
The other alternative to these snubber circuits is to use diodes with high voltage rating. This results in higher conduction loss as the forward drop of these diodes are more.
In the proposed configuration shown in Fig. 4, the energy trapped in the parasitic elements, instead of being wasted in snubber circuits, is fed back to the input source itself. The snubber winding, marked as Ws, has the same number of turns as primary and is wound tightly coupled to the secondary. The leakage inductance between the snubber winding and the secondary is made negligible by twisting the two windings together Triple insulated wires may be used in applications where isolation requirements are stringent.

Just as explained previously, when Vsec goes negative D1 switches off and CD1 resonates with Lksec. However, now when CD1 reaches 2*Vsec, the snubber diodes connected to Vin begin to conduct thus clamping CD1 to 2*Vsec. The energy stored in the leakage inductance is fed to the input source.
The following are the salient features of the invention: -
1. The new configuration achieves soft-switching for the output rectifier diodes, hence reducing the switching losses.
2. The peak voltage stress across the diodes is 2*Vsec as opposed to nearly 4*Vsec in the conventional configuration. Hence rectifiers of lower voltage rating can be used resulting in significant reduction in the conduction losses.
3. A major source of EMI namely the ringing between leakage inductance and junction capacitance of the diodes is eliminated.
The invention as described in the complete specification is by way of example mainly to illustrate active concept/- principle envisaged in accordance with the invention.
It is understood that the said description will no way limit the scope of the invention. It is evident that within the concept envisaged, various modifications are permissible without departing from the active principle and scope of the invention.
The scope and ambit of the invention is apparent in the ensuing statement of claims.

A switched mode power supplies comprises a Phase-Modulated full-bridge converter characterised in that Snubber winding is tightly coupled to secondary and having same number of turns as primary, the primary and secondary being connected to load, the set snubber winding being placed proximate to secondary and having its one end connected to main power supply through a bridge rectifier such that leakage inductance between snubber winding and secondary being rendered negligible by twisting the two windings together and the energy stored in the leakage inductance being fed to input source.
Dated this 24th day of April 2000



498-mas-1998-claims filed.pdf

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498-mas-1998-form 1.pdf

498-mas-1998-form 26.pdf

498-mas-1998-form 5.pdf

498-mas-1999-other documents.pdf

Patent Number 211913
Indian Patent Application Number 498/MAS/1999
PG Journal Number 02/2008
Publication Date 11-Jan-2008
Grant Date 13-Nov-2007
Date of Filing 29-Apr-1999
Applicant Address BANGALORE - 560 012,
# Inventor's Name Inventor's Address
PCT International Classification Number H02 M 3/07
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA