|Title of Invention||
A METHOD AND APPARATUS FOR REDUCING THE LOCK TIME OF A PHASE LOCK LOOP (PLL)
|Abstract||The lock time is reduced in a phase locked loop frequency synthesizer that has both active modes and standby modes. In the active mode the frequency synthesizer operates to maintain a stable frequency output. The standby or sleep mode is used to reduce power consumption when the frequency synthesizer is not required to provide a frequency output. When the synthesizer is placed in standby mode the most recent value of the Voltage Controlled Oscillator (VCO) tuning voltage is maintained on the VCO tuning control line of the frequency synthesizer. The voltage is maintained on the VCO tuning output pin in Integrated Circuit (IC) frequency synthesizers. The voltage error on the VCO tuning pin is minimized thereby minimizing the lock time of the frequency synthesizer.|
METHOD AND APPARATUS FOR REDUCING PLL LOCK
BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates to Phase Locked Loops (PLL's). More particularly, the present invention relates to a novel and improved method and apparatus for reducing the time required to obtain phase lock in a PLL that is activated following operation in standby mode.
II. Description of the Related Art
Accurate frequency sources are vital to the operation of numerous electronic systems and devices. Frequency sources are used as timing sources within electronic devices and are also used to tune electronic devices to desired communication channels.
Many types of accurate frequency sources are available. The specific type of frequency source implemented within a particular application is determined according to the design constranits of the particular application. Atomic clocks exhibit extreme levels of frequency accuracy, however, their size, cost, and absence of timing range greatly limit their actual application within an electronic system. Similarly, accurate frequency sources can be designed utilizing the piezoelectric effect of quartz crystals- The small size and relative accuracy of quartz crystal based frequency sources make them popular for most consumer based electronic devices. However, a frequency source based upon the fundamental frequency of a quartz crytal is limited by the minimal frequency timing range and limitations on the fundamental frequency of a quartz crystal.
Indirect frequency synthesis is used to overcome the problems of the lack of frequency tuning and limited center frequency associated with fundamental quartz crystal frequency sources. Indirect frequency synthesis utilizes a Phase Locked Loop (PLL) to generate a frequency source that is a multiple of a reference frequency. Specific implementations of indirect frequency synthesis often use a quart;; crystal oscillator as the reference frequency.
The time the PLL takes to acquire and lock a VCO output signal is important in many applications. PLL lock time design constraints are determined by the specific application. Frequency synthesizers utilizing PLL's are used within portable communication devices to generate Local Oscillator (LO) signals. LO signals are used to tune receivers and transmitters to specific
channels- Typically in a receiver the LO is used to downconvert the received RF signal to a baseband signal. Conversely, in a transmitter a LO is used to upconvert baseband signals to designated RF channels. Frequency synthesizers used for the generation of LO signals are found in devices such as two-way radios, stereo receivers, televisions, and wireless phones. However, one of
SUMMARY OF THE INVENTION
The present invention is a novel and improved method and apparatus for decreasing the time required for a frequency synthesizer to lock aft r waking up from a sleep or standby mode. When the frequency synthesizer is placed in the sleep or standby mode the voltage on the VCO turning line is maintained, The portions of the frequency synthesizer required to maintain phase lock are powered down during sleep mode to conserve power. The powered down circuits include the reference divider, phase detector, and
output frequency divider. The voltage on the VCO tuning line is maintained at the voltage value that was on the VCO turning line just prior to the frequency synthesizer being placed in the sleep mode.
In a frequency synthesizer Integrated Circuit (IC) the voltage at the VCO time pin is maintained when the IC is placed in sleep mode. The IC samples the voltage value of the VCO control line just prior placing the IC in the sleep mode. The sampled value is maintained at the VCO tune pin of the frequency synthesizer IC.
BRIEF DESCRIPTION OF THE DRAWINGS
The features, objects, and advantages of the present invention -will become more apparent from the detailed description set forth. below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:
filters, amplifies, downconverts, and processes the received signal. The receiver 250 incorporates user interfaces that enable it to present the received information to the user. The user interface may include an earpiece speaker to provide audio output to the user as well as a display to provide textual or graphical output to the user.
The transmit path of a wireless phone 200 includes a baseband 250 circuit that provides the interface between the phone 200 and the user. The user interface may include a keypad, a touch sensitive screen, and a microphone. The baseband circuit 250 collects and processes the user input. The type of processing includes conditioning the input and modulating the input in the modulation format specified by the phone system, The input signal conditioning may consist of filtering as well as digitizing.
The processed baseband signal is then upconverted to an Intermediate Frequency (IF)- Upconversion of the baseband signal is performed using a first
mixer 252 in conjunction with a first Local Oscillator (LO) 254. The first LO 254 is typically a fixed LO such that the IF is constant within a predetermined narrow band, A fixed first LO 254 minimizes the complexity required in the IF processing section 260. The IP processing circuit 260 filters and simplifies the upconverted baseband signal. The IF section 260 may include an Automatic Gain Control (AGC) section to ensure that subsequent amplifiers are not compressed. The output of the IF section 260 is coupled to a second mixer 262 that uses the output of a frequency synthesi2:er 264 to upconvert the IF signal to an RF signal. The frequency Synthesizer 264 is capable of tuning in discrete steps over a frequency band to provide upconversion of the IF signal to a specified RF channel
The upconverted output of the second mixer 262 is coupled to an RF section 266 where the RF signal is filtered and amplified. The RF section 266 filters out the unwanted mixer products as will as filtering out spurious frequency components that degrade the quality of the RF signal. The output of the RF section 266 is coupled to an amplifier 270 that provides the final gain stage for the transmit signal The output of the amplifier 270 is coupled to an isolator 280, The isolator 280 is used to prevent signal reflections and energy coupled in the transmit frequency band from reaching the transmit circuits of the phone 200. The output of the isolator 280 is coupled to the duplexer 220 which couples the transmit RF signal to the antenna 210,
The use of a common antenna 210 for both the transmit and receive signals is accomplished by using the duplexer 220 to couple the signals to and from the antenna 210. In the receive path the duplexer 220 couples the signal
received at the antenna 210 to the receiver 230 while rejecting signals in the transmit frequency band. The signals in the transmit frequency band are rejected in. the duplexer 220 path to the receiver to eliminate the possibility of saturating the receiver 230 with transmit power.
the reference divider 332 is commanded to go into the sleep mode. The choice as to which configuration is most advantageous will depend on the specific frequency synthesizer 300 application.
Reference dividers 332 are typically used in most frequency synthesizers 300 to allow the use of a higher frequency reference oscillator 330 while maintaining a lower frequency at the input to the phase detector 340. A higher frequency reference oscillator 330 permits a more reasonably sized crystal oscillator. However, a lower frequency is desirable at the phase detector 340 input because the frequency of the phase detector 340 determines the tuning step size of the frequency synthesiser 300, The reference divider's 332 inclusion in the frequency synthesizer 300 is not mandatory and one of ordinary skill in the art will recognize that the frequency synthesizer 300 can be implemented without a reference divider 332.
The VCO 360 generates the output signal 364 of the frequency synthesizer 300. The VCO 360 output frequency is determined by the signal applied at the control input of the VCO 360. The VCO 360 output is also coupled to an output frequency divider 362, The output frequency divider 362 scales the frequency of the VCO 360 to the frequency of the phase detector 340. The output frequency divider 362 is advantageous when the frequency synthesizer 300 is required to tune over multiple channels. The frequency synthesizer 300 can also be tuned by varying the reference divider 332 or the reference oscillator 330, however, the most common method is the utilization of the output frequency divider 362.
The output frequency divider 362 is controlled by a sleep signal 302 which commands the output frequency divider 362 to power down when the phone is in the sleep mode. The value of the output divider ratio, analogous to the reference divider ratio, may be lost when the output frequency divider 362 is commanded to go into the sleep mode. However, like the reference divider ratio value, the output frequency divider ratio value can be saved in nonvolatile memory or can be saved in a memory location that is not powered down when the output frequency divider is commanded to go into the sleep mode.
The scaled frequency output 366 of the output frequency divider 362 is coupled to a second input on the phase detector 340. The phase detector 340 compares the two input signals and outputs a signal based on the phase error between the two input signals. The phase detector 340 is controlled by a sleep signal 302 which commands the phase detector 340 to power down when the phone is in the sleep mode.
The output of the phase detector 340 is coupled to the input of a voltage hold circuit 342 that is designed to maintain the VCO 360 control voltage signal when the frequency synthesizer is placed in the sleep mode. The actual implementation of the voltage hold circuit 342 depends on the type of phase detector 340 used in the loop- The voltage hold circuit 342 can be a sample and hold circuit where the output voltage of the phase detector is sampled continuously and held when the sleep signal 302 indicates the frequency synthesizer 300 is placed in the sleep mode. The sleep signal 302 commanding the voltage hold circuit 342 does not cause it to power down in the sleep mode. Instead, the sleep signal 302 commands the voltage hold circuit 342 to change from sampling the voltage on the control line, when the sleep signal 302 indicates an active mode, to maintaining the voltage on the control line when the sleep signal 302 indicates sleep mode.
The output of the voltage hold circuit 342 is coupled to the input of a loop filter 350. The loop filter acts to limit the bandwidth of the VCO 360 control signal. The loop filter 350 is commonly implemented as a passive filter and therefore requires no external, power source. However, the loop filter 350 can be implemented as an active filter. The output of the loop filter 350 is coupled to the control input of the VCO 360, As stated above, the output frequency of the VCO 360 is determined by the signal applied at the control input.
When the frequency synthesizer 300 is operating in the active mode all of the elements in the synthesizer are active and the voltage hold circuit 342 allows the output from the phase detector 340 to proceed unchanged to the loop filter 350. The loop operates to lock the VCO 360 output to the reference frequency when the frequency synthesizer 300 is in the active mode. When the frequency synthesizer is commanded to the sleep mode those elements that utilize the sleep signal 302 as a power control signal are powered down. The voltage hold circuit 342 utilizes the sleep signal 302 to maintain the voltage on the VCO 360 control line 352 at the value just prior to the application of the sleep signal 302.
When the frequency synthesizer 300 is commanded to return to the active mode from the sleep mode the VCO 360 initially operates at a frequency much closer to the frequency desired when the loop is locked. Therefore, the initial frequency error in the loop is smaller than if the VCO control voltage were not controlled during the sleep mode. The loop is able to reduce the time it takes to lock the VCO 360 to the reference frequency 330 because of the smaller initial frequency error. The reduction in lock time serves to reduce the
the switch 410 is in the open circuit position, the second amplifier 420 outputs the voltage stored in the capacitor 414- The voltage stored in the capacitor 414 represents the last voltage value output from the first amplifier 404 prior to open circuiting the switch 410. The output of the second amplifier 420 is constant in the hold mode since the first amplifier 404 no longer drives the voltage level across the capacitor 414.
The output of the second amplifier 420, which is the output of the voltage hold circuit 342, is coupled to the loop filter 350, The loop filter 350 serves to couple the VCO control voltage to the VCO 360. Therefore, it can be seen that the circuit of FIG, 4 can be used to allow continuous control over the VCO control voltage or can be used to maintain the VCO control voltage at a given level
The previous description of the preferred embodiments is provided to enable any person skilled in the art to make or use the present invention. The various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the inventive faculty. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein,
1. A method for reducing the lock time of a Phase Locked Loop (PLL) comprising:
sampling a Voltage Controlled Oscillator (VCO) control voltage of an active PLL; and
maintaining the VCO control voltage at the sampled VCO control voltage in response to a command signal.
2- The method of Claim 1 wherein the command signal is a sleep signal,
3. The method of Claim 1 further comprising placing the PLL in a
low power mode,
4. The method of Claim 3 wherein the task of placing the PLL in the low power mode occurs in response to the command signal.
5. A Phase Locked Loop (PLL) with reduced lock time comprising:
a phase detector that outputs a Voltage Controlled Oscillator (VCO) control signal;
a Voltage hold circuit coupled to the phase detector output; and
a VCO having a control input coupled to the voltage hold circuit;
wherein the voltage hold circuit samples the VCO control signal when the FLL is in an active state and the voltage hold circuit maintains the sampled VCO control signal when the PLL is in a low power state,
6. The PLL of Claim 5 further comprising:
a loop filter;
wherein the VCO is coupled to the voltage hold circuit via the loop filter,
7. The PLL of Claim 5 wherein the PLL switches from the active state to the low- power state in response to a command signal,
8. The PLL of Claim 7 wherein the command signal is a sleep signal.
9. The PLL of Claim 5 wherein the voltage hold circuit is a sample
and hold circuit
10. A frequency synthesizer Integrated Circuit (IC) comprising:
a control signal output; and
a voltage hold circuit;
wherein the voltage hold circuit samples the control signal output when the frequency synthesiser IC is in an active mode and maintains the control signal output when the frequency synthesizer IC is in a low power mode.
11. The frequency synthesizer IC of Claim 10 wherein the control signal output is a Voltage Controlled Oscillator (VCO) control signal output.
12. The frequency synthesizer IC of Claim 11 wherein the frequency synthesizer IC switches from the active mode to the low power mode in response to a command signal.
13. The frequency synthesizer IC of Claim 12 v/herein the command signal is a sleep signal.
14. A method for reducing the lock time substantially as herein described with reference
to the accompanying drawings.
15. A Phase Locked Loop (PLL) substantially as herein described with reference to the
|Indian Patent Application Number||IN/PCT/2002/1833/CHE|
|PG Journal Number||50/2007|
|Date of Filing||08-Nov-2002|
|Name of Patentee||M/S. QUALCOMM INCORPORATED|
|Applicant Address||5775 Morehouse Drive, San Diego, California 92121-1714|
|PCT International Classification Number||H03L 7/14|
|PCT International Application Number||PCT/US2001/014992|
|PCT International Filing date||2001-05-08|