Title of Invention

COMMUNICATION METHOD AND APPARATUS

Abstract In a frame sync method, a receiver searches for the presence of an N-symbol long unique word pattern. For each possible frame sync detected, the receiver proceeds to demodulation and FEC processing. After each iteration of the FEC decoder, the detected unique word pattern is compared to the expected one and the frame sync is detected if the number of unique word errors has decreased.
Full Text

Communication Method and Apparatus
The present invention relates to a method, apparatus, program and/or signal for data communication over a channel that is susceptible to interference. Particularly, but not exclusively, the present invention relates to a frame synchronisation technique usin forward error correction (FEC).
FEC techniques have been developed which allow a very low signal energy-to-noise ratio {EsINo)- One example is Turbo' coding as described in 'Near Shannon Limit error-correcting coding and decoding: Turbo codes' by C. Berrou, A. Glavieux and P. Thitimajshima, Proc. IEEE ICC, Geneva, May 1993. However, these FEC techniques require the start and end boundaries of the data transmission to be defined precisely by the receiver before the FEC decoding process starts. The detection of the transmission boundaries is known as frame synchronisation or frame sync.
Frame sync is one of the first operations in the demodulation process; usually, the demodulation process is followed by the FEC process, so that there is a time separation between the frame sync and the FEC process. Within this time separation, frame sync needs to be established successfully with the minimum E9/N0 required by the FEC process. Known frame sync techniques, as described for example in 'Optimum Frame Synchronization', by J. L. Massey, IEEE Trans, Commun.. vol. 20, no. 2, April 1972 and Trame Synchronization Techniques', by R. Scholtz, IEEE Trans. Commun., vol. 28, no. 8, August 1980, achieve frame sync at a low Es/No by means of lengthy Unique Words (UW), specially designed data patterns which are added to each packet transmission. The unique words occupy bandwidth which could otherwise be used to carry user or signalling data.
V The use of lengthy unique words is particularly costly of bandwidth in multiuser environments where channel conditions vary over time and per user, such that each burst transmission requires independent acquisition at the receiver. One such environment is a TDMA scheme where it is desirable to use small burst lengths to minimize latency and for efficient resource management; however, this leads to a high ratio of framing overhead to data within bursts.
It would be desirable to find a frame sync technique which improves the data transmission efficiency without sacrificing frame sync quality.

The paper Decoder-assisted Frame Synchronisation for Turbo Coded Systems', by H. Howlader, Y. Wu and B. Woemer, 2nd International Symposium on Turbo Codes, Brest, France, September 2000, discloses a decoder-assisted frame sync technique in which a synchronisation word is embedded in a packet of data before encoding. Th^ synchronisation word is preceded by a number of flush bits which are necessary to bring the Turbo decoding trellis to a known state. The synchronisation word then guides the decoding trellis through a sequence of known states, if the correct synchronisation has been detected.
According to one aspect of the present invention, there is provided a method of encoding data for transmission over a channel, in which the data contents of a frame or burst are combined with a unique word and the unique word is input to a systematic convolutional encoder before any of the data. The state of the convolutional encoder is reset before the contents of each burst or frame are encoded. In this way, the unique word is convolutionally encoded independendy of the data, without using flush bits. This avoids the overhead associated with transmitting flush bits. This aspect of the invention also extends to a corresponding decoding method and to a signal encoded by the method.
According to another aspect of the present invention, there is provided a method of detecting the synchronisation timing of a received burst or frame, in which a received signal including a forward error corrected unique word is decoded using an iterative technique, and the detected number of errors in the unigue word after each iteration is used to determine whether the assumed synchronisation tinning is correct.
Specific embodiments of the present invention will now be described with reference to the accompanying drawings, in which:
Figure 1 is a graph showing the probability of packet loss due to frame sync failure as a function of the threshold number of bits required to be equal to unique word bits in order to detect frame sync, in a prior art frame sync technique;
Figure 2 is a graph showing the probability of packet loss due to frame sync failure as a function of the threshold number of bits required to be equal to unique word bits in order to detect frame sync, in a technique in an embodiment of the present invention;

Figure 3 is a diagram showing the composition of a transmitted frame in an embodiment of the present invention;
Figure 4 is a diagram of the demodulation and decoding stages performed by a receiver in an embodiment of the present invention;
Figure 5 is a table showing the output of a rate 1/3 encoder in a specific embodiment of the present invention;
Figure 6 is a table showing the output of a rate Vz encoder in a specific embodiment of the present invention; and
Figure 7 is a table of sample unique word and parity bit patterns at the start and end of a frame.
In order to explain the advantages of embodiments of the present invention, a prior art frame sync technique will first be described.
In the prior art frame sync technique, the start of a frame of transmitted data is detected by comparing the received bit sequence with a known unique word pattern at the receiver. An N symbol unique word is assumed to be detected if the receiver detects at least n bits equal in value to the unique word pattern within a window of//bits. The criteria for choosing a suitable value of n are the probability that the unique word is present but is not detected and the probability that the unique word is detected but is not actually present, for any random sequence of symbols. The possible events are

The probability of missed detection (Pm) increases with:
a) Increasing threshold n
b) Increasing symbol error rate (decreasing EJNoY and
c) Increasing length of the unique word.
If a unique word is missed, then the whole packet is lost by the receiver. The probability of false detection (Pf) increases with:
a) Decreasing threshold n
b) Decreasing the length of the unique word; and



Science Press, 1984. It is mainly for this reason that long unique words are used in practice.
Embodiments of the present invention eliminate the dependence of Pp on Pf by providing a mechanism by which the receiver can detect a false detection. The overall receiver complexity may also be reduced by allowing detection of false alarms well before the FEC process has been fully completed. Hence, Ps is nov^ given by:

Figure 2 shows Ps as a function of n with N=64 using an embodiment. The independence of Ps on Pf has eliminated the minimization floor; for any value of Ps an appropriate value of // can be chosen, even for the lowest values of EJNp.
With these embodiments, Ppis given by:

By choosing appropriate values for N and n, one can achieve the requirement Pm«Pfee even for small values of N, and hence with short unique words.
In the embodiments, the unique word is treated as part of the data for the purposes of forward error correction. Hence, the unique word detection benefits from the FEC process to remove unique word bit errors, which makes the frame sync decision definitive, In addition, the embodiments allow the use of decoder assisted techniques such as described in 'Irnproving frame synchronization when using convolutional codes' by P. Robertson, Proc. IEEE GLOBECOM, December 1993; the paper by Howlader, Wu and Woemer referenced above; and 'Frame synchronization of convolutionally encoded sequences for packet transmission', by M. Howlader and B. Woemer, Proc. IEEE ICC, New Orleans, June 2000. These techniques may further reduce the value of Pm-
The technique comprises in outline the following steps:
a) The receiver searches for the presence of an N-symbol long unique word pattern and makes decisions based on some threshold n derived from the required Pn.
b) Every instant the receiver assumes that the unique word is detected, it proceeds tademodulation and FEC processing. Optionally, decoder-assisted techniques such as referenced above may be used to enhance the reliability of the unique word acquisition.

c) After each iteration of the FEC decoder, the detected unique word pattern is compared to the expected one and the frame sync hypothesis is tested according to two possible cases:
a. Case 1 - If the frame sync assumption is correct, the FEC should
improve the reliability of all the data, including the unique word. If
the unique word mismatched data is reduced, this is a strong
indication that the unique word has been correctly found. In this case,
the receiver completes the FEC process and outputs the data.
b. Case 2 - If the frame sync assumption is wrong, the amount of
unique word mismatched data should either increase, or not change
as the FEC process attempts to conect the wrong data decisions. This
indicates that the frame sync failure was caused by a false detection.
In this case, the receiver abandons the FEC process and returns to
frame sync search mode.
The frame sync hypothesis can be tested in one of two ways:
i) Sequentially, each time a possible frame sync appears in steps a) and b);
or
ii) Selecting from a list of possible frame sync hypotheses over a finite
interval, sorted according to their strength, where steps a) and b) are replaced by a list of metrics described in the Massey, Scholtz or Howlader, Wu and Woemer papers referenced above. The sequential test method requires greater computational load but gives a result with minimum delay. The hierarchical list method reduces computational load but incurs delay due to the creation of the list.
A specific embodiment will now be described with reference to Figure 3. In this example, the FEC technique is Turbo coding with a variable coding rate and the modulation scheme is BPSK for the unique word section and QPSK for the data section. However, other combinations of FEC and modulation may be used. In general, the unique word and data can be carried using any modulation scheme, such as m-3xy PSK or ;n-ary QAM, for example.
The unique word may be selected from a family of unique words, such fis-Gold or Kasami codes or other pseudo-noise (PN) sequences, according to criteria such as

low auto-correlation and cross-correlation, large number of transitions, or minimum d.c. characteristics. Only one unique word may be used, or one of a set of unique words may be selected to convey information in the unique word, such as packec type.
The selected unique word is added to the data d and input before the data c^ to an FEC encoder comprising a first recursive convolutional encoder CI and a second recursive convolutional encoder C2 in parallel, with a bit interleaver BI connected before the input to the latter. The first encoder CI outputs first parity bits p and the second encoder C2 encodes second parity bits q, which are fed to a puncturing mapper PM. The puncturing mapper outputs punctured first and second parity bits/? "and q^ according to a puncturing scheme which depends on the variable coding rate.
The bit interleaver BI preferably has a capacity sufficient to store the selected unique word and the data bits d, unless a constraint length is applied, as described for example in WO 99/3452 L After each frame is encoded, the FEC encoder is reset to an initial state so that the encoding of each frame is independent.
The data bits d and the first and second punctured parity bits p' and ^^ are input to a QPSK modulator M which outputs channel symbols having Land Q components. The QPSK symbols are transmitted in the middle of the frame F.
The unique word data bits are BPSK modulated by a BPSK modulator BM and the BPSK symbols transmitted as the first 32 symbols of the frame. The first parity bits • UWp generated from the unique word data bits are also BPSK modulated and the first S BPSK symbols transmitted after the unique word data symbols UW. The remaining 24 BPSK symbols of the unique word first parity bits UWp are transmitted at the end of the frame F.
-The unique word data bits UW and the data bits d are interleaved by the bit interleaver BI and input to the second coder C2 to generate the second parity bits q, which are incorporated in the data symbols D in the middle of the fran^ie. However, the symbols may be assembled in the frame F in another order, so long as the order is known at the receiver.
Since a systematic FEC technique is used, the advantageous synchronisation properties of the unique word are preserved in the transmitted signal. Additionally, the incorporation of the unique word bits into the first and second parity bits p and q allows

the correction of unique word bits by the receiver, depending on whether correct frame sync has been established.
One specific example is illustrated in Figure 5, which shows the output bits of a rate 1/3 Turbo coder in the order in which they are input to the puncturing mapper PM. The first 32 of the data bits d and first parity bits p, as highlighted in Figure 5, are BPSK modulated and inserted at the beginning and end of the frame F as shown in Figure 3. However, the modulated symbols niay occupy other positions within the frame unless a panicular order is required in order to reduce the delay of the encoding and modulating stage, as described for example in WO 99/34521.
Another specific example is illustrated in Figure 6, which shows the output of a rate V2 Turbo coder in the order as output to the puncturing mapper PM, in which the shaded bits are punctured. According to the puncturing map, odd-numbered first parity bitsp are punctured except in the rangep -psh which are transmitted so as to give 1/3 coding and therefore better protection to the unique word. This achieves a unique word construction independent of the coding rate.
Figure 7 shows, in hexadecimal, sample sequences of possible unique word bits UW and first parity bits UWp at the beginning and end of a frame.
Figure 4 is a schematic diagram of the process steps perfomied by a receiver in accordance with the present invention. The received signal is demodulated by a unique word demodulator UD, which may be coherent or non-coherent, and is optimised for BPSK demodulation of the unique word signal. The demodulafcd unique word symbols are processed by a unique word correlator UC which generates t list of possible frame sync positfons in time or hypotheses, together with a measure ol^their relative strengths. The unique word correlator may use additional rules, such as Mtssey's rule.
Where the unique word is variable to convey signalling information, the unique word correlator correlates the demodulated symbols with each of the possible unique words and generates a strength for each possible unique word.
The possible hypotheses Hi to HN are sorted by a sorter S according to their strengths. The hypotheses H are processed in order of their hypothesis strength, and for each processed hypothesis the receiver demodulates the received frame using a demodulator D and decodes the demodulated data using an iterative FEC decoder FD corresponding to the FEC coder used to encode the signal. For Turbo decoding, either

the MAP or SOVA algorithms may be used by the FEC decoder FD. After each iteration of the FEC decoding algorithm, the number of unique word errors is compared with the number of unique word errors detected before that iteration, by a verification process V. If the hypothesis is correct, as indicated by the arrow C, the number of errors should decrease over one or more iterations. If this is the case, the decoded data is output at an output stage O and the decoding step is complete for the current frame.
If the number of unique word errors increases or stays the same after one or more decoding iterations, the hypothesis is judged incorrect, as indicated by the arrow I, and the hypothesis H of the next highest strength is selected for processing. The hypotheses are processed in order of strength until a correct hypothesis is found, or all of the hypotheses have been processed without finding a correct one. In the latter case, the frame cannot be decoded, and is discarded at a failure stage FS.
Figure 4 shows multiple demoduladng, decoding and verification steps, but this does not necessarily imply that there are multiple demodulators, decoders and verifiers.
While the use of Turbo codes has been described above, other systematic and/or convoJutional codes may be used to achieve some or all of the effccis of the invention.
Although the encoding and decoding stages are illustrated in terms of discrete processes, either of these stages may be performed by a single processor, such as a DSP. A compfiter program may he provided for execution on the processor so as to perform the encoding or decoding processes. The computer program may be stored on a suitable physical carrier, such as a disc, or transmitted on a suitable signal carrier.



CLAIMS
1. A method of detecting the synchronization timing of a signal including a systematic
forward error corrected synchronisation pattern, comprising the steps of:
a) detecting a possible synchronisation timing of the systematic synchronisation pattern;
b) decoding the signal using the possible synchronisation timing by means of an iterative decoding algorithm, wherein the number of errors of the decoded synchronisation pattern before a non-zero number of iterations of the decoding algorithm is compared with the number of errors of the decoded synchronisation pattern after said non-zero number of iterations, the non-zero number being less than the number of iterations required to decode the signal to a desired quality; and
c) detecting the synchronisation timing of the signal as said possible synchronisation timing if the number of errors after said non-zero number of iterations is less than the number of errors before said non-zero number of iterations.

2. A method.according to claim 1, wherein the synchronisation pattern and parity data cfependent on the synchronisation pattern and independent of the data are input to ^ decoding algorithm in an initial state of the decoding algorithm before the data of parity data dependent on the data are input.
3. .A method of detecting the synchronization timing of a signal including a systematic convolutionally encoded synchronisation pattern and data, comprising the steps of:

a) detecting a possible synchronisation timing of the systematic synchronisation pattern;
b) decoding the signal using the possible synchronisation timing by means of an iterative decoding algorithm into which the synchronisation pattern and parity data dependent on the synchronisation pattern and independent of the data are input in an initial state of the decoding algorithm before the data or parity data dependent on the data are input, wherein an error metric of the decoded synchronisation pattern before a non-zero number of iterations of the decoding

algorithm is compared with the error metric of the decoded synchronisation pattern after said non-zero number of iterations, the non-zero number being less than the number of iterations required to decode the signal to a desired quality; and c) detecting the synchronisation timing of the signal as said possible
synchronisation timing if the error metric after said non-zero number of iterations is less than the error metric before said non-zero number of iterations.
4. A method according to claim 3, wherein said error metric is the number of errors in the decoded synchronisation pattern.
5. A method according to any preceding claim, further comprising decoding the. signal using at least one further iteration of the decoding algorithm if the synchronisation timing of said signal is detected.
6. A method according to any preceding claim, wherein step a) includes detecting a plurality of possible synchronisation tinaings of said signal together with a
0
likelihood of each said possible synchronisadon timing, and steps b) and c) are performed for said possible synchronisation timings in order of likelihood until the synchronisation timing is detected.
7. A method according to any one of claims 1 to 5, wherein, if synchronisation is not
detected, the method is repeated when another possible synchronisation timing is
detected.
8. A method according to any preceding claim, wherein there are a plurality of possible synchronisation patterns, and steps a), b) and c) are performed for each possible synchronisation pattern.
9. A method of generating a frame of forward error corrected data, comprising: a) receiving data;

b) convolutionally encoding said data together with a synchronisation pattern, wherein said synchronisation pattern is input before said data is input, so as to generate as output a first encoded output which is dependent on the synchronisation pattern and independent of the data and a second encoded output which is dependent on said data; and
c) genergiting said frame of forward error corrected data from said output of the encoding step and from said synchronisation pattern in unencoded form.

10. A method according to claim 9, wherein the encoding step begins from a predetermined initial state before the data and synchronisation pattern are encoded.
11. A method according to claim 9 or 10, including puncturing some of the second encoded output so that it is not included in said generated frame, while including all of said first encoded output in said generated frame.
12. A method according to any preceding claim, wherein said synchronisation pattern is selected from a group comprising the bit patterns of the hexadecimal numbers E4564ADA, BED8B3EA, F2F5F496, C9113642. F9A42BB1, D4E35729, 4CB9D9D1, 6AAF7A6E, AE7E4BB5, 514BBSBA, B5896CCD, AS7B0DA6, 5A1A679D, 61FEA549, A32AD281, 775D1B05 and DFB2880E
13. Apparatus for detecting the synclironization liming of a signal including a systematic forward error corrected synchronisation pattern, comprising:

a) a preliminary synchronisation detector for detecting a possible synchronisation timing of the systematic synchronisation pattern;
b) a decoder for decoding the signal using the possible synchronisation timing by means of an iterative decoding algorithm, wherein the number of eirors of the decoded synchronisation pattern before a non-zero number of iterations of the decoding algorithm is compared with the number of errors of the decoded synchronisation pattern after said non-zero number of iterations, the non-zero number being less than the number of iterations required to decode the signal to a desired quality; and

c) a definitive synchronisation detector for detecting the synchronisation timing of the signal as said possible synchronisation timing if the number of errors aft'^.r said non-zero number of iterations is less than the number of errors before said non-zero number of iterations.
14. Apparatus according to claim 13, wherein said decoder is arranged to receive the synchronisation pattern and parity data dependent on the synchronisation pattern and independent of the data in an initial state of the decoder.
15. Apparatus for detecting the synchronization timing of a burst signal including a systematic convolutionally encoded synchronisation pattern and data, comprising:

a) a preliminary synchronisation detector for detecting a possible synchronisation timing of the systematic synchronisation pattern;
b) a decoder for decoding the signal using the possible synchronisation timing by means of an iterative decoding algorithm into which the synchronisation pattern and parity data dependent on the synchronisation pattern and independent of the data are input in an initial state of the decoding algorithm before the data or parity data dependent on the data are input, wherein an error metric of the decoded synchionisation pattern before a non-zero number of iterations of the decoding algorithm is compared with the error metric of the decoded synchronisation pattern after said non-zero number of iterations, the non-zero number being less than the number of iteradons required to decode the signal to a^desired quality; and
c) a'definitive synchronisation detector for detecting the synchronisation timing of the signal as said possible sjTichrGnisation dniing if the error metric after said non-zero number of iterations is less than the error metric before said non-zero number of iterations.
16. Apparatus according to claim 15, wherein said error metric is the number of errors
in the decoded synchronisadon pattern.

17. Apparatus according to any one of claims 13 to 16, wherein said decoder is arranged to decode the signal using at least one further iteration of the decoding algorithm if the synchronisation timing of said signal is detected,
IS. Apparatus according to any one of claims 13 to 17, wherein the preliminary detector is arranged to detecting a plurality of possible synchronisation timings of said signal together with a likelihood of each said possible synchronisation timing, and the decoder and definitive detector are arranged to process said possible synchronisation timings in order of likelihood until the synchronisation timing is detected.
19. Apparatus according to any one of claims 13 to 17, wherein the decoder and definitive detector are an*anged to process said possible synchronisation timing as it is detected by the preliminary detector, and the preliminary detector is arranged to detect a further possible synchronisation timing if the synchronisation timing is not detected.
20. Apparatus according to any one of claims 13 to 19, wherein there are a plurality of possible synchronisation patterns and the preliminary detector, decoder and definitive detector are arranged to process each possible synchronisation pattern.
21. Apparatus for generating a frame of forward error corrected data, comprising:

a) a convolutional encoder arranged to encode data together with a synchronisation partem, wherein said synchronisation pattern is input to the convolutional encoder before said data is input, so as to generate as output a first encoded output which is dependent on the synchronisation pattern and independent of the data and a second encoded output which is dependent on said data; and
b) a frame generator arranged to generate said frame of forward eiTor corrected data from said output of the encoding step and from said synchronisation pattern in unencoded form.

22. Apparatus according to claim 21, wherein the encoder is arranged to begin encoding the data and synchronisation pattern from a known state,
23. Apparatus according to claim 21 or 22, wherein said frame generator is arranged to puncture selected portions of the second encoded output so that it is not included in said generated frame, while including all of said first encoded input in said generated frame.
24. Apparatus according to any one of claims 13 to 23, wherein said synchronisation pattern is selected from a group comprising the bit patterns of the hexadecimal numbers E4564ADA, BED8B3EA, F2F5F496, C9113642, F9A42BB1, D4E35729, 4CB9D9D1, 6AAF7A6E, AE7E4BB5, 514BB8BA, B5896CCD, A87B0DA6, 5A1A679D, 61FEA549. A32AD281, 775D1B05 andDFB28S0E.
25. A computer program arranged to perform a method according to any one of claims 1
to 12 when executed by suitably arranged apparatus.
26, A carrier bearing a computer program according to claim 25.

27. A method of detecting the synchronization timing of a signal
substantially as herein described with reference to the
accompanying drawings.
28. An apparatus for detecting the synchronization timing of a burst
signal substantially as herein described with reference to the
accompanying drawings.



Documents:

1191-chenp-2003-abstract.pdf

1191-chenp-2003-claims duplicate.pdf

1191-chenp-2003-claims original.pdf

1191-chenp-2003-correspondnece-others.pdf

1191-chenp-2003-correspondnece-po.pdf

1191-chenp-2003-description complete duplicate.pdf

1191-chenp-2003-description complete original.pdf

1191-chenp-2003-drawings.pdf

1191-chenp-2003-form 1.pdf

1191-chenp-2003-form 18.pdf

1191-chenp-2003-form 26.pdf

1191-chenp-2003-form 3.pdf

1191-chenp-2003-form 5.pdf

1191-chenp-2003-pct.pdf


Patent Number 209349
Indian Patent Application Number 1191/CHENP/2003
PG Journal Number 38/2007
Publication Date 21-Sep-2007
Grant Date 27-Aug-2007
Date of Filing 31-Jul-2003
Name of Patentee M/S. INMARSAT LTD
Applicant Address 99 City Road, London EC1Y 1AX,
Inventors:
# Inventor's Name Inventor's Address
1 FEBVRE, Paul 229 Britannia Road Ipswich Suffolk IP4 5HF
PCT International Classification Number H04L 1/00
PCT International Application Number PCT/GB2002/000431
PCT International Filing date 2002-01-30
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 0102448.8 2001-01-31 U.K.