|Title of Invention||
"SEMI CONDUCTOR CHIP WITH SURFACE COVERING"
|Abstract||This invention relates to a semiconductor chip with atleast inane layer of a semiconductor chip-carrier (1), atleast in one group arranged circuits (T1, T2) and with at least in one wiring level (3) supply-and signal lines (Vss, Vdd, SL1, SL2) running , over the circuits (T1, T2) wherein at least in one wiring level (3) over at least one circuit group, the supply - and signal lines (Vss, Vdd, SL1, SL2) have a maximum width so that the distance between two lines in each case is minimum.|
- 1 A- -
GE 98 P 2365
Semi conductor chip with surface covering.
She invention refers to a semi conductor chip with atleast in one layer of a semiconductor chip carrier realised, at least in a group organised circuit and with atleast in a wiring level supply and signal lines running over the circuit.
Such a semiconductor chip is knoum from the IP 0378 306 A2. In semiconductors chip there, a first circuit group in a protected area and a second circuit group in a not protected area are arranged. The fuse of first area takes place in known semiconductor chip through a conducting coat, which is arranged over the wiring level of first circuit group. This cdnductiag coat is electrically connected with the circuit group,whererein an orderly function of this circuit group is provided only at intact coat,
The first circuit group covers have a mini-processor as well as asso ciated periphery circuits like memory and a transfer logic circuit. In the memory specially secret informations can remain. It is also conceivable that the micro processor has a special structure, which is specially well suited for security relevant functions, through the conducting coat, whose integrity is continuously checked, a spying out by means, for example of a scanning electron microscope during the operation of circuit is prevented.
Indeed this conducting coat demands a further process step in the manufacture of semiconductor chip. Besides corresponding evaluation circuits for the detection of integrity of conducting coat are necessary.
Therefore it is the assignment of the invention to provide a semiconductor chip Which avoids this disadvantage.
The problem is solved that in a semiconductor chip as per the type atleast in one wiring level over atleast one circuit group the supply and signal lines have a largest possible width; so: that the distance between two lines is maximum around double of minimum realisable distance as per the respective position of a technology generation. In an advantageous development, the distance between two lines corresponds essentially the minimum realisable distance as per the respective position of a technology generation.
Mainly it means herein that the distance between the lines along the largest part of respective line length is minimum or maximum double so large as minimum. Through this less distance at one side the chip surface is almost covered through the anyway necessary conducting wiring layer and orotected from optical and also electron optical investigations. On the other side a large area distance of lines in order to take up an optical surface investigation would lead to it that the circuits do not function anymore without that further detector cfrcuite were necessary.
Distance only at certain points of lines for example in order to separate circuit parts does not succeed since through the slight distance a bonding of neighboured lines will take place. The widening of lines takes place in design of topology of semiconductor chip. Herein first the earth lines are worked out as wide as possible in order to guarantee a best possible capacitive coupling of earth to chip carrier as well as to guarantee a voltage supply of low impedance at minimum joining of remaining signal lines among each other. In next step the supply voltage lines are widened. First at end the signal lines are widened in order to ensure a least possible coupling of signal lines-among each other.
The widening of lines as per invention at least in one wiring level
takes place at least over security critical circuit parts like me
mory for secret codes or special encoding circuits. It is however
of advantage to widen the lines of the entire surface in order not
to provide any possible hint to a probable attacker, where security
relevant circuit parts lie-
in case more number of wiring levels exist, it is possible to -cover
different circuit groups in different wiring level wherein here al
so covering overlapping can arise. Besides it is possible with mul
tiple wiring levels, to plan were complete coverings without addi
The invention is explained followingly closer with help of accompanying Figures
in an execution example.
Figure 1 on principle a cross section representation with a circuit - and wiring level of a semiconductor chip. Figure 2 a. cutout from a wiring section as per state of art find Figure 3 the same cutout of a wiring level as per the invention.
The cross section representation as per Figure 1 shows a p-conduct-ing semiconductor chip carrier 1 in which as circuit example 8. CMOS-inverter is realised. This is built with one n-channel-transistor T and a P-channel-transistor T 2. Over the active coat of semiconductor chip carrier'1, an insulating coat- 2, which is formed mostly out of Silicon oxide is arranged. A wiring level 3 is assembled over this insulating layer 2. This comprises of earth lines VSS, supply voltage lines Vdd as well as signal lines SL1, SL2. For realisation of CMOS- inverters the source area S1 of p-channel-transistor T1 through the insulating layer 2 throughout is connected with the earth line VSS. Both the drain areas D1of n-channel transistor T1 as well as drain area 2 of P-channel transistor T2 are connected through the insulating layer 2 through out with the signal line SL1 o The source area S2 of P-channel -transistor T2 is connected with the supply voltage line Vdd. In the insulating layer 2 gate electrodes G1 and G2 are arranged, which are connected with a signal line SL2. Over the wiring level 3, usually a further protective coat in form a passivation layer 4 is arranged. In figure 1 in fact only one active layer and a wiring level 3 is shown, the invention is realised however likewise with multiple number of active layers and/or multiple number of wiring levels.
In Figure 2 a cutout from a wiring level as per state of art is shown. As it is identified, between lines there are considerable gaps, so that under circumstances the circuit structure lying thereunder can be spotted by optimum ways.
Figure 3 shows on the other hand a wiring level as per invention, in which all lines are so far widened, that among them e realisable distance results as per the respective status of technology generations. Through here, while at one hand, an optical investigation of circuit structure under the wiring level is not possible, on the other hand, in experiments to remove the conductor, a bonding of individual conductors takes place, so that short circuits generate. A complete removal of conductor would prevent the function of circuit lying thereunder.
1 - Semiconductor chip with atleast in one layer of a semiconductor chip carrier (i) realised atleast in one group of arranged circuits
2. Semiconductor chip as claimed in claim i, wherein the width of lines (Vss, Vdd, SL1, SL2) is sized in such a way that the distance between two lines mainly, according to the respective status of technology of generation corresponds to the minimum realisable distance-
This invention relates to a semiconductor chip with atleast inane layer of a semiconductor chip-carrier (1), atleast in one group arranged circuits (T1, T2) and with at least in one wiring level (3) supply-and signal lines (Vss, Vdd, SL1, SL2) running , over the circuits (T1, T2) wherein at least in one wiring level (3) over at least one circuit group, the supply - and signal lines (Vss, Vdd, SL1, SL2) have a maximum width so that the distance between two lines in each case is minimum.
|Indian Patent Application Number||701/CAL/1999|
|PG Journal Number||11/2007|
|Date of Filing||10-Aug-1999|
|Name of Patentee||SIEMENS AKTIENGESELLSCHAFT|
|Applicant Address||WITTELSBACHERPLATZ 2,80333 MUNCHEN,|
|PCT International Classification Number||HOIL 27/10|
|PCT International Application Number||N/A|
|PCT International Filing date|