Title of Invention

"A POWER LINEARIZER OF A CDMA SYSTEM TO CONTROL A DIGITAL GAIN AND METHOD THEREOF"

Abstract The present invention relates to a power linearizer to control a digital gain of a voltage controlled power amplifier and method thereof in a CDMA system. Because a general power linearizer controls an analog amplification control signal of a power amplifier, it is difficult to accurately compensate a power. Accordingly, a linearization input unit 100 according to the invention calculates an adjust gain a[n] by using a difference power between a linear power and a non-linear power for an input power s[n] and controls a level of the input power s[n] by using a value added the adjust gain a[n] and a transmission gain g[n]. Therefore, the invention easily performs a power compensation by easily compensating the level of the input power s[n] of the voltage controlled power amplifier 300.
Full Text BACKGROUND OF THE INVENTION 1. Field of the Invention
[1] The present invention relates to a power linearizer of a CDMA system to control a digital gain and method thereof.
2. Background of the Related Art
[2] In general, 2 radio frequency band amplifier using active elements gentrarw many uadesired distortion components according TO a change of a power level.
[3] Especially when the amplifier is opcratedin the vicinity of a saturation area, a. non-linear phenomenon remarkably appears to distort an zaplitude and a phase of an output, and when more than rwo signals are inputted, intermoduiatjon distortion (IMD) components axe generated between the inpuc signils, having such influence on the adjacent channel,
[4j The IMD components work as a noise source to degrade a transmission oualiry of z commuaicaiioa systcia and reduce s cipzciry of the CDM-\ sysztza.
[i] Figure 2 is a ;chemz.uc block diagram of a related art pcrr lintznzzr c: a CDMA rystem, As shows thsre^:, the related art poer liseaxiscr la eludes aa iapu: uzit 10 for coavertbg a distal Lt signal (sfrj bio znzlog si£na;( s[:}). 2 Unearizaricn
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amplifying controller 20 fcr performing zn i^nplification control to remove a con-iiaeir characteristic of a power amplifier 30, and z. power amplifier 30 for amplifying a power oi an input signal (S(T)) inputted from the input ucit 10 und^r the control of the linearization amplifying controller 20.
[6] The input urit 10 includes a multiplier 11 for muluplying T.he dagiral input
signal (s[nB and a transmission gain signal (gjaj togciher, and s digital-to-analog converter
12 for converting the digital signal outputted from the multiplier 11 to an analog signal.
[7] The linearization amplifying controller 20 includes a multiplier 21 for
multiplying power control information (c[n]), which controls an increase znd d^crsase of
a-piification, and a power control step (P) indicative of an increased or decreased po"s-'er
value. It funher includes an accumulator 22 for accmnulaung an output signal or the
multiplier 21, an adder 23 for adding a digital output signal of the accumulator 12 and an
adjust gam (a[nj) for removing a non-linear characteristic of :he power amplifier 30, and
a GJgital-to-analog converter 24 for converting the digital signal outpurred from the adder
23 into an amplification ccntro] signal of an anslog form.
[2] The power control information en] has a ccntro: value of 1 or 2 in digital form- One control value ir."cases the power zs high as a zpzziTizd vaJue s-nd the other ccntro: value deceases ths pr.wcr as lew zs z speafied vaJuc. T^t* >pccirieH po^'cr vaJuc rsft-Ts :o the power contro: step (P).
2

[5] The multiplier 21 of the linearization amplifying controller 20 multiplies the power control information c[n] and the power control step (p), and the accumulator 22 accumulates the output signal of the multiplier 21.
[10] The adder 23 adds the output signal of the accumulator 22 and the adjusi gain (a[a]) and outputs an zs^phiicsxioz control signal for controlling amplification of the power amplifier 30 so as to remove a non-linear characteristic of the power amplifier 30, The adjust gain afn] is a value to adjust the amplification so that the non-linear power amplifier 30 may have a linearity. The value of afn] used for generating die amplification control signal to remove the non-linear characteristic of the power 2rnp liner 30 is critical. [11] The digital/analog converter 24 of the linearization amplifying controller 20 converts the output sig-al of rhe axider23 into an analog forin, and grosratEs an analog amplifjcauion control signal (v(i)) co control an amplification leve! of the power amplifier 3D.
[12] The multiplier 11 of the input unit 10 multiplies the digital input signal (s[nj and the transmission gan signal (g[n]), and the digital/analog converter 12 of rhe input unit 3 0 convx'rts che digital s:gna] outputtcc from the multiplier 11 into an anaiog signal s{i) ind outputs IT to the pav^r ampiifier 30.
[13] The power irr.plirier 30 amplifies the power of the output signal "(:) of the digital/analog converts: 12 according :o tbe analog arnpiiijetuo- control signal (v(:))
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ourpurted from the digit al/analog convener 24 of the linearization simplifying controller 20.
[14] Figure 2 is a graph showingpower characterisTic curves of 2 power linearizer in accordance with the related art amplifier. As shown, PA(V) indicates an actual power characteristic c-Lrve of the power znpuner 30, PB(V) indicates a required linear power characteristic curve, aadPC(V) indicates £ power compensation rcrve to remove the nonlinear characteristic,
[15] In the CDMA system, m order to minimize die influence on the adjacent channel and increase the subscriber accommodation capacity: each mobile terminal should use the minimum power.
[16] With reference to Figure 2, on the assumption that a desired power is P3, when the power amplifier 3C has a linear chsxacteristic, Vj is to be applied :o zhe power amplifier 30 as a value et the input signal. However, when the voltage of V, is inputted, the power amplifier 30 outputs a power of P, according zo the aos-lmear characteristic. [17] Accordingly, the power of P2 should be obtained through die power compsnsation. That is, is shown :n the outpui charactcrisxic of :he power amplifier 30. zr. i-3pu; vcltasc of V- is .necessarv to output the accurz.1:; P,.
[ ] Thus, the va)ue of V, - V, is compensated by uimg s value of the £rrpl:ficitio2 control s-cr.aj v'x) o: the power amplifier 30, zzzd tht vajue of the ad;usr gsxn
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a[n] used for generating the corresponding amplification control signal v(t) is TO be generated.
[19] The value of a[n] is computed by using a difference value between z requested input voltage according to the linearization characteristic curve for outpurung z desired power and an actual input voltage according to a nonlinear characteristic curve for ou-purting the desired power. The conventional power lincarizer hzs the adjust gam a[n], thai is, the compensation value for outputting a desired power, in 2 table form. Accordingly, a value to be compensated at an arbitrary point (an input voltage) is computed by linearly interpolating a corresponding value stored in the table.
[20] The power lincarizer of the related art has many problems. For example, the conventional power liDearizer should have a slope of a straight line for interpolation and an offset value, aad a power compensation value at an arbitrary position of the equation of the straight line should be computed, which-makes it complicated to Implement the power linsarizer.
[21] In addition, the conventional power linearizes compensates the power by adjusting the amplificaticr control signal of the amplifier as much 2s an error bera'een *_he linear power (a requested power) and the non-linear power. In this respect, the amplification control signal costrob the i=ipliiicat;on of the power ampliSer in an analog formal. Since aniiog SIETIIS aj-e influenced by noise, ix is difneuh to accurately control the
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[22] The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
[23] An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
[24] Another object of the present invention is to provide a power linearizer of a CDMA system that is capable of accurately and easily compensating a non-linearity of a voltage controlled power amplifier (VCA).
[25] Another object of the present invention is to provide a power linearizer of a CDMA system that is capable of increasing a capacity of the CDMA system by controlling a digital gain of the VCA.
[26] Accordingly, the present invention provides a power linearizer to control a digital gain signal, comprising : a linearization input circuit coupled to receive a digital input signal and generate a compensated analog input signal to compensate for non-linear characteristics of a power amplifier, wherein the compensated analog input signal is generated with a gain adjust signal that compensates the non-linear characteristics of the power amplifier ; an amplification controller configured to control an amplification of the power amplifier ; and the power amplifier coupled to amplify the compensated analog input signal in accordance with a control signal.
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[27] The present invention also provides a power linearizer to control a digital gain signal comprising : an adder configured to add a gain adjust signal and a transmission gain signal to generate a digital gain signal ; the gain adjust signal configured to compensate for a non-linear characteristic of a voltage controlled power amplifier ; a multiplier coupled to multiply the digital gain signal and a digital input signal to generate a compensated digital input signal ; and a digital/analog converter coupled to convert the compensated digital input signal into a compensated analog input signal.
[28] A power linearizing method, comprising the steps of : computing a power error value between a linear power (P2) and a non-linear power (Pi) for an input voltage ; square root processing the power error value and computing an adjust gain value ; adjusting a transmission gain signal using the adjust gain value ; compensating a level of a digital input signal using the adjusted transmission gain signal ; and amplifying a power of the level-compensated input signal to generate a linearized power signal.
[29] The present invention also provides A power linearizer to
compensate a digital input signal, comprising : means, such as herein described, for computing a power error value between a linear power (P2) and a non-linear power (Pi) for an input voltage ; means, such as herein described, for SQUARE ROOT processing the computed power error value and computing an adjust gain value ; means, such as herein described, for adjusting a transmission gain signal by using the computed adjust gain value means, such as herein described, for compensating a level of a digital input signal using the adjusted transmission gain signal ; and means, such as herein described, for amplifying a power of the level-compensated input signal and outputting a linearized power signal.
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[30] To further achieve at least the other objects in whole or in
part and in accordance with the purpose of the invention, and embodied and broadly described herein, there is provided a method of compensation a nonlinear characteristic of a power amplifier, comprising adding a digital compensation signal to a digital gain adjust signal to generate an adjusted digital compensation signal, applying the adjusted digital compensation signal to a digital input signal to generate an adjusted digital input signal, and converting the adjusted digital input signal to an adjusted analog input signal
[31] Additional advantages, objects, and features of the
invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

[32] The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein:
[33] Figure 1 is a schematic block diagram showing the construction of a related art power linearizer of a CDMA system;
[34] Figure 2 is a graph showing power characteristic curves of the related art power ljneanzer;
[35] Figure 3 is a schematic block diagram showing :hs construction of 2 power linearize of a CDMA sysrern in accordance with a preferred embodiment of the present invention;
[36] Figure 4 is a graph showing a power characrcrisric curve of a power linearizing method in accordance with the preferred embodiment of the present invention; and
[37] Figure 5 is a flow chair of the power linearizing izethod of a CDMA system in accordance with the preferred embodiment of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS [38] In the preferred embodiment, in order ;o remove .ncn-hr.ca.nry ;o have s iirjraj cnara. et eristic, a level of a voltage inputted to a power niplifier is prelcrably adjusted raihex than adjusting an amplification control signal o: ibe power amplifier.
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[3 9] Figure 3 is a schematic block diagram showing trie cons:ruction of a power Uiicarizer of a CDMA, system Ln accordance with a preferred embodiment of the present invention. As shown therein, an adjust gain (a[n]) is added ro the transmission gain sign a] g[n], to produce linearity in the power amplifier.
[40] Referring to Figure 3, the power amplifier preferably lEcludes a iinearizarioa input unit 100 to compensate a level of an input signal to remove a non-lineariry of a power amplifier 300, an arnpIi5cation controller 20i0 ro conirol arr.pHfics.tJon of the power amplifier 300, and a power amplifier 300 operated under the control of the amplification controller 300s to amplify a power of a signal s{t) outputted from the lineax-ination input unit ICO.
[41] The linearization input unit. 103 preferably includes an'arHer 110 to add an
adjust gain (a[nj to a transmission gain signi\ (gfnj). The adjust gair vaiue a[n] preferably
removes the non-line2r characteristic of the power amplifier 300 and the transmLssion gain
g[n] adjust a digital gain. Thz lictarizer inpu: unit 100 further includes a multiplier 120
to multiply the djgita] gain ouipucied from the adder 110 and the dig:ral input signal (s[a])
and adjust a level of thr digital input signal, and a digital/analog converr-r 130 to convert
the digital input signal, which has been level-adjusted by the multiplier 120, to an analog
signal.
[42] The ampl^Cfttioa controller 200 preferably includes a multiplier 210 icr multiplying a power control mfonr.ztion. (cLr.X1 for controlling arj ^ncrc^se or decrtase of
10

amplification and a power control step (P) indicative of a power value 10 be increased or decreased. "The amplification controller 20C also preferably includes an accumulator 22C for accumulating the output signal of the multiplier 210; and a digital/analog convener 23C for converting die amplification control signal (v(t)) in a digital form outputted torn zhc accumulator 220 into an analog form, and controlling the power amplifier 300.
[43] Figured is a graph showing a power characteristic curve adopted to a power linearizing method accordance with a preferred embodiment of the present invent;on. As shown therein, PA(V) indicates an actual power characteristic curve of the power ampHfer 300, and PB(V) indicates a requested h'neai power characteristic carve.
[44] On the assumption thai a desired power Is P., when the power amplifier 300 is operated according to the linear power characteristic curve of PB(V), the input voltage cf Vj is preferably applied to the power amplifier 300. la this respect, however, the power amplifier 300 may acn:d]y output a power according to the non-linear power characteristic such as PA(V).
[45] Accordingly, when the input voltage of V. is applied to the power amplifier 300, the power oi P, may be outpurred. Thus, the difference between the desired power Lnd the actually inputted power is P.-P2- In the preferred embodimtai, the error of the output power, that is, p.-P3. preferably is compensated to remove the noa-Iincaxity cf tht power £_rr;plifitr 300
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[46] Figure 5 is a flow chart of the power linearizing method of a CDMA system in accordance with the preferred embodiment of the present invention. In order to compensate the difference value (tie power error) between the actual non-Linear power P corresponding ;o the input voltage V. and the desired linear power P,, the power error ,P--P2! is preferably computed in step SH.
[47] When t power error is computed for a corresponding input voltage, an adjust gain a[n] is preferably computed in the following equsuon (1) for die pou-er error ir. step SL2.
a[n] - -sqrt |P,-P2| {P^PJ "I ; Equation 1
- sqrt iP:-F3] _(P2>PJ/
[48] In this manner, the power linearizcr of the present invention preferably computes the adjust gain a[n] for the finite number of input voltages by -jsing the ens--act eristic curve of input voltage to output voltage, and inzy store the corresponding input voltage and the adjust gain :n a look up table.
[49] Thereafter, the adjust gan a[n] searched from the look-up table for the current input voltage is preferably inputted to the adder 110 of the linearization input unit 100. The adder 110 preferably adds the transmission ga;.n signal g[n] and the adjust gain aTn] and adjusts the irans=iissicn grain signal g[n] in step 513.
[50] The adjusted trsjasmissioa gain is preferably i.ipuntd ro the multiplier 120. Thrn, -he multiplier 120 rr.sy multiply tic current digital ir-pu; voitage s[-j tr.d the
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adjusted transition gain together TO adjusr the level of the digital input signal in step
S14.
[51] The level-adjusted input signal is preferably inputted to tie digital/analog convener 130 and converted into an analog form, and ther. applied to the power amplifier 300 in step S15.
[52] The power amplifier receives the analog input signal which has been level-adjusted to rtmeve the noa-linearity and amplifies the power. Thus, the power-ampUfied signal obtains the linear characteristic. The power is compensated by controlling the level of :he input signal, -which is more resistant to noise than the amplification control signal of the power amplifier. Therefore the pover linearization ot the power amplifier cm be more accurately and easily controlled.
[53] As so far described, the power linearizcr of a CDMA, system and its method of the preferred embodiment have many advantages. For example, by adjusting the voltage inputted to the input terminal of the voltage controlled power amplifier (VCA), the non-linearity of the VCA can be accurately compensated. Additionally, the power compensation can be more easily performed Moreover, :be capacity of the CDMA rvsxem can be increased.
[54] The foregoing embodiments and ad\-zr.tages are merely exemplary and are EG; 10 be construed as limiting the present jvention. Tne presen: teachizg can be readily 3ppacd:o chorr pcs of appa. The descriptioz of ihe prefer,: ir.vsntion is intended
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to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structure described herein as performing the recired function and not only structural equivalents but also equivalent
structures.
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WE CLAIM :
1. A power linearizerto control a digital gain signal, comprising :
a linearization input circuit coupled to receive a digital input signal and generate a compensated analog input signal to compensate for nonlinear characteristics of a power amplifier, wherein the compensated analog input signal is generated with a gain adjust signal that compensates the nonlinear characteristics of the power amplifier;
an amplification controller configured to control an amplification of the power amplifier; and
the power amplifier coupled to amplify the compensated analog input signal in accordance with a control signal.
2. The linearizer as claimed in claim 1, wherein the linearization input
circuit comprises :
an adder configured to add the gain adjust signal with a transmission gain signal to output a digital gain signal;
a multiplier configured to multiply the digital gain signal and the digital input signal to provide a compensated digital input signal; and
a digital/analog converter configured to convert the compensated digital input signal into a compensated analog input signal.
3. The power linearizer as claimed in claim 2, wherein the gain adjust
signal is computed by square root processing an error value between a linear
power (P2) and a non-linear power (Pi).
4. The power linearizer as claimed in claim 3, wherein the error value
is equal to an absolute value of Pi _ P2, wherein square root processing is
equal to a negative square root of the error value when Pi is greater than P2>
and wherein the square root processing is a positive square root of the error
value when P2 is greater than Pi.
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5. The power linearizer as claimed in claim 3, wherein P2 is a desired
power output of the power amplifier and Pi is an uncompensated power
output of the power amplifier.
6. The power linearizer as claimed in claim 1, wherein the amplification
controller comprises :
a multiplier configured to multiply a power control information to control an increase or decrease of amplification and a power control step signal indicative of an increased or decreased power value ;
an accumulator configured to accommodate an output signal of the multiplier; and
a digital/analog converter configured to convert a digital amplification control signal outputted from the accumulator into an analog form to control the power amplifier.
7. A power linearizer to control a digital gain signal comprising :
an adder configured to add a gain adjust signal and a transmission gain signal to generate a digital gain signal; the gain adjust signal configured to compensate for a non-linear characteristic of a voltage controlled power amplifier;
a multiplier coupled to multiply the digital gain signal and a digital input signal to generate a compensated digital input signal; and
a digital/analog converter coupled to convert the compensated digital input signal into a compensated analog input signal.
8. The power linearizer as claimed in claim 7, comprising a voltage
controlled amplifier coupled to receive an amplification control signal, and
configured to amplify a power of the compensated analog input signal.
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9. The power linearizer as claimed in claim 7, comprising an
amplification control signal generator configured to control the voltage
controlled power amplifier.
10. The power linearizer as claimed in claim 9, wherein the amplification
control generator comprises :
a multiplier configured to multiply a power control information to control an increase or decrease of amplification and a power control step signal indicative of an increased or decreased power value ;
an accumulator configured to accumulate an output signal of the multiplier; and
a digital/analog converter configured to convert a digital amplification control signal outputted from the accumulator into an analog form to control the power amplifier.
11. The power linearizer as claimed in claim 7, wherein the gain adjust
signal is computed by square root processing an error value between a linear
power (P2) and a non-linear power (Pi).
12. The power linearizer as claimed in claim 11, wherein the error value
is equal to an absolute value of Pi - P2, and wherein square root processing
comprises taking a negative square root of the error value when Pi is greater
than P2, and wherein the square root processing comprises taking a positive
square root of the error value when P2 is greater than Pi.
i
13. A power linearizing method,,comprising the steps of :
computing a power error value between a linear power (P2) and a non-linear power (Pi) for an input voltage ;
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square root processing the power error value and computing an adjust gain value ;
adjusting a transmission gain signal using the adjust gain value ;
compensating a level of a digital input signal using the adjusted transmission gain signal; and
amplifying a power of the level-compensated input signal to generate a linearized power signal.
14. The method as claimed in claim 13, wherein adjusting the
transmission gain signal comprises the steps of:
storing each of a plurality of input voltages and corresponding adjust gain values in a table ;
selecting an adjust gain value for the input voltage from the table ; and
adding the selected adjust gain value to the transmission gain and adjusting the transmission gain.
15. The power linearizing method as claimed in claim 13, wherein the
error value is equal to an absolute value of Pi _ P2, and wherein the square
root processing comprises taking a negative square root of the error value
when Pi is greater than P2, and wherein the square root processing comprises
taking a positive square root of the error value when P2 is greater than Pi.
16. The power linearizing method as claimed in claim 13, comprising
providing an amplification control signal to a power amplifier to control the
amplification of the level-adjusted compensated input signal.
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17. The power linearizing method as claimed in claim 16, wherein
providing an amplification control signal comprises the steps of:
multiplying a power control information for controlling an increase or decrease of amplification and power control step indicative of an increased or decreased power value together;
accumulating an output signal of the multiplier; and
converting an amplification control signal in a digital form outputted from the accumulator into an analog form, and
controlling the power amplifier using the amplification control signal.
18. A power Nnearizerto compensate a digital input signal, comprising :
means, such as herein described, for computing a power error value
between a linear power (P2) and a non-linear power (Pi) for an input voltage ;
means, such as herein described, for SQUARE ROOT processing the computed power error value and computing an adjust gain value ;
means, such as herein described, for adjusting a transmission gain signal by using the computed adjust gain value ;
means, such as herein described, for compensating a level of a digital input signal using the adjusted transmission gain signal; and
means, such as herein described, for amplifying a power of the level-compensated input signal and outputting a linearized power signal.
19. The power linearizer as claimed in claim 18, wherein the error value
is equal to an absolute value of Pi _ P2, and wherein SQUARE ROOT
processing is equal to a negative square root of the error value when Pi is
greater than P2, and wherein the SQUARE ROOT processing is a positive
square root of the error value when P2 is greater than Pi.
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-20-
20. The power linearizer as claimed in claim 18, comprising means,
such as herein described, for generating an amplification control signal and
outputting the amplification control signal to the means for amplifying, such as
herein described.
21. A power linearizer, substantially as herein described, particularly
with reference to and as illustrated in the accompanying drawings.
The present invention relates to a power linearizer to control a digital gain of a voltage controlled power amplifier and method thereof in a CDMA system. Because a general power linearizer controls an analog amplification control signal of a power amplifier, it is difficult to accurately compensate a power. Accordingly, a linearization input unit 100 according to the invention calculates an adjust gain a[n] by using a difference power between a linear power and a non-linear power for an input power s[n] and controls a level of the input power s[n] by using a value added the adjust gain a[n] and a transmission gain g[n]. Therefore, the invention easily performs a power compensation by easily compensating the level of the input power s[n] of the voltage controlled power amplifier 300.

Documents:

00721-cal-2001-abstract.pdf

00721-cal-2001-claims.pdf

00721-cal-2001-correspondence.pdf

00721-cal-2001-description(complete).pdf

00721-cal-2001-drawings.pdf

00721-cal-2001-form-1.pdf

00721-cal-2001-form-18.pdf

00721-cal-2001-form-2.pdf

00721-cal-2001-form-3.pdf

00721-cal-2001-form-5.pdf

00721-cal-2001-g.p.a.pdf

00721-cal-2001-priority document others.pdf

00721-cal-2001-priority document.pdf

721-CAL-2001-(17-11-2011)-CERTIFIED COPIES(OTHER COUNTRIES).pdf

721-CAL-2001-(17-11-2011)-CORRESPONDENCE.pdf

721-CAL-2001-(17-11-2011)-FORM-6.pdf

721-CAL-2001-(17-11-2011)-OTHERS.pdf

721-CAL-2001-(17-11-2011)-PA-CERTIFIED COPIES.pdf

721-CAL-2001-(25-04-2012)-CORRESPONDENCE.pdf

721-CAL-2001-(25-04-2012)-OTHERS.pdf

721-CAL-2001-(25-04-2012)-PA.pdf

721-cal-2001-abstract.pdf

721-CAL-2001-ASSIGNMENT.pdf

721-CAL-2001-CERTIFIED COPIES(OTHER COUNTRIES).pdf

721-cal-2001-claims.pdf

721-CAL-2001-CORRESPONDENCE 1.1.pdf

721-cal-2001-correspondence.pdf

721-cal-2001-description (complete).pdf

721-cal-2001-drawings.pdf

721-cal-2001-examination report.pdf

721-cal-2001-form 1.pdf

721-cal-2001-form 18.pdf

721-cal-2001-form 2.pdf

721-CAL-2001-FORM 3-1.1.pdf

721-cal-2001-form 3.pdf

721-CAL-2001-FORM 5-1.1.pdf

721-cal-2001-form 5.pdf

721-CAL-2001-FORM-27.pdf

721-cal-2001-gpa.pdf

721-cal-2001-letter patent.pdf

721-CAL-2001-PA.pdf

721-cal-2001-priority document.pdf

721-cal-2001-reply to examination report.pdf

721-cal-2001-specification.pdf

721-cal-2001-translated copy of priority document.pdf


Patent Number 200909
Indian Patent Application Number 721/CAL/2001
PG Journal Number N/A
Publication Date 19-Jan-2007
Grant Date 19-Jan-2007
Date of Filing 26-Dec-2001
Name of Patentee LG ELECTRONICS INC.
Applicant Address 20 YOIDO-DONG ,YONGDUNGPO-KU SEOUL
Inventors:
# Inventor's Name Inventor's Address
1 JIN MIN - HO 628 YONGDONG 3-KU SAPKYOEUP,YESAN-KUN CHOONG-CHUNGNAM -DO
PCT International Classification Number H 03 F1/26
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 87333/2000 2000-12-30 Republic of Korea