Title of Invention

A METHOF FOR PERFORMING TIMING CORRECTION ON AN INTEGRATED CIRCUIT DESIGN

Abstract

ABSTRACT OF THE DISCLOSURE A method is provided for performing timing correction on a hierarchical integrated circuit design comprising the steps of forming a hierarchical integrated circuit design, applying a hierarchical timing tool to the entire circuit hierarchy, applying a timing correction algorithm to improve timing of the design as measured by the hierarchical timing tool; and applying a parallel timing management tool to multiple applications of the hierarchical timing tool and the timing correction algorithm. Also claimed is an information handling system including means for implementing the parallel hierarchical timing correction method of the present invention.

Full Text

FIELD OF THE INVENTION The invention relates to computerized design of integrated circuits. More particularly, the invention relates to using a computer program to evaluate and implement changes in integrated circuit design based on timing correction synthesis algorithms. BACKGROUND OF THE INVENTION Integrated circuits grow ever more complex. In particular, very large scale integrated ("VLSI") chip designs grow more complicated every day. It is known in the art to use synthesis algorithms to mathematically evaluate electronic circuits with the help of a computer. In their most simple form, synthesis algorithms express a circuit in terms of a logical truth table and then apply heuristics to the truth table to determine if the circuit can be optimized for various different constraints, such as timing, area, power dissipation, or testability. Synthesis algorithms for the evaluation of chip designs thus are becoming more complex. Accordingly, the complexity of the heuristics (meaning, in general, guidelines or assumptions, based on observed generalities that are not necessarily mathematically precise or fully understood in a scientific sense) applied to the . problem of optimal chip design today are vastly more complicated than those available in preceding generations of synthesis tools. However, in the real world, we have neither infinite compute power, infinite time, nor reliable computer systems. We must still be able to turn around the synthesis of large chips rapidly to meet demanding product development schedules. The traditional way of dealing with these problems is through the introduction of hierarchy in the hardware language ("HDL"). If the pieces of the chip designs being synthesized stay roughly the same size, and it is simply the number of pieces that multiplies to increase the chip design size, then multiple parallel synthesis runs can be used to manage the latency problems of synthesizing the system. Technology independent optimization and technology mapping of large complex integrated circuits can be dealt with effectively in a parallel fashion. However, the timing-correction of a large hierarchical chip design is a difficult problem, which does not succumb to a parallel solution as easily. Unless strict latch-bounding constraints are imposed, it is difficult to resolve the results of timing a piece of a hierarchical chip design by itself (in-vitro) with the results of timing that piece in the context of the timing model of the entire design (in-vivo). The traditional solution to this problem, involves the generation of tuning constraints files of arbitrary complexity, specifying factors such as primary input arrival times, transition times, and equivalent drive circuits, primary output required arrival times, and loadings. However, there are always places where the in-vitro timing model using these timing constraints files diverge from the in-vivo. AM effective approaches to timing-correcting large hierarchical structures in parallel also must deal with the parallel-timing-correction convergence problem. Consider the following situation: a hierarchical design with two timing correctable entities. A signal emanates from the first design and is sunk by the second. At the beginning of the first timing-correction iteration, the first design drives the signal out with a high-power buffer. The second immediately buffers that signal and drops it to a number of sinks. This signal is also late, such that timing-correction tries to fix it. Timing correction is run on the first and the second designs in parallel. The timing correction job on the first design decides to eliminate the high-power buffer because the signal is loaded lightiy by the second design. Simultaneously, the timing correction job on the second design drops the input buffer because the drive strength of the output buffer driving the signal out of the first design is so high. Both jobs measure that the timing characteristics of the signal in question have improved, where in actuality, when the hierarchy is re-assembled, no progress has been made, and indeed the tuning may have gotten worse. If timing-correction is attempted in parallel another time, the reverse happens, and both the input and the output are re-buffered, putting the design back in its original state. Both the divergence between the timing as measured in the in-vivo versus the in-vitro model, and the parallel-timing-correction convergence problem must be managed appropriately in an effective solution to parallel timing correction of large hierarchical structures. SUMMARY OF THE INVENTION An object of the invention is to provide for a timing-correction means that can accurately and efficiently timing correct a hierarchical chip design. The invention provides a method is provided for performing timing correction on a hierarchical integrated circuit design comprising the steps of forming a hierarchical integrated circuit design, applying a hierarchical timing tool to the entire circuit hierarchy, applying a timing correction algorithm to improve timing of the design as measured by the hierarchical timing tool; and applying a parallel timing management tool to multiple applications of the hierarchical timing tool and the timing correction algorithm. Also the invention relates to an information handling system comprising means for implementing the parallel hierarchical timing correction method of the present invention. Accordingly the present invention provides a method for performing timing correction on an integrated circuit design comprising the steps of creating a hierarchical integrated circuit design; applying a hierarchical timing tool to said integrated circuit design; applying a parallel timing management tool to a design hierarchy to manage multiple appUcations of said hierarchical timing tool to different pieces of said design hierarchy; and making timing corrections in said design hierarchy in accordance with the results of the application of said hierarchical timing tool and said parallel timing management tool. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT The present invention is an effective solution to the timing-correction-of-large-hierachical-stmctuies problem. The invention is called parallel-hierarchical-timing-correction. There are two separate aspects of this solution: HIERARCHICAL TIMING TOOL: The &st aspect of the solution works on a hierarchical structure and does not rely on the second aspect of the solution, known as the PARALLEL TIMING MANAGEMENT TOOL. (The solution will work, albeit slowly, if only the HIERARCHICAL TIMING TOOL is implemented.) PARALLEL TIMING MANAGEMENT TOOL: The second aspect of the solution uses the PARALLEL TIMING MANAGEMENT TOOL to improve the latency of the solution. The PARALLEL TIMING MANAGEMENT TOOL does not rely on the HIERARCHICAL TIMING TOOL. (A PARALLEL TEMESTG MANAGEMENT TOOL solution can be implemented without a HIERARCHICAL TIMING TOOL solution, but it does not make too much sense to do this.) This solution assumes underlying tools that provide three services: 1. Close integration of synthesis and timing: Without an accurate timing model, accurate timing correction cannot be accomplished. 2. Incremental timing capability: Resolving timing on a large design can take many minutes (45 minutes is not unusual). Accurate timing correction would be prohibitive if every timing correction decision IPAUS:2741.1 29094-00003 entailed this cost. However, with incremental timing, synthesis can try thousands of potential timing-improvements a second on even the largest of designs, and receive accurate feedback about the efficacy of the changes from the timing subsystem. 3. Hierarchical Timing Tool capability: The timing-tool must be able to time the same hierarchical design being timing-corrected. The simplest form of the Hierarchical Timing Tool of the solution works as follows: The design hierarchy is loaded into the timing/timing-correction systerp ('the system'), and the hierarchical timing-model is initialized. Theh, for each,element in the hierarchy, timing-correction is applied. The hierarchical nature of the timing subsystem keeps the timing-model across the entire hierarchy consistent. If the critical path which spans multiple hierarchy boundaries is improved in one hierarchy piece, we see this improvement reflected across the entire hierarchy. In essence, hierarchical tuning is maintaining aU the boundary constraints within the hierarchy in real time with no loss of accuracy. This simple approach suffers from a number of problems. First, in this simple approach, timing correction is applied only once to each element in the hierarchy. If only sunple heuristics are applied in the process of timing-correction, then the resulting netlist will not have been optimized fully. However, if the most powerful heuristics are applied in the process of timing-correction, the resulting netlist wUl again be non-optimal. The pieces of the hierarchy timing-corrected initially will have been timing-corrected incorrecfly due to gross problems in the other, un-timing correct portions of the netlist. This difficulty is easy to fix, by modifying the simple routine to visit the entire hierarchy more than once, adjusting the amount and power of the heurisitcs applied by the number of times that the entire hierarchy has been visited. The first time around the hierarchy, timing-cortection is applied requesting a small amount of work, fixing gross >lgATIS-77 timing problems. The second time around, mid-levels of work are requested, etc. It is not until all the 'easy' cross-hierarchy timing-problems have been solved that the most advanced heuristics are chosen. The second problem associated with this simplistic approach is that too much timing-correction is applied. Not all elements in the hierarchy should have attention paid to them. In general, the critical path is contained in a few of the hierarchical elements, and the rest of the design warrants only a cursory pass of timing-correction to eliminate gross problems. The solution to this is to choose the elements in the hierarchy based on some measure of their need for timing correction. The heuristic that the preferred embodiment of the invention implements to solve this problem is as follows. For each synthesizable piece in the design hierarchy, determine the worst slack in the piece, the sum of the worst slack of the 32 worst points, and the number of times timing-correction has been applied to that piece. Build a list of these pieces, major order the worst slack, minor order the sum of the worst slacks. Truncate the list to the worst-path (all the hierarchy pieces on the worst path will have the same worst slack, and will appear on the top of the list), or 5 pieces, whichever is longer. Choose the piece from the truncated list that has had the least amount of timing-correction applied, and apply timing-correction based'-on the number of previous timing-correction passes to that piece. The invention should in no way be limited to this heuristic. The important point is rather that for maximum effectiveness, the Hierarchical Timing Tool of the invention should include a means for focusing particular attention on those areas of the chip design most in need of timing correction. The third problem with the simple approach is that it is sequential. The solution to this problem is to extend the system to manage multiple peer timing-correction processes running in parallel. This is the second aspect of the invention, called the Parallel Timing Management Tool. Each process is in an endless loop of the following steps: Choose the next hierarchical piece to timing-correct, insuring that piece is not being timing-corrected by any of the other processes that are running in parallel; Broadcast the name of the piece, such that all other processes are aware that it is being timing-corrected; Timing-correct the chosen piece; Broadcast resulting timing-corrected net list for the chosen piece to all other processes; Update timing model with new netlists from other processes; Re-initialize the timing subsystem; Go to top of loop. The parallel timing-correction convergence problem is managed by controlling the number of jobs running simultaneously. When a raw (not timing-corrected) model is loaded into the system, the gross nature of the problems that get corrected far outweigh the subtle boundary-oriented convergence problems, and the system can tolerate a large number of processes running simultaneously. As time progresses, and the timing corrections being introduced become more specific, the susceptibility of those fixes to convergence problems grows. However, the probability of the system hitting both in input and output sides of a hierarchical boundary on the critical path diminish as the number of processes running diminishes. The foregoing description of the preferred embodiment of the invention describes the invention. However, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention. Accordingly, the invention is limited only by the following claims and their equivalents. We claim: 1. A method for performing timing correction on an integrated circuit design comprising the steps of: creating a hierarchical integrated circuit design; applying a hierarchical timing tool to said integrated circuit design; applying a parallel timing management tool to a design hierarchy to manage multiple applications of said hierarchical timing tool to different pieces of said design hierarchy; and making timing corrections in said design hierarchy in accordance with the results of the application of said hierarchical timing tool and said parallel timing management tool. 2. The method of claim 1, wherein the step of applying said hierarchical timing tool comprises: selecting aspects of said design hierarchy most in need of timing correction to provide selected aspects and applying said hierarchical timing tool to said selected aspects. 3. A method for performing timing correction on an integrated circuit design comprising the steps of: creating a hierarchical integrated circuit design; applying a hierarchical timing tool to said integrated circuit design; applying a parallel timing management tool to a design hierarchy to manage multiple applications of said hierarchical timing tool to different pieces of said design hierarchy; and making timing corrections in said design hierarchy in accordance with the results of the application of said hierarchical timing tool and said parallel timing management tool, wherein the step of applying said hierarchical timing tool comprises: a. selecting aspects of said design hierarchy most in need of timing correction to provide selected aspects and applying said hierarchical timing tool to said selected aspects, b. for each piece of said design hierarchy, determining a specified number of worst slack points in said piece; c. for each piece, determining a sum of a specified number of worst slack points in said piece; d. tracking the number of times said hierarchical timing tool has been applied to each piece; e. building a list of said pieces in descending order by worst slack in each of said pieces and in ascending order by the sum of the worst slack points in said piece; f truncating said list at a specified number of pieces; g. choosing a chosen piece from said pieces from the truncated list that has had the smallest number of applications of said hierarchical timing tool; and h. applying hierarchical timing correction steps to said chosen piece. 4. A method for performing timing correction on an integrated circuit design comprising the steps of: creating a hierarchical integrated circuit design; applying a hierarchical timing tool to said integrated circuit design; applying a parallel timing management tool to a design hierarchy to manage multiple applications of said hierarchical timing tool to different pieces of said design hierarchy; and making timing corrections in said design hierarchy in accordance with the results of the appHcation of said hierarchical timing tool and said parallel timing management tool, choosing a chosen piece from said pieces to which hierarchical timing correction steps should be applied; broadcasting a name of said chosen piece such that all other processes are aware that said chosen piece is being timing corrected; applying said hierarchical timing correction steps to said chosen piece; and updating a list of said pieces. 5. A method for performing timing correction on an integrated circuit design, substantially as herein described and exemplified.

Documents:

784-mas-1997 abstract duplicate.pdf

784-mas-1997 abstract.pdf

784-mas-1997 assignment.pdf

784-mas-1997 claims duplicate.pdf

784-mas-1997 claims.pdf

784-mas-1997 correspondence others.pdf

784-mas-1997 correspondence po.pdf

784-mas-1997 description (complete) duplicate.pdf

784-mas-1997 description (complete).pdf

784-mas-1997 form-19.pdf

784-mas-1997 form-2.pdf

784-mas-1997 form-26.pdf

784-mas-1997 form-4.pdf

784-mas-1997 form-6.pdf

784-mas-1997 petition.pdf