Title of Invention

METHOD AND APPARATUS FOR SUSPENDING AND RESUMING OPERATION OF A COMPUTER SYSTEM

Abstract

ABSTRACT OF THE DISCLOSURE METHOD AND APPARATUS FOR SUSPENDING AND RESUMING OPERATION OF A COMPUTER SYSTEM A method and apparatus for saving the state of computer systems components provides a resume capability for battery operated computer systems after integrated circuits within the computer system have been completely powered-down The state is read from the microprocessor and various peripheral components and stored in non¬volatile storage until computer system operation is resumed.

Full Text

The present invention relates generally to computing systems, and more specifically to a method and apparatus for suspending and resuming operation of a computer system by saving the state of the computer system prior to removing power from the microprocessor and peripheral components. 2. Description of the Related Art: Present-day computer systems provide power management to conserve energy and reduce heat generated by a computer system when system activity is not required. Notebook computer systems and personal digital assistants (PDAs) also use power management to conserve battery power. A computer system may be set to a totally shutdown state, or may be placed in various modes known as "suspend" or "resume", among other terms of art used to describe an operating mode in which a portion of the computer system is active waiting on a stimulus to resume full system operation. Examples of stimuli that can be detected for resuming operations are mouse movement, modem dial-in, and local area network (LAN) activity. When a user is operating a computer system, the "suspend" function is critical to quick operation. It is not desirable to have to boot or reconfigure the computer system from a completely shut down state when the computer system is conserving energy for short intervals while there is no user input. However, the suspend function does not typically remove power from the microprocessor controlling the computer system. Large microprocessors and other integrated circuits as used in present-day computer systems have tens of millions of transistors. The leakage current while the microprocessor and other integrated circuits are in a completely static state may be too great to achieve long battery life or satisfy energy management policies. System designers trade off operating power versus leakage current when selecting devices for implementing processors and other systems components. For low operating power, a low supply voltage and consequently a low threshold voltage for the logic is desired. However, low threshold logic yields high leakage current while the devices are in a quiescent state. To avoid high leakage current, it is possible to remove power from the electronics in a computer system. However, when power is removed the state of the microprocessor and other integrated circuits will be lost. In some circumstances, software could be used to extract and store the state prior to power down; however, for peripheral controllers such as LAN controllers and storage device controllers, the state of the integrated circuits is often inaccessible from the operating system software. This makes it impossible to save the state or configuration of the hardware, requiring either the hardware to remain powered in the static state or the operating system to shut down the system and restart it later. Therefore, it would be desirable to provide a method and apparatus for suspending and resuming operation of a computer system by saving the state of computer system components so that power may be removed from the computer system components without requiring a reboot of the computer system to resume operation. SUMMARY OF THE INVENTION The objectives of suspending and resuming a computer system by saving the state of computer system components so that power may be removed from the computer system components is achieved in a method and system for suspending and resuming operation of a computer system that saves the state of internal registers of one or more components within the computer system. The state is read using scanning latches in the computer system component. The scan registers can be internally accessed via the internal scan chains or externally by using a serial test port interface or a boundary scan interface. The state is then saved in non-volatile storage, and power is removed from the computer system component. Upon receiving a resume signal, the power is restored to the computer system component, the saved state is read from the non¬volatile storage, and the state is written back to the computer system component. The state is written back internally via the scan chains or externally using the serial test port interface or the boundary scan interface. Execution of the computer system then resumes with the computer system component in the previously saved state. The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description. Accordingly, the present invention provides a method for suspending and resuming operation of a computer system, said method comprising in response to receiving a suspend indication, scanning states of internal registers of a component integrated circuit within said computer system to read data corresponding to said states from scanning registers; storing said states in non¬volatile storage; and removing power from said component integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein like reference numerals indicate like components, and: Figure lA is a block diagram of a computer system component in which a preferred embodiment of the present invention may be practiced; Figure IB is a schematic diagram of scan registers within the computer system component of Figure lA; Figure 2 is a block diagram of a computer system in accordance with a preferred embodiment of the present invention; Figure 3 is a flowchart depicting the operation of an operating system in accordance with a preferred embodiment of the present invention; Figure 4 is a flowchart depicting the operation of power control logic in accordance with a preferred . embodiment of the present invention; and Figure 5 is a block diagram of a computer system in accordance with alternative embodiments of the present invention. DESCRIPTION OF MH ILLUSTRATIVE EMBODIMENT With reference now to the figures, and in particular with reference to Figure lA, there is depicted a block diagram of a computer system component 10 in which a preferred embodiment of the present invention may be practiced. Computer system component 10 may be a processor core, a computer system application specific integrated circuit (ASIC), or a peripheral controller. System component 10 contains functional logic blocks llA, IIB, and IIC that perform functions in accordance with the operation of a computer system. Level-sensitive scan design (LSSD) scan chains 12 are provided to read and write the states of internal registers within functional logic blocks llA, IIB, and IIC. LSSD scan chains 12 are typically provided for test and verification purposes. Access to all of the state holding elements within system component 10 allows both design verification and production line testing to be performed prior to use in a computer system. Scan chain architectures that may be used with the techniques of the present invention are described in U.S. patent 5,920,575 entitled "VLSI Test Circuit Apparatus and Method," which is incorporated herein by reference, but other boundary scan and test port circuits and topologies may be used without departing from the spirit and scope of the invention. In addition to LSSD scan chains 12, a Joint Test Action Group (JTAG) interface 13 is integrated within system component 10. JTAG interface 13 provides a connection 15 through which an external tester may access internal registers within system component 10, allowing the state of nearly all internal latches to be read or written, typically for the purpose of testing system component 10. The details of JTAG interface 13 are defined by IEEE (Institute of Electrical and Electronics Engineers) standard 1149.1 - IEEE Standard Test Access Port and Boundary Scan Architecture, as well as the 1994 Supplement to the 1149.1 specification. The interfaces used are not restricted to JTAG type interfaces, but it is convenient to use the JTAG hardware layer and protocols substantially compatible with the JTAG standard interface in order to provide compatibility with test equipment commonly available at present. The present invention uses state information from functional logic blocks llA, IIB, and IIC in a novel way to store the state of system component 10 prior to suspending operation of a computer system and restore the state prior to resuming operation. The state information read from and written to LSSD scan chains 12 can be accessed by many different means. LSSD scan chains 12 can be accessed directly within system component 10, via special commands through JTAG interface 13, or via boundary scan interface 14 by putting system component 10 in scan mode. The scan mode can be initiated and terminated via commands provided through JTAG interface 13 or via external pin connections forming part of boundary scan interface 14. LSSD architecture is advantageous for implementing the techniques of the present invention, as it provides access to the state of all internal latches. Additionally, LSSD structures are already present in LSSD-testable designs, and therefore the invention does not require new circuit design techniques or modification to circuits that have been designed incorporating LSSD scan chains. An alternative approach, referred to as "bubble scan" adds another low-leakage state-saving device to each LSSD latch. This state-saving device is used to hold the state of the latch during low-power intervals (such as suspend mode). In contrast to the present invention, power must be maintained to the components containing state-saving latches. Additionally, the "bubble scan" approach requires new circuit designs and more circuit area for realization. Semiconductor manufacturers have large investments in reusable circuit libraries and entire system designs presently incorporate standard LSSD structures. The present invention can leverage these investments by addition of simple control logic and control software to an existing architecture. Referring now to Figure IB, the structure of scan cells within LSSD scan chains 12 of Figure lA is depicted. Registers 16 have system data inputs 18 for loading logic values from functional logic blocks llA, IIB, and IIC and system data outputs 17 for setting logic values within functional logic blocks llA, IIB, and IIC. Registers 16 are serially connected in a chain, with a scan data input for loading logic values at the top of each chain, and a scan data output at the end of each chain. The chain inputs and outputs are accessible internally, as well as via boundary scan interface 14 and JTAG interface 15. Scan clocks provide control of shifting data within LSSD scan chains 12, and the system clock provides the high frequency clock for normal system operation. Referring now to Figure 2, a computer system in accordance with a preferred embodiment of the invention is shown. Computer system core 20 is a large-scale building block for the computer system. External devices 42, interfaced via a bus 43, complete the functional portion of the computer system. External devices include memory, storage devices, graphics devices, human input devices, etc. A non-volatile storage 40 located external to computer system core 20, is used to store state information for the suspend/resume functionality of the present invention. A controllable power supply comprising an NMOS transistor 41 is also included within the computer system, for controlling the primary power to the blocks within computer system core 20. A low-current standby power supply connection 44 is provided for retention of state information in portions of computer system core 20, for standby power provided to power control logic 24, and to other computer system components that cannot be completely powered down. Within computer system core 20, processor core 21 provides execution of program instructions and manipulation of data values. Integrated peripherals 23 such as serial ports, direct memory access (DMA) controllers, etc., provide computer system functions. External bus interface 29 provides bus 43 connection to external devices 42 through I/O blocks 45. Processor core 21, I/O blocks 45, integrated peripherals 23 and external bus interface 29 all contain LSSD scan chain registers. Scan data outputs 32 from each of the chains are coupled to a scan multiplexer 27 to allow selection of an individual scan chain output 34 to power control processor 24. Power control logic 24 can read the scan chain registers by selecting a scan chain via multiplexer control signal 33 and controlling the acquisition and transfer of state information from the blocks containing scan chains via a control bus interface 38. Once power control logic 24 has retrieved the state of the computer system core 20 by reading the scan chains, the data is stored in non-volatile internal storage 26, which may either be powered via standby power 44 or may be implemented in a technology that does not require power to retain its state, such as electrically-erasable read-only memory. Non-volatile internal storage 26 may also be powered by the main computer system core power provided through controllable power supply 41, if the state information is first transferred to non-volatile external storage 40 before controllable power supply 24 disables power to the computer system core 20. I/O blocks 45 can be loaded with appropriate values before controllable power supply 41 disables power. This will be required if some of external devices 42 cannot be powered down. The state of external connections to computer system core 20 must be controlled to avoid putting external devices 42 in a high leakage state, generating false bus cycles, or potentially causing damage to external devices 42. Power control logic 24, which may be a processor or hardwired logic block, begins the suspend sequence for computer system core 20 by receiving a command from processor core 21, via control bus interface 38. Alternatively, other schemes for creating a suspend request may be implemented, such as a single control line coupled between power control logic 24 and processor core 21. Power control logic 24 may suspend the clocks to processor core 21 and integrated peripherals 23 by controlling clock control 22. This freezes the operation of computer system core, with the exception of power control logic 24 and associated components. The scan chain data is read from the various blocks' and then stored in non-volatile internal storage 26. Next, power control logic 24 may remove primary power from computer system core 20 via controllable power supply 41. Within the sequencing of suspend or shutdown events, non-volatile internal storage 26 or non-volatile external storage 40 may be used selectively to provide differing levels of energy savings. For example, for the initial portion of the suspend operation (which could be a very long time period, perhaps months depending on the leakage values), it may be preferable to retain the state within non-volatile internal storage 26 and maintain some level of power supply current required by computer system core 20. After a time period has elapsed determined by a time 46 within power control logic 24, a higher level of energy saving may be initiated by writing the state of computer system core 20 to non-volatile external storage 40 and completely removing power from computer system core 20. Timer 46, may also be implemented in program instructions if power control logic comprises a microprocessor, or as a block external to power control logic 24 within computer system core 20, or other suitable architecture for causing power control logic 24 to initiate the transfer of data to non-volatile external storage 40. Multiple transistors within programmable power supply 41, with multiple power supply connections to computer system core 20 may be used to accomplish the different levels of energy savings, or the energy savings may be due to clock control 22 shutting off clocks to the internal blocks. An error detection and correction block 30 may provide higher reliability for saving and retrieving state information, or may incorporate encoding or compression to reduce the amount of energy and time required to store and retrieve state information. The error correction and detection may be necessary in a given configuration, as some non-volatile storage devices have a limited number of write cycles before failure. The use of non-volatile internal storage 26 and non¬volatile external storage 40 is tailored to the system that is implemented. For example, if computer system core 20 is used in a system which is in a suspended state most of the time, non-volatile external storage 40 might be used exclusively. However, if the system is activated very frequently, non-volatile internal storage 26 may be used exclusively. For a system that uses both types of non-volatile storage, the timing of a transfer of data from non-volatile internal storage 26 to non-volatile external storage 40 is a function of the power requirements of non-volatile internal storage 26 versus non-volatile external storage 40. Reset control 25 is interfaced to power control logic 24 to provide reset and/or resume signaling. Once a resume is signaled, power control processor can restore primary power by enabling controllable power supply 41, and retrieve the state from either non-volatile internal storage 26 or non-volatile external storage 40. The state information is written to the various functional blocks via scan chain inputs 31. A particular scan chain input is selected by scan demultiplexer 28 to receive a scan data output 35 from power control logic 24. A scan demultiplexer control 36 is provided for this purpose. Control bus interface 38 is used to control the loading of state data into processor core 21, integrated peripherals 23, and external bus interface 29. Once the state data is loaded, clock control 22 can be signaled to re-enable clocks to processor core 21 and integrated peripherals 23. The ability to read and write the state of the internal latches of computer system core 20 makes it possible to store and retrieve this information. While originally provided for testing purposes, the need for sophisticated energy management makes it desirable to use LSSD scan strings and LSSD scannable latches for state retrieval and restoration. This will minimize the time required to place the computer system in a state in which power may be removed from the principal components, and also reduce the associated time required to restore the operating state of the computer system (e.g., not rebooting or reconfiguring the system after powering off), and provide a complete reconstruction of the state of the machine prior to shutdown. A complete restart of a computer system subsequent to removing power from the processors and peripherals has been necessary in the past because the state of the machine may not be completely accessible to the software. The present invention makes it possible to restore the state of the machine directly via the scan interfaces. The operating system need only flush or save non-scannable memory arrays such as caches and translation look-aside buffers, etc. in addition to storing the state of the component integrated circuits. After the non-scannable memory images have been restored, power can be restored to the component integrated circuits and the stored state can be restored via the scan interface. For example of the complete state storage and recovery of the present invention, a disc access may have been started in a particular storage device, but a seek to a particular sector may not have been completed. While the disc controller is maintaining the command and waiting for the seek to complete, the system cannot be shut down without changing the state of the machine (canceling the command). Also, the interface to a storage device is generally managed by a storage device driver, which may not provide a power-down interface to the operating system for providing an orderly power-down/power-up sequence. The improvements of the present invention also apply to network interface operation. The network interface may have information written to configure protocols, IP addresses, etc., and this information is maintained by a device driver or an application running within the computer system. In order to remove power from the network interface and subsequently restore power, upon restoration all of the network interface's state must be restored. It may not be possible for the network device driver to completely read and write the state, making it necessary to restart the device driver or application managing the network interface. Referring now to Figure 3, a flowchart depicting operation of an operating system in accordance with a preferred embodiment of the method of the present invention is shown. When a system suspend request is received (decision 61), which may be triggered by a user button or a software command, the scheduler (task time-slice manager or priority manager) ceases scheduling tasks and allocating execution to tasks and processes and interrupts are disabled (step 63). At this point, execution is single-threaded and cannot be interrupted. Next, any cache memory and translation look-aside buffers (TLBs) are flushed to external storage. This storage may be memory that is still powered, or a magnetic hard disk file. After cache memory is flushed, power control logic 24 is signaled to shutdown the system (step 65). The operating system then stalls until the clocks are halted and power is removed from the components that are powered down (step 66). Power control logic 24 is responsible for saving the state of the components that are powered down, and restoring them prior to resuming operation so that when power is restored and clocks are reapplied the state of the machine is restored. The operating system then resumes operation from the state prior to suspend, with the suspend request removed (step 67). Referring now to Figure 4, a flowchart depicting operation of a power control logic block (such as power control logic 24 of Figure 2) in accordance with a preferred embodiment of the method of the present invention is shown. While a shutdown request has not been received (decision 70), power control logic 24 remains in an idle state or performs other tasks (step 71). When a shutdown request is received, power control logic 24 stops the system clocks (step 72). Next, the state is read from system devices, including the processor via scan ports in the integrated circuits (step 73). The state of all the devices is transferred to non-volatile storage (step 74), the scan clocks are stopped, and power is removed from computer system core 20 (step 75). Power control logic 24 then enters an idle state (step 76) until a resume indication is received from a user button, a timer or other signaling mechanism. When a resume indication is received (decision 77), power is restored to the system devices and scan clocks are reenabled (step 78), the previously-saved state is read from non-volatile storage (step 79), and the state is written to the system devices via the scan ports (step 80). Then, system clocks are restored (step 81), allowing operation to proceed from where it was halted. Referring now to Figrure 5, a computer system in accordance with alternative embodiments of the invention is depicted. In these embodiments, the components have test interfaces and/or boundary scan interfaces, but are not specially tailored to internally incorporate the state storage and recovery of the present invention. The test interfaces and/or boundary scan interfaces are used externally to provide a mechanism whereby the state can be read from and written to the components. Central computer unit 100 is coupled to memory 110 for storing program instructions and data, as well as to peripheral devices 111. Peripheral devices 111 may include video controllers, network interfaces, input devices, printer interfaces, storage device interfaces, as well as other devices that provide useful connections for central computer unit 100. The state of peripheral devices 111, may also be saved via JTAG connections 114 to shutdown/restart control processor 113 or boundary scan connections 112. Since JTAG and boundary scan implementations are pervasive in large-scale circuits used today, many off-the-shelf peripheral device components may interface in the manner depicted in Figure 5 without modification. Central computer unit 100 contains a processor 101 for executing program instructions and a cache memory 102 for holding instructions and data values. In accordance with high density integration available in present integrated circuits, central computer unit 100 also contains peripheral and system support components to implement a large portion of the computer system. A memory controller 105 for managing the memory subsystem of the computer, a direct memory access (DMA) controller 104, and a bus bridge 103 provide system support for managing memory and input/output transfers from central computer unit 100. A UART 106 provides serial communications, and a network interface 107 provides network communications between central computer unit 100 and connected devices. In addition to functional blocks associated with the computer system operation, a Joint Test Action Group (JTAG) interface 108 is integrated within central computer unit 100. The JTAG interface 108 provides a port through which an external tester may access internal registers within central computer unit 100, allowing the state of nearly all internal latches to be read or written, typically for the purpose of testing the central computer unit integrated circuit prior to use or installation within a computer system. The interfaces used are not restricted to JTAG type interfaces, but it is convenient to use the JTAG hardware layer and protocols substantially compatible with the JTAG standard interface in order to provide compatibility with test equipment commonly available at present. In the computer system of Figure 5, JTAG interface 108 is coupled via JTAG connections 114 to power control logic 113, which may be a processor or hard-wired logic block, providing a mechanism for power control logic 113 to read or write the state of central computer unit 100. In accordance with a first alternative embodiment of the invention, the state of central computer unit 100 is saved prior to shutdown and restored prior to restart by special command sequences issued by power control logic 113 to JTAG interface 108, so that operation of the computer system may be frozen within a shutdown routine without requiring a reboot of the computer system in order to resume operation. A second alternative embodiment of the invention may also be practiced within the computer system of Figure 5. In addition to JTAG connections 114, power control logic 113 is coupled to central computer unit 100 via boundary scan connections 112. When a special test mode is initiated, which can be through external pins on central computer unit 100 or by a special command issued through JTAG interface 108, central computer unit 100 may be placed in "scan" mode, in which a subset of the pin connections on central computer unit 100 become boundary scan test pins. Through boundary scan connections 112 the state of central computer unit 100 may be read more quickly that, data can be read through JTAG interface 108, but at the cost of a more complex circuit. In addition to its uses as a suspend/resume mechanism for computer systems and personal digital assisitants (PDAs), the present invention may be used to provide a "hot spare" capability for servers and other critical computer systems incorporating redundant components, or components that might be brought on-line on an "as needed" basis, such as LAN switches or modem banks. At system initialization, the state of the components in the "hot spare" are initialized to a desired state, the state is then read into non-volatile storage, and the power is removed from the components. When the "hot spare" is needed, the power can be restored and the state written back to the components within the "hot spare." The "hot spare," initialized to the desired state, can then be used within the computer system. Although the invention has been described with reference to specific embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that such modifications can be made without departing from the spirit or scope of the present invention as defined in the appended claims. WE CLAIM : 1. A method for suspending and resuming operation of a computer system, said method comprising in response to receiving a suspend indication scanning states of internal registers of a component integrated circuit within said computer system to read data corresponding to said states from scanning registers; storing said states in non-volatile storage; and removing power from said component integrated circuit. 2. The method according to claim 1, comprising the steps of : restoring power to said component integrated circuit in response to a resume indication; reading said states from said non-volatile storage; and restoring said states within said component integrated circuit by writing data corresponding to said state to said scanning registers. 3. The method according to claim 2, comprising the step of prior to saving said states, halting system clock signals within said component integrated circuit; and after restoring power to said component integrated circuit, starting system clock signals within said component integrated circuit. 4. The method according to claim 2, wherein said non-volatile storage is located within said component integrated circuit, and wherein said storing said states in said non-volatile storage moves data corresponding to said states within said component integrated circuit, and wherein said restoring said states restores said states from within said component integrated circuit. 5. The method according to claim 4, wherein said non-volatile storage comprises random access memory coupled to a standby power supply, and wherein said removing power from said component integrated circuit does not remove power from said non-volatile storage. 6. The method according to claim 5, comprising the step of waiting a predetermined time subsequent to scanning said states; and in response to said predetermined time elapsing, transferring said scanned states to a second non-volatile storage external to said component integrated circuit. 7. The method according to claim 4, wherein said non-volatile storage is electrically erasable read-only memory, and wherein storing said states writes said states to said electrically erasable read-only memory. 8. The method according to claim 2, wherein said non-volatile storage is external to said component integrated circuit, and wherein said storing and reading steps transfer said states through an interface between said internal registers and said external storage. 9. The method according to claim 2, comprising the step of waiting a predetermined time subsequent to receiving said suspend indication, and wherein storing said states is performed in response to said predetermined time elapsing. 10. The method according to claim 2, wherein said scanning said states reads said states through a serial test port interface. 11. The method according to claim 2, wherein said scanning said state reads said state through boundary scan registers, and wherein said method further comprises putting said component integrated circuit in scan mode in response to receiving said suspend indication. 12. The method according to claim 2, wherein said computer system comprises an active and a standby unit coupled to a common bus, wherein said component integrated circuit is located within said standby unit, wherein said scanning said states, storing said states, and removing power are performed at system initialization; and said steps of restoring power, reading said states, and restoring said states are performed in response to an indication for said standby unit to become active. 13. A computer system, comprising: a component integrated circuit, having internal functional registers accessible via scanning registers; a non¬volatile storage coupled to said component integrated circuit, for storing states of said component integrated circuit in response to a suspend indication, wherein said states are read from said component integrated circuit via said scanning registers; and a controllable power supply coupled to said component integrated circuit, for powering said component integrated, circuit when said component integrated circuit is operating and for removing power subsequent to said states being stored in said non-volatile storage. 14. The computer system according to claim 13, comprising a clock control circuit for gating off system clock signals within said component integrated circuit so that the condition of said states is frozen. 15. The computer system according to claim 13, wherein said non-volatile storage is located within said component integrated circuit. 16. The computer system according to claim 15, wherein said non-volatile storage comprises random access memory coupled to a standby power supply, and wherein said standby power supply continues to supply power to said random access memory after said controllable power supply has removed power from said component integrated circuit. 17. The computer system according to claim 13, comprising: a second non¬volatile storage coupled to said component integrated circuit for storing said states; and a timer for determining when a predetermined time has elapsed, and wherein said states are written to said second non-volatile storage prior to said controllable power supply removing power from said component integrated circuit. 18. The computer system according to claim 13, wherein said non-volatile storage is electrically erasable read-only memory. 19. The computer system according to claim 13, wherein said non-volatile storage is external to said component integrated circuit, wherein said computer system further comprises an interface between said internal registers and said external storage, and wherein said states are transferred through said interface. 20. The computer system according to claim 19, wherein said interface is a serial test port interface. 21. The computer system according to claim 20, wherein said serial test port interface comprises a test port in accordance with the Joint Test Action Group (JTAG) specification, and wherein said states are transferred by issuing special JTAG commands. 22. The computer system according to claim 13, wherein said component integrated circuit includes boundary scan registers, and wherein said states are read by putting said component integrated circuit in scan mode. 23. The computer system of claim 13, comprising: a bus for coupling processing and peripheral components; an active component coupled to said bus; and a standby component, containing said component integrated circuit, coupled to said bus, and wherein said states are saved in said non¬volatile storage at system initialization and said state is retrieved in response to an indication for said standby component to become active. 24. The computer system of claim 13, comprising a power control logic processor for reading states of said component integrated circuit. 25. The computer system of claim 24, wherein said power control logic processor controls said controllable power supply to control power to said component integrated circuit. 26. The computer system of claim 24, comprising a clock control circuit coupled to said power control logic for gating off system clock signals within said component integrated circuit in response to said shutdown processor. 27. The computer system of claim 24, wherein said shutdown processor is located within said component integrated circuit, and wherein said power control logic is coupled to an alternate power supply so that power is maintained to said power control logic when said controllable power supply removes power from said component integrated circuit. 28. A component integrated circuit for use in a computer system comprising: internal registers accessible via scan registers; and internal non-volatile storage for storing a state of said internal registers in response to a suspend indication. 29. The component integrated circuit of claim 28, wherein said internal non¬ volatile storage comprises electrically erasable read-only memory. 30. The component integrated circuit of claim 28, wherein said non-volatile storage comprises random access memory coupled to a standby power supply input for supplying power to said random access memory after power has been removed from main power supply pins. 31. The component integrated circuit in accordance with claim 28, comprising a power control logic within said component integrated circuit for transferring said state to said non-volatile storage. 32. The component integrated circuit in accordance with claim 28, comprising clock control logic for gating off clock signals to functional logic after said state has been saved. 33. A method for suspending and resuming operation of a computer system substantially as herein described with reference to the accompanying drawings.

Documents:

0803-mas-2001 abstract-duplicate.pdf

0803-mas-2001 abstract.pdf

0803-mas-2001 claims-duplicate.pdf

0803-mas-2001 claims.pdf

0803-mas-2001 correspondence-others.pdf

0803-mas-2001 correspondence-po.pdf

0803-mas-2001 description (complete)-duplicate.pdf

0803-mas-2001 description (complete).pdf

0803-mas-2001 drawings-duplicate.pdf

0803-mas-2001 drawings.pdf

0803-mas-2001 form-1.pdf

0803-mas-2001 form-19.pdf

0803-mas-2001 form-26.pdf

0803-mas-2001 form-3.pdf

0803-mas-2001 form-5.pdf

0803-mas-2001 petition.pdf