Title of Invention

"AN APPARATUS AND METHOD FOR PROCESSING DATA BY GENERATING ERROR CORRECTING PRODUCT CODE BLOCK"

Abstract This invention relates to a method of processing data by generating an error correcting product code block comprises: a first step of processing digital data on a byte by byte basis to configure an information data block out of (MxN) bytes of N rows x N columns, arranging data on a byte by byte basis in said information data block and arranging data in each row sequentially from the 0th to the (N-l)-th column according to the sequence of data transmission and sequentially from the 0th to the (M-l)-th row according to the sequence of data transmission; a second step of arranging a matrix block of (KxM) rows x N columns by using K information data blocks arranged sequentially to the sequence of data transmission; a third step of adding an error correcting check word of K bytes to each columns of (KxM) bytes of the matrix block to turn of an N rows into a read-Solomon code word C2 of (Kx(M+l)) bytes; and a fourth step of adding an error correcting check word of a bytes to each roe of N bytes to turn each of the (Kx(M+1)) rows into a Read-Solomon code word CI of (N+P) bytes; said error correcting product code block being a Read-Solomon error correcting product code block of (Kx(M+l)x(N+P) bytes having an information section of K information data blocks of (KxMxN) bytes, the sum of (MxN) bytes of an information data block and the average number of bytes of a check word added thereto being held to a constant value of (M+l)x(N+P) bytes.
Full Text This invention relates to a method of configuring an error correcting product code block adapted for use for digital data recording/transmission and, more particularly, it relates to a method of processing data for generating an error correcting product code block devised set as not to change the level of redundancy after the -error correcting ability is modified.) The present irivention also relates to a method of processing data for recording such data on a recording medium as well as to an apparatus for processing such data.
In a system for recording digital data by using the unit of byte, which is equal to eight bits, data are processed by configuring Reed-Solomon error correcting product code blocks. More specifically, after arranging data of (MxN) bytes in M rows x N columns, a PO-byte error correcting check word is added to the N-byte information section of each column and then a Pi-byte error correcting check word is added to the N-byte information section of each row to produce a Reed-Solomon error correcting product code block comprising (M+PO) rows x (N+PI) columns. Then, random errors and burst errors can be efficiently corrected on the data reproducing side or the data receiving side by means of the Reed-Solomon error correcting product code blocks that is recorded and transmitted.A Reed-Solomon error correcting product code block as described above operates efficiently when the redundancy is large or the ratio of the redundant section of the error correcting check word (PixM+POxN+PlxPO) to the entire code word (M+PO)x(N+PI) is small. On the other hand, its error correcting ability is raised for both random errors and burst errors when
large values are used for PI and PO.
It is known that, when different Reed-Solomon error correcting product code blocks having a same level of redundancy are compared, those having small M, N, PI and PO are poorly adapted for error correcting because tjhe probability of occurrence of error correction rises with such code blocks.
On the other hand, while it is also known that the error correcting ability of a Reed-Solomon error correcting product code block is raised by increasing the values of M and N because the values of PI and PO are also increased accordingly, if the redundancy is held to a same level, such high error correcting ability cannot be realized without satisfying the requirements as will be described below.
Firstly, in terms of code word length that allows a Reed-Solomon code word to be configured, M+PO and N+PI have to be equal to or less than 255 bytes..
Secondly, there is a hardware cost restriction to be observed. Specifically, it is expressed typically
in terms of the cost of the operational circuit and that of the memory for storing the entire code word or (M+PO)x(N+PI) bytes. Since the cost of a memory can change with the development of semiconductor technology, it is highly desirable to make the above described parameters of M, N, PI and PO of Reed-Solomon error correcting product code block variable as a function of the advancement of semiconductor technology and, particularly, the reduction in the cost of a memory.
This is because a same error in a physical length or a time length is translated into a larger burst error bytes as the density with which data are recorded on a medium or the rate at which data are transmitted through a transmission path is raised in accordance with the advancement of semiconductor technology so that a higher error correcting ability becomes
necessary.
Conventionally, however, a Reed-Solomon error correcting product code block having (M+PO)x(N+PI) bytes is configured for a given data of (MxN) bytes so that the redundancy is automatically set as a function of the entire size of the product code block. In other words, any attempt for maintaining a given level of error correcting ability is accompanied by a problem of invariable block size.
However, as a higher recording density and a higher transmission rate are expected with the
advancement of semiconductor technology in the future, a much more higher level of error correcting ability will be required for an error correcting product code block of a given size. This in turn requires the use of a large error correcting check word, although it entails an enhanced level of redundancy if the conventional technology is used.
It is, therefore, an object of the present to provide a method of processing data for generating an error correcting product code block devised so as to maintain the current level of redundancy after the error correcting ability is improved as a result of advancement of the technologies of semiconductor and data recording/transmission. It is another object of the present invention to provide a method of processing data for recording such data on a recording medium as well as to an apparatus for processing such data.
According to the invention, the above objects are achieved by providing an error correcting product code block data structure obtained by configuring a (Kx(M+l)x(N+P))-byte Reed-Solomon error correcting product code block for a (KxMxN)-byte data and making K variable to consequently make the entire size of the Reed-Solomon error correcting product code block variable and, at the same time, the error correcting ability variable in proportion to the value of K.
The present invention therefore provides a method for processing data to be recorded or transmitted, said method generating an error correcting product code block comprising the steps of:
first, processing digital data on a byte by byte basis to configure a plurality of first information data blocks, each block comprising (MxN) bytes of M rows x N columns, permitting data to exist on the byte by byte basis in each first information data block and permitting the data in each roe to exist sequentially from a 0-th to a (N-l) -th column according to a sequence of data recording/ transmission and sequentially from a 0-th to a (M-l) -th row according to the sequence of data recording/ transmission;
each first information data block containing an ID-word comprising a sector number;
second, providing a matrix block of (KxM) rows x N columns by using K of the plurality of first information data blocks arranged sequentially to the sequence of data recording/ transmission;
third, adding a first error correcting check word of K bytes to each column of (KxM) bytes of the matrix block to turn each of the N columns into a Reed-Solomon code word C2 of (Kx(M+l)) bytes;
fourth, adding a second error correcting check word of P bytes to each row of N bytes to turn each of the (Kx(M+l)) rows into a Reed-Solomon code word CI of (N+P) bytes,
the error correcting product code block is a Reed-Solomon error correcting product code block of (Kx(M+l)x(N+P) bytes having an information section of K of the first information data blocks of (MxN) bytes; and
Fifth, redistributing the error correcting product code block of (Kx (M+l)x(N+P)) bytes on a byte by byte basis, so as to obtain a redistributed error correcting product code block formed of K second information data blocks of (M+l)x(N+P) bytes, each having an associated ID word and the error correcting check word of K bytes existing on a byte by byte basis at a position corresponding to every M bytes of information data.
With the above method, the sum of (MxN) bytes of an information data block and the average number of bytes of a check word added thereto is held to a constant value of (M+l)x(N+P) that is not dependent on the number of information data blocks, or K, of the error correcting product code block and hence the level of redundancy of the (M+l)x(N+P) bytes is maintained invariable.
According to the invention, there are also provided a method of processing data for recording such an error correcting product code block, a recording medium for recording such an error correcting product code block and a telecommunication apparatus for transmitting such an error correcting product code block.
This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:
FIG. 1 is an illustration showing the configuration of a known Reed-Solomon error correcting product code block;
FIG. 2 is a block diagram showing the procedure of generating a Reed-Solomon error correcting product code block according to an embodiment of the invention;
FIG. 3 is an illustration showing the configuration of a Reed-Solomon error correcting product code block generated by the procedure of FIG. 2;
FIG. 4 is an illustration showing the configuration of sectors of a Reed-Solomon error correcting product code block generated by a method according to the invention;
FIG. 5 is a block diagram showing the procedure of generating a Reed-Solomon error correcting product code block according to another embodiment of the invention;
FIG. 6 is an illustration showing the configuration of a Reed-Solomon error correcting product code block generated by the procedure of FIG. 5;
FIG. 7 is a block diagram showing the procedure of generating a Reed-Solomon error correcting product code block according to still another embodiment of the invention; and
FIG. 8 is an illustration showing the configuration of a Reed-Solomon error correcting product code block generated by the procedure of FIG. 7.
Now, the present invention will be described by referring to the accompanying drawings that illustrate preferred embodiments of the invention.
FIG. 1 is an illustration showing the configuration of a known Reed-Solomon error correcting product code block. With this known format, as described earlier, a Reed-Solomon error correcting product code block of
(M+PO)x(N+PI) bytes is configured for an information data of (MxN) bytes and, therefore, the level of redundancy and the size of the entire block is closely tied to each other so that the size of the block cannot be arbitrarily changed without modifying the error correcting ability. In other words, the level of redundancy is inevitably and undesirably raised if a large errcr correcting check word is used.
Contrary to this, according to the invention, a Reed-Solomon error correcting product code block is configured in a manner as illustrated in FIG. 2.
In a first embodiment, which will be described hereinafter, values of K=16, M=12, N=172 and P=10 are selected for recording a data of 2,048 bytes in a sector of a recording medium, which may preferably be an optical disc.
In this embodiment, P=10 bytes is selected for code word CI and K=16 bytes is selected for cord word C2 as the number of bytes of error correcting check word in view of the fact that an even number is more efficient than an odd number for a same error correcting ability, that a required level of burst error correcting ability cannot be maintained for K=16 rows if P=8 bytes or less because of a rise in the probability of error correction and that a relationship of K>P is required to raise the level of burst error correcting ability for a same level of redundancy.

Additionally, values of M=12 and N=172 are selected in view of the fact that the size of a sector has to be slightly larger than 2,048 bytes because a sector number and an error detecting word have to be added to a recorded data of 2,04 8 bytes for each sector.
FIG. 2 is a block diagram showing the procedure of generating a Reed-Solomon error correcting product code block by using a unit of 16 sectors. FIG. 3 is an illustration showing the row configuration of a Reed-Soiomon error correcting product code block in a sector.
Referring to block A through C of FIG. 2, in the first stejp, a digital data is processed on a byte by byte basis to form an information data block with (MxN) bytes of M (=12) rows x N (=172) columns and data are arranged on a byte by byte basis in the information data block, while data are arranged sequentially in each row from the 0th to the (N-l)-th column according to the sequence of data transmission and sequentially from the 0th to the (M-l)-th row according to the sequence of data, transmission.
Then, in the second step, a matrix block of (KxM) rows x N columns is arranged by using K (=16) information data blocks, each having a configuration as described above.
Subsequently, in the third step, an error correcting check 1 of K (=16) bytes is added to each

column of (KxM) bytes of the matrix block to turn each of N rows into a Reed-Solomon code word C2 of (Kx(M+l)) bytes.
Finally, in the fourth step, an error correcting check word of P (=10) bytes is added to each row of N bytes to turn each of the (Kx(M+l)) rows into a Reed-Solomon c|ode word CI of (N+P) bytes.
The 'entire error correcting product code block is a Reed-Solomon error correcting product code block of (Kx(M+l) x(N+P) ) bytes having an information section of K information data blocks of (KxMxN) bytes. The sum of (MxN) bytes of an information data block and the average number of bytes of a check word added thereto is held to a constant value of (M+l)x(N+P) bytes.
This embodiment will be described further by referring to FIGS. 2, 3 and 4.
A data to be recorded is taken in by 2,048 bytes at a time for a sector, to which a sector number and an error detecting word (16 bytes) are added for the sector to make the total number of bytes equal to 2,064. (See block A of FIG. 2.) As shown in FIG. 4, a total ot 16 bytes are used for a sector number (ID; sector identification)', an ID error correcting word (IEC), a system reservation code (RSV) and an error detecting code (EDC).
The 2,064 bytes are assigned to a sector of a Reed-Solomon error correcting product code block and

stored in the storage area of M rows x N columns -12 rows x 172 columns = 2,064 bytes obtained by-subtracting the storage area for an error correcting check word from the overall storage area of a sector of (M+l) rows x (N+P) columns = 13 rows x 182 columns.
In this way, the data is sequentially stored into K=16 sectors of memory.
After storing a data of 192 rows x 172 columns in K=16 sectors, each of the 172 columns are processed to produce a Reed-Solomon code word C2 of (192+12) bytes to fill the 16 void rows, each of which is arranged for every 16 rows (as indicated by X in FIG. 3). (See block B of FIG. 2.)
The relationship between the 16 rows to be filled with Reed-Solomon code words and the degree of the Reed-Solqmon code word C2 is determined in advance such that the positions of the 16 rows and the degree show a one-to-one correspondence or the former correspond to a lower degree side of the 15th down to the 0th.
After filling the 16 void rows (X), an error correcting check word of 10 bytes is added to each row of the matrix of 208 rows x 172 columns to form a (172+10)-byte Reed-Solomon code word CI for each of the 208 columns. Thus, a Reed-Solomon error correcting product code block is formed as shown in FIG. 3 by using a unit of 16 sectors. (See block C of FIG. 2.)
The block has a size of
208 rows x 182 columns = 37,856 bytes that can be optimally stored with a generous margin in a memory device that is currently commercially available at low cost.
The redundancy of a Reed-Solomon error correcting product code block realized by using a unit of 16 sectors is equal to
(208 x 182 - 192 x 172) / (208 x 182) = 12.76% while a correctable burst error has a maximum length that can be obtained on the basis of the number of rows corresponding to the number of error correcting check words C2, or 16 rows x 182 columns = 2,912 bytes.
As a correctable burst error has a maximum length that can be obtained on the basis of the number of rows corresponding to the number of error correcting check words C2, the error correcting ability can be improved by increasing the number of rows and that of error correcting check words C2 of a Reed-Solomon error correcting product code block.
Thus!, the level of redundancy can be maintained to a constant level with the above described method of the present invention because the information data is always allocated to th'e sectors in a manner as illustrated in FIG. 4.
Situations where the number of rows and that of error correcting check words have to be increased for a Reed-Solomon error correcting product code block may
include those where the error correcting ability has to be raised and those where the recording density per given length of the tracks of an optical disc as a result of advancement of the technologies of semi¬conductor and data recording/transmission. If such is the case, the number of error correcting check words C2 can be increased by increasing the number of rows of the block. For reproducing the stored information, the stored pieces of information are sequentially picked up along the rows of the block and, with the above described method of the present invention, a same level of redundancy can be maintained if the stored Reed-Solomon error correcting product code block is taken up for error correction.
While a figure of K=16 is used in the above description, it may be needless to say that K=12 may be selected depending on the memory size. Then, a less costly memory device may be used for the purpose of the invention since the size of block is 28,392 byte which can be stored in 256 Kbit capacity.
FIG. 5 is a block diagram showing the procedure of generating a Reed-Solomon error correcting product code block according to a second embodiment of the invention. Note that K=12 in this embodiment. Blocks 5A, 5B and 5C of FIG. 5 correspond to blocks A, B and C in FIG. 2 respectively.
FIG 6 is an illustration showing the configuration
of a Reed-Solomon error correcting product code block generated by the procedure of FIG. 5.
FIG. 7 is a block diagram showing the procedure of generating a Reed-Solomon error correcting product code block according to a third embodiment of the invention. FIG. 8 is an illustration showing the configuration of a Reed-Solomon error correcting product code block generated by the procedure of FIG. 7.
As shown, a data to be recorded is taken in by 2,048 bytes at a time for a sector, to which a sector number and an error detecting word (16 bytes) are added for the s|ector to make the total number of bytes equal to 2,064. (See block 7A of FIG. 7.) The 2,064 bytes are assigned to a sector of a Reed-Solomon error correcting product code block and stored in the storage area of M rows x N columns = 12 rows x 172 columns = 2,064 bytes obtained by subtracting the storage area for an error correcting check word from the overall storage area of a sector of (M+l) rows x (N+P) columns = 13 rows x 182 columns.
In this way, the data is sequentially stored into K=18 sectors of memory.
After storing a data of 216 rows x 172 columns in K=18 sectors, each of the 172 columns are processed to produce a Reed-Solomon code word C2 of (216+18) bytes to fill the 12 void rows, each of which is arranged for every 12 |rows (as indicated by X in FIG. 8). (See
block 7B of FIG. 7.)
After filling the 18 void rows (X), an error correcting check word of 10 bytes is added to each row of the matrix of 234 rows x 172 columns to form a (172 + 10 )-byte Reed-Solomon code word CI for each of the 2 34 columbs. Thus, a Reed-Solomon error correcting product code block is formed as shown in FIG. 8 by using a unit of 18 sectors. (See block 7C of FIG. 7.)
This embodiment can raise the error correcting ability relative to the preceding embodiments, although the level of redundancy remains same.
As described above in detail, there is provided a method of processing data for generating an error correcting product code block devised so as to maintain the current level of redundancy after the error correcting ability is improved as a result of advancement of the technologies of semiconductor and data recording/transmission.




We Claim:
1. A method for processing data to be recorded or transmitted, said method generating an error correcting product code block comprising the steps of:
first, processing digital data on a byte by byte basis to configure a plurality of first information data blocks, each block comprising (MxN) bytes of M rows X N columns, permitting data to exist on the byte by byte basis in each first information data block and permitting the data in each row to exist sequentially from a 0-th to a (N-1) -th column according to a sequence of data recording/ transmission and sequentially from a 0-th to a (M-1) -th row according to the sequence of data recording/ fransmission;
each first information data block containing an ID-word comprising a sector number;
second, providing a matrix block of (KxM) rows x N columns by using K of the plurality of first information data blocks arranged sequentially to the sequence of data recording/ transmission;
third, adding a first error correcting check word of K bytes to each column of (KxM) bytes of the matrix block to turn each of the N columns into a Reed-Solomon code word C2 of (Kx(M+l)) bytes;
fourth, adding a second error correcting check word of P bytes to each row of N bytes to turn each of the (Kx(M+l)) rows into a Reed-Solomon code word CI of (N+P) bytes,
the error correcting product code block is a Reed-Solomon error correcting product code block of (Kx(M+l)x(N+P) bytes having an information section of K of the first information data blocks of (MxN) bytes; and
Fifth, redistributing the error correcting product code block of (Kx (M+l)x(N+P)) bytes on a byte by byte basis, so as to obtain a redistributed error correcting product code block formed of K second information data blocks of (M+l)x(N+P) bytes, each having an associated ID word and the error correcting check word of K bytes existing on a byte by byte basis at a position corresponding to every M bytes of information data.
2. A method of processing data as claimed m claim 1, wherein:
a value of MxN is at least 2054 and less than 2064, the K is an even number having a value being at least 12, the P is an even number having a value being at least 10, a value of Kx(M+l) is at most 255, and a value of N+P is at most 255.
3. A method of processing data as claimed in any one of claim 1 and 2, wherein M=12, N=172, K=16 and P=10.
4. A method of processing data as claimed m any one of claims 1 and 2, wherein M=12,N=172, K-12andP=10.
5. A method of processing data as claimed in any one of claims 1 and 2, wherein M=12, N=172, K-18 and P=10.
6. A method of processing data as claimed in claim !, wherein:
each of the second information data blocks contains data to be transmitted or second on a sector of a recording medium, and ID word of the information data blocks comprises:
a sector identification, an ID error correcting information a system reservation code, and an error detecting code.
7. A method of processing data as claimed in claim 6, wherein;
the sector identification includes four bytes, the ID error correcting information includes two bytes, the system reservation code includes six bytes, and the error detecting code includes 4 bytes.
8. A method for generating a data signal containing redistributed error correcting
product code block is formed of K information data blocks of (M+l)x(N+P)
bytes, each having the associated ID word and the error correcting check word
of K bytes existing on a byte by byte basis at a position corresponding to every
M bytes of information data, said redistributed error correcting product code
block being formed by a method as claimed in any of claims 1 to 7.
9. A recording medium comprising an error correcting product code block thereon, wherein data is processed and the error correcting product code block is generated by a method according to any one of claims 1 to 7.
10. A recording medium as claimed in claim 9, wherein said error correcting product code block being correspondingly recorded in a sector.
11. A data processing apparatus comprising means for processing digital data on a byte by byte basis to configure a plurality of first information data blocks comprising (MxN) bytes of M rows x N columns;
means for arranging the digital data on a byte by byte basis in the first information data block and arranging the digital data in each row sequentially from a 0-th to a (N-l)-th column according to a sequence of data transmission or recording and sequentially from a 0-th to a (M-l)-th row according to the sequence of data transmission or recording,
means for arranging a matrix block or (KxM) rows x N columns by using K of the first information data blocks arranged sequentially according to the sequence of data transmission or recording,
means for adding a first error correcting check word of K bytes to each column of (KxM) bytes of the matrix block to turn each of the N rows into a Reed-Solomon code word C2 of (Kx(M+l)) bytes; and means for adding a second error correcting check word of P bytes to each row of N bytes to turn each of the (Kx(M+l)) rows into a Reed-Solomon code word CI of (N+P) bytes,
the error correcting product code block is a Reed-Solomon error correcting product code block of (Kx(M+l)x(N+P) bytes having an information section of K of the first information data blocks of (MxN) bytes; and
means for redistributing the error correcting product code block of (Kx (M+l)x(N+P)) bytes on a byte by byte basis, so as to obtain a redistributed error correcting product code block formed of K second information data blocks of (M+l)x(N+P) bytes, each having an associated ID word and the error correcting check word of K bytes existing on a byte by byte basis at a position corresponding to every M bytes of information data.
12. A data processing apparatus as claimed in claim U wherein the means for processing an error correcting product code block is arranged in a telecommunications apparatus, a data recording apparatus for recording data onto a disk or an error correction processing apparatus.
13. A transmission apparatus for transmitting a data signal as claimed in claim 8 comprising the data processing apparatus as claimed in any one of claims 10 or 11.
14. An optical disk data reproducing apparatus for reproducing data from an optical disk in which an error correcting product code block is recorded, and for executing error correction processing with respect to the reproduced data, said error correcting product code block being configured by a method as claimed by any of claims 1 to 7.

Documents:

763-del-1996-abstract.pdf

763-del-1996-claims.pdf

763-del-1996-complete specification (granted).pdf

763-del-1996-correspondence-others.pdf

763-del-1996-correspondence-po.pdf

763-del-1996-description (complete).pdf

763-del-1996-drawings.pdf

763-del-1996-form-1.pdf

763-del-1996-form-13.pdf

763-del-1996-form-2.pdf

763-del-1996-form-3.pdf

763-del-1996-form-4.pdf

763-del-1996-form-6.pdf

763-del-1996-gpa.pdf

763-del-1996-pa.pdf

763-del-1996-pct-210.pdf

763-del-1996-petition-124.pdf

763-DEL-1996-Petition-138.pdf

abstract.jpg


Patent Number 195840
Indian Patent Application Number 763/DEL/1996
PG Journal Number 31/2009
Publication Date 31-Jul-2009
Grant Date 07-Jul-2006
Date of Filing 09-Apr-1996
Name of Patentee KABUSHIKI KAISHA TOSHIBA
Applicant Address LOCATED AT 72 HORIKAWA-CHO SAIWAI-KU KAWASAKI-SHI JAPAN.
Inventors:
# Inventor's Name Inventor's Address
1 YOSHIHISA FUKUSHIMA C-508, 6-14 SEKIME JOTO-KU OSAKA-SHI JAPAN.
2 TAKASHI YUMBIA 606 BELBE-NISHIURA 58 NISHIURA KOWATA UJI-SHI KYOTO JAPAN.
3 TADASHI KOJIMA 4-77-19 TOMIOKANISHI KANAZAWA-KU YOKOHAMA JAPAN.
4 KOICHI HIRAYAMA 1-7-10 GUMISAWA TOTSUKA-KU YOKOHAMA-SHI JAPAN.
PCT International Classification Number G11B 20/12
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 7-086874 1995-04-12 Japan