Title of Invention	METHOD AND APPARATUS FOR PROVIDING DYNAMICALLY VARIABLE TIME DELAYS FOR ULTRASOUND BEAMFORMER
Abstract	A phased array sector scanning ultrasonic system includes a separate receive channel for each respective element- in an ultrasonic transducer array. Each receive channel inparts at delay to the echo signal produced by each respective element* The delayed echo signals are summed to form a steered, dynamically focused and dynamically windowed receive beam even when the transmit beam does not emanate from the center of the array. The receiver has a beamformer including a multiplicity of beamformer channels 35% The beamformer dynamically increases delays to each channel without introducing unwanted discontinuities, by combing and synchronizing a FIFO and an interpolator. The interpolator uses "Wallace tree" adders to accumulate bit-shifted versions of the inputs. The number of additions is less than the number of bits which would be needed to represent equivalent coefficients. This reduces the hardware relative to a conventional implementation which incorporates multipliers with shifts and adds equaling the number of bits in the coefficients.

Title of Invention

METHOD AND APPARATUS FOR PROVIDING DYNAMICALLY VARIABLE TIME DELAYS FOR ULTRASOUND BEAMFORMER

Abstract

A phased array sector scanning ultrasonic system includes a separate receive channel for each respective element- in an ultrasonic transducer array. Each receive channel inparts at delay to the echo signal produced by each respective element* The delayed echo signals are summed to form a steered, dynamically focused and dynamically windowed receive beam even when the transmit beam does not emanate from the center of the array. The receiver has a beamformer including a multiplicity of beamformer channels 35% The beamformer dynamically increases delays to each channel without introducing unwanted discontinuities, by combing and synchronizing a FIFO and an interpolator. The interpolator uses "Wallace tree" adders to accumulate bit-shifted versions of the inputs. The number of additions is less than the number of bits which would be needed to represent equivalent coefficients. This reduces the hardware relative to a conventional implementation which incorporates multipliers with shifts and adds equaling the number of bits in the coefficients.

Full Text	METHOD AND APPARATUS FOR PROVIDING DYNAMICALLY VARIABLE TIME DELAYS FOR ULTRASOUND BEAMFORMER Field of the Invention This invention generally relates to ultrasound imaging systems which form ultrasonic beams by time delay and summation of return signals in a multiplicity of parallel channels. In particular, the invention relates to means for providing the required beamforming delays to channel processing. Background of the Invention Conventional ultrasound imaging systems comprise an array of ultrasonic transducers which are used to transmit an ultrasound beam and then receive the reflected beam from the object being studied. For ultrasound imaging, the array typically has a multiplicity of transducers arranged in a line and driven with separate voltages. By selecting the time delay (or phase) and amplitude of the applied voltages, the individual transducers can be controlled to produce ultrasonic waves which combine to form a net ultrasonic wave that travels along a preferred vector direction and is focused at a selected point along the beam. Multiple firings may be used to acquire data representing the same anatomical information. The beamforming parameters of each of the firings may be varied to provide a change in maximum focus or otherwise change the content of the received data for each firing, e.g., by transmitting successive beams along the same scan line with the focal point of each beam being shifted relative to the focal -2- point of the previous beam. By changing the time delay and amplitude of the applied voltages, the beam with its focal point can be moved in a plane to scan the object. The same principles apply when the transducer is employed to receive the reflected sound (receiver mode). The voltages produced at the receiving transducers are summed so that the net signal is indicative of the ultrasound reflected from a single focal point in the object. As with the transmission mode, this focused reception of the ultrasonic energy is achieved by imparting separate time delay (and/or phase shifts) and gains to the signal from each receiving transducer. Such scanning comprises a series of measurements in which the steered ultrasonic wave is transmitted, and the reflected ultrasonic wave is received and stored. Typically, transmission and reception are steered in the same direction during each measurement to acquire data from a series of points, along an acoustic beam or scan line. The receiver is dynamically focused at a succession of ranges along the scan line as the reflected ultrasonic waves are received. An ultrasound image is composed of multiple image scan lines. A single scan line (or small localized group of scan lines) is acquired by transmitting focused ultrasound energy at a point in the region of interest, and then receiving the reflected energy over time. The focused transmit energy is referred to as a transmit beam. During the time after transmit, one or more receive beamformers coherently sum the energy received by each channel, with dynamically changing phase rotation or delays, to produce peak sensitivity along the desired scan lines at ranges proportional to the elapsed time. The resulting focused sensitivity pattern is referred to as a receive beam. A scan line's resolution is a result of the directivity of the associated transmit and receive beam pair. -3- Scan lines are defined by their position and angle. The intersection of a beam with the transducer face is referred to as the phase center. The angle of a scan line relative to orthogonal is referred to as the steering angle. Beamforming delays may be fixed or dynamic. Transmit delays are fixed to provide peak pressure at - a particular range. Receive delays are typically dynamic since the peak sensitivity must track the increasing range r of reflections as a function of elapsed time t: (1) where c is the speed of sound in the imaged media. The elapsed time may be quantized by an amount ##r, which is equivalent to quantized focal ranges: (2) The geometry used herein is shown in FIGS. 1A and 1B for linear/sector and curved linear transducers, respectively. The important reference points are the phase center, focal point and element position. The phase center will always be the origin of the (x,z) Cartesian coordinate system. The focal point is r and the element position is pi. For curved arrays the element position is determined by the radius of curvature p and the channel angle ##j = lip, where li is the distance from phase center along the face of the probe. The beamformer must compensate for channel to channel differences in the propagation time Tp of sound traveling between phase center and pi via a reflector at r. The relative delay Td is the difference between the propagation time for channel i and the propagation time for the phase center. For the geometry in FIG. 1A, the times Tp and Td are as follows: -4- Referring to FIG. 2, a conventional ultrasound imaging system includes a transducer array 10 comprised of a plurality of separately driven transducer elements 12, each of which produces a burst of ultrasonic energy when energized by a pulsed waveform produced by a transmitter 22. The ultrasonic energy reflected back to transducer array 10 from the object under study is converted to an electrical signal by each receiving transducer element 12 and applied separately to a receiver 24 through a set of transmit/receive (T/R) switches 26. The T/R switches 2 6 are typically diodes which protect the receive electronics from the high voltages generated by the transmit electronics. The transmit signal causes the diodes to shut off or limit the signal to the receiver. Transmitter 2 2 and receiver 24 are operated under control of a scan controller 28 responsive to commands by a human operator. A complete scan is performed by acquiring a series of echoes in which transmitter 22 is gated ON momentarily to energize each transducer element 12, and the subsequent echo signals produced by each transducer element 12 are applied to receiver 24. A channel may begin reception while another channel is still transmitting. The receiver 24 combines the separate echo signals from each transducer element to produce a single echo signal which is used to produce a line in an image on a display monitor 30. -5- Transmitter 22 drives transducer array 10 such that the ultrasonic energy produced is directed, or steered, in a beam. To accomplish this, transmitter 22 imparts a time delay to the respective pulsed waveforms W. that are applied to successive transducer elements 12 via respective beamformer channels. Each channel has a respective pulser associated therewith. By adjusting the pulse time delays appropriately in a conventional manner, the ultrasonic beam can be directed away from axis 36 by an angle ##8 and/or focused at a fixed range R. A sector scan is performed by progressively changing the time delays in successive excitations. The angle ##$ is thus changed in increments to steer the transmitted beam in a succession of directions. The echo signals produced by each burst of ultrasonic energy reflect from objects located at successive ranges along the ultrasonic beam. The echo signals are sensed separately by each transducer element 12 and the magnitude of the echo signal at a particular point in time represents the amount of reflection occurring at a specific range. Due to the differences in the propagation paths between a reflecting point P and each transducer element 12, however, these echo signals will not be detected simultaneously and their amplitudes will not be equal. Receiver 24 amplifies the separate echo signals, imparts the proper time delay to each, and sums them to provide a single echo signal which accurately indicates the total ultrasonic energy reflected from point P located at range R along the ultrasonic beam oriented at the angle ##0. To simultaneously sum the electrical signals produced by the echoes impinging on each transducer element 12, time delays are introduced into each separate beam-former channels of receiver 24. The beam time delays for reception are the same delays as the transmission delays described above. However, the time delay of each -6- receiver channel is continuously changing during reception of the echo to provide dynamic focusing of the received beam at the range R from which the echo signal emanates. Under the direction of scan controller 28, receiver. 24 provides delays during the scan such that steering of receiver 2 4 tracks the direction ##6 of the beam steered by transmitter 2 2 and provides the proper delays and phase shifts to dynamically focus at points P along the beam. Thus, each transmission of an ultrasonic pulse waveform results in the acquisition of a signal with a magnitude which represents the amount of reflected sound from anatomy located along the ultrasonic beam. A detector 25 converts the received signal to display data. in the B-mode (greyscale) , this would be the envelope of the signal with some additional processing such as edge enhancement and logarithmic compression. Scan converter/interpolator 32 receives the display data from detector 25 and converts the data into the desired image for display. In particular, the scan converter converts the acoustic image data from polar coordinate (R-##6) sector format or Cartesian coordinate linear array to appropriately scaled Cartesian coordinate display pixel data at the video rate. This scan-converted acoustic data is then output for display on display monitor 30, which images the time-varying amplitude of the envelope of the signal as a grey scale. Referring to FIG. 3, the receiver comprises a receive beamforming section 34 and a signal processor 38. The receive beamforming section 34 of receiver 24 includes separate beamformer channels 35. Each beam-former channel 35 receives the analog echo signal from a respective transducer element. The beamformer controller 50 converts scan line and transmit focus numbers to addresses into a channel control memory (not shown). The scan controller 28 (FIG. 2) and beamformer control- -7- ler 50 (FIG. 3) are loaded by the system host CPU in response to user actions such as changing the display format or connecting a different ultrasound probe. As seen in FIG. 4, each beamformer channel 35 comprises a receive channel and a transmit channel, each, channel incorporating delay means 40 and 42 respectively, which are controlled to provide the needed beamform-ing delays by receive control logic 44 and transmit control logic 46 respectively. Transmit is typically done by using a counter to delay the start of transmit pulse generation. Some systems may also apply relative phase rotations in addition to, or in place of, delays for receive. The receive channels also have circuitry 48 for apodizing and filtering the receive pulses. The signals entering the summer 3 6 (see FIG. 3) have been delayed so that when they are summed with delayed signals from each of the other beamformer channels 35, the summed signals indicate the magnitude and phase of the echo signal reflected from anatomy located along the steered beam (##$) . Signal processor 38 receives the beam samples from the summer 3 6 and produces an output to scan converter 3 2 (see FIG. 2). In accordance with the foregoing conventional time-delay digital beamforming system, each signal processing channel 35 comprises an analog-to-digital converter (ADC) and a FIFO which is controlled to provide integer time delays. The ADC and FIFO inputs are driven with asynchronous clocks to produce variable delays. Extra clock cycles are inserted when necessary to increase the FIFO depth. This degrades the performance of the ADCs and presents many implementation difficulties due to timing. Other prior art digital beamformers interpolate the data to a higher sampler rate before entering the FIFO. This increases the required size of the FIFO. -8- Yet, other prior art digital beamformers interpolate the output of the FIFO. Dynamic changes in the delay of the FIFO create discontinuities at the input to the interpolator, degrading the interpolator per- formance. Summary of the Invention The present invention is an apparatus for generat-ing the required beamforming delays for an ultrasound imaging system with minimal hardware and software. In particular, the invention--is a method for providing dynamically variable time delays with sub-sample rate precision in an ultrasound beamformer. Receive beamforming for a high-performance ultrasound imaging system requires time delay precision on the order of 5 nsec. However the receive signal may be fully represented, digitally, with much lower sample periods: such as 40 MHz for a real signal or 10 MHz after demodulation and/or filtering. The present invention provides dynamically variable delays with a precision which is a fraction of the sample period, without increasing the actual sample rate. The fractional delays are provided through the use of an interpolator running at the input sample rate. To maintain focus during reception, ultrasound beamformer must dynamically increase delays to each channel. The present invention provides the required dynamic delay without introducing unwanted discontinuities, by combining and synchronizing a FIFO and an interpolator. The preferred embodiment of the interpolator uses "Wallace tree" adders to accumulate bit-shifted versions of the inputs. The number of additions is less than the number of bits which would be needed to represent equivalent coefficients. This reduces the hardware relative to a conventional implementation which incorporates -9- multipliers with shifts and adds equaling the number of bits in the coefficients. Another feature of the preferred embodiment is that its performance is adequate over the complete range of input frequencies conventionally utilized for medical imaging, while allowing for degradation outside of that frequency range. It does not require modification when the input signal changes frequency. This feature is optional: some embodiments may include frequency-dependent configurations. Brief Description of the Drawings FIGS. 1A and 1B are diagrams showing the beamform-ing geometry for linear/sector and curved linear transducers respectively. FIG. 2 is a block diagram showing the major functional subsystems within a conventional real-time ultrasound imaging system. FIG. 3 is a block diagram of a typical 128-channel beamformer for the system depicted in FIG. 2. FIG. 4 is a block diagram of the channel processing in the conventional beamformer depicted in FIG. 3. FIG. 5 is a block diagram of a receive signal processing channel in accordance with the present invention. FIG. 6 is a graph showing the four-point cubic interpolation frequency response of an interpolation filter in accordance with the invention. FIGS. 7A and 7B are graphs showing the magnitude response and group delay, respectively, for an interpolation filter in accordance with the invention. FIG. 8 is a block diagram showing the dynamic beam-forming delay logic in accordance with the preferred embodiment of the invention. FIG. 9 is a block diagram showing the delay control logic incorporated in the dynamic beamforming delay -10- logic depicted in FIG. 8. FIG. 10 is a block diagram showing the interpolator incorporated in the dynamic beamforming delay logic depicted in FIG. 8 in accordance with one preferred embodiment of the invention. FIG. 11 is a block diagram showing further details of a representative shift and add block incorporated in the interpolator depicted in FIG. 10. FIG. 12 is a block diagram showing the interpolator incorporated in the dynamic beamforming delay logic depicted in FIG. 8 in accordance with another preferred embodiment of the invention. Detailed Description of the Preferred Embodiments Referring to FIG. 5, each receive signal processing channel 3 5 in accordance with the present invention comprises an amplifier 52 which amplifies the signal detected by a respective ultrasound transducer element; an analog-to-digital converter 54 which converts the amplified analog signal into a stream of digital samples at a sampling rate (e.g., each digital sample having 8 bits); an integer sample period delay circuit 56 for delaying the digital samples by a time interval equal to an integer number of sample periods; and a fractional sample period delay circuit 58 for delaying the digital samples by a time interval equal to a fraction of the sample period. The outputs of the respective fractional sample period delay circuits for each processing channel are then summed in the summer 36, shown in FIG. 3. In accordance with the present invention, the integer sample period delay circuit comprises a dynamic FIFO 101 and a series of clocked pipeline registers 102-105 (see FIG. 8), while the fractional sample period delay circuit comprises an interpolator 107. Parallel receive beamforming could be supported by having multiple read locations from each FIFO. An alternative would be to -11- have separate FIFOs for each receive beam. In accordance with the broad concept of the invention, the dynamic FIFOs provide range-dependent time delay to support broadband beamforming. The FIFOs support a 40-MHz sample rate providing a "coarse" delay, accuracy of ±12.5 nsec. The initial lengths of the FIFOs are controlled by multiple-bit control fields called "initial receive delay". When a delay increment machine (not shown) requests a FIFO delay increment, the FIFO length is increased at the output with a repetition or "hold" of the output sample, i.e., the output data does not change from the previous 40 MHz clock tick. In accordance with the invention, one interpolator is required for each receive beam. The interpolator provides the "fine" delay adjustment by interpolating between samples from the FIFO. In accordance with one preferred embodiment, the interpolator interpolates between four samples from the FIFO to produce a delay of 2.75, 2.5, 2.25 or 2.0 25-nsec clock periods. This provides a delay accuracy of ±3.125 nsec. The interpolator coefficients in accordance with the preferred embodiment are listed in Table 1. TABLE 1 Coefficients Breakdown -20 -(16+4) -31 -32+1 -28 -32+4 0 0 74 64+8+2 152 128+32-8 220 256-32-4 256 256 220 256-32-4 152 128+32-8 74 64+8+2 0 0 -28 -32+4 -31 -32 + 1 -20 -(16+4) 0 0 -12- These coefficients are all simple combinations of powers of 2, scaled by 256. To obtain a delay of 2.75, the 1st, 5th, 9th and 13th coefficients are used; to obtain a delay of 2.5, the 2nd, 6th, 10th and 14th coefficients are used; and so on. The delay counter 106 (see FIG. 8) associated with each beam selects the interpolation coefficients and indicates when a FIFO delay increase is required. When a FIFO delay increase "holds" the FIFO output, the interpolator data must also be held. An example is shown in Table 2, where each row represents a 4 0 MHz clock tick. The first column indicates the desired dynamic delay in units of 40 MHz clock ticks, starting in the first row at 5.0. The interpolator provides the fractional portion of this delay, with two additional integer delays. The next four columns are the content of the interpolator input buffers, and the last four columns are the coefficients used. A FIFO delay increment is required in the last row, thus s(25) is held at the output of the FIFO, as well as all the data in the interpolator input buffer. TABLE ; 2 Time Delay Interpolator Input Buffer Interpolator Coefficients 10.0 5.0 8(6) 8(5) s(4) 8(3) 0 256 0 0 11.0 5.0 8(7) 8(6) 8(5) 8(4) 0 256 0 0 12.0 5.0 8(8) 8(7) s(6) 8(5) 0 256 0 0 13.0 5.0 8(9) s(8) s{7) 8(6) 0 256 0 0 14.0 5.25 8(10) 8(9) 8(8) 8(7) -28 220 74 -20 15.0 5.25 8(11) 8(10) 8(9) 8(8) -28 220 74 -20 16.0 5.25 8(12) 8(11) 8(10) 8(9) -28 220 74 -20 17.0 5.25 8(13) 8(12) s(ll) 8(10) -28 220 74 -20 18.0 5.5 8(14) 8(13) s(12) 8(11) -31 152 152 -31 19.0 5.5 S(1S) 8(14) a(13) 8(12) -31 152 152 -31 20.0 5.5 8(16) 8(15) s(14) a(13) -31 152 152 -31 21.0 5.5 8(17) 8(16) 6(15) 8(14) -31 152 152 -31 22.0 5.5 8(18) 8(17) s(16) 8(15) -31 152 152 -31 23.0 5.5 8(19) a(18) 8(17) 8(16) -31 152 152 -31 24.0 5.5 s(20) 8(19) 8(18) 8(17) -31 152 152 -31 25.0 5.5 8(21) 8(20) 8(19) 8(18) -31 152 152 -31 26.0 5.75 8(22) 8(21) s(20) 8(19) -20 74 220 -28 27.0 5.75 8(23) s{22) 8(21) s(20) -20 74 220 -28 28.0 5.75 8(24) s s(22) 8(21) -20 74 220 -28 29.0 5.75 s(25) s(24) B(23> s(22) -20 74 220 -28 30.0 6.0 S(25) s(24) s(23) s(22) 0 256 0 0 31.0 6.0 8(26) 8(25) s(24) s(23) 0 256 0 0 -13- Interpolation is equivalent to applying a linear time-invariant filter to a zero-filled signal. The zero-filled signal represents the sampled input signal with zeros between the known sample values. The spectrum of the zero-filled, sampled signal has high-fre-. quency images of the input spectrum at harmonics of the sample rate. The interpolation filter passes the spectrum of the input signal while attenuating all the images. These images are above the array design frequency as determined by the interelement spacing. Thus, they produce grating lobes. The relative level of these grating lobes is determined by the stopbands of the interpolation filter around the sample rate harmonics. The filter coefficients for this design are listed in Table 1. The frequency response of this interpolation filter is shown in FIG. 6. It has a -3 dB passband to greater than 13 MHz, and -35 dB stopbands around 40, 80, and 120 MHz, each 26 MHz wide. Thus a CW signal would have grating lobes at -35 dB in the worst case. The grating lobes of a typical signal are much lower. A worst case example would be a 20-cycle PW Doppler burst on a 40-channel aperture. The first grating lobe will be attenuated an additional -6 dB, making the overall level less than -40 dB. Another way to look at the interpolator is as a selection of all-pass filters with different group delays. This approach may be more intuitive since it is closer to the actual implementation. In this design, four coefficients are applied according to the desired fractional delay. Since there are four fractional delays available, there are four sets of four coefficients, each with an associated group delay and magnitude response. FIGS. 7A and 7B shows the responses for the coefficients listed in Table 1. The magnitude response is flat to ±0.5 dB out to 13 MHz, and the group delay is correct to within 3.25 nsec out to 13 MHz. -14- While this approach provides insight into the resulting accuracy, it does not lead to an estimate of beamforming performance (i.e. grating lobe levels), as directly as the first approach. Compared to cordic rotation or linear interpolation, this approach provides better-performance and/or less hardware in all modes. In accordance with a preferred embodiment of the invention shown in FIG. 8, dynamic beamforming delays are provided by FIFO 101, pipeline registers 102-105, and interpolator 107. The FIFO 101 provides delays that are an integer number of sample clock (SCLK) periods. Registers 102 and 103, provide an additional delay of two sample periods, to IN2, the nominal center input of the interpolator 107. The interpolator 107 provides an additional fractional delay between the center two (IN2 and IN3) input samples. Although a four-sample interpolator is shown, the invention may be generalized to use Q input samples from Q registers, where Q is an integer equal to 2 or more. The input registers would then provide Q/2 sample periods of delay, while the interpolator interpolated between the .center two inputs. The dynamic beamforming delay logic shown in FIG. 8 has a delay counter 106 which controls FIFO 101, registers 102-105, and interpolator 107 in a synchronous manner. The overall delay may be increased in response to a "Delay Increment" signal from a delay increment machine (not shown) , at each tick of a control clock (CCLK). The delay counter 106, shown in FIG. 9, outputs a fractional delay index and an overflow bit. In the general case where the interpolator 107 provides a selection of L fractional delays from 0 to (L - 1) /L sample periods, then the index is M - log2L bits. Each time CCLK ticks with "Delay Increment" set, the delay counter accumulator 108 increments to select the next fractional delay. When overflowing from (L - 1) to 0, the overflow logic 110 sets the overflow bit for one -15- SCLK period to disable reading the FIFO 101 via REN and clocking the registers via CE. REN stops the read of the FIFO while continuing, to write, producing an extra sample of FIFO delay per SCLK tick. One SCLK tick of REN increases the FIFO delay one sample period. CE holds the contents on the interpolator input registers to keep them synchronized with the FIFO output, with the nearest four samples to the desired output. This happens simultaneously with the interpolator delay switching from (L - 1)/L to 0 fractional delay, producing the desired net increase of 1/L fractional delays without discontinuity. This is illustrated in Table 2. To meet practical timing constraints, CCLK must have the proper relationship to SCLK. The CCLK trigger edge must occur early enough to allow the REN" and CE control inputs to setup before the SCLK trigger edge. In general, the CCLK may run at a slower rate than the SCLK. The CCLK frequency fc only needs to be high enough to keep up with the rate that the beamforming delays must change over range. A good approximation is: (7) where fs is the SCLK frequency, fn is the minimum receive f-number, and $ is the maximum steering angle relative to broadside. A system which has a minimum receive f-number of 1.5, a maximum steering angle of 45 degrees, a sample rate of 40 MHz, and an interpolation ratio L of 4, requires a 10 MHz control clock. The interpolator may be a conventional interpolator such as described in the prior art; however, the preferred embodiment is shown in FIG. 10. A multiplexer 111 selects one of the L fractional delays according to the index from delay counter 106 (see FIG. 8). If the index is zero, the sample from the second (0/2) input -16- register is passed to the output directly. Otherwise, the output of one of (L - 1) shift and add blocks 112 through 114 is used. An advantage of the foregoing method is that no multipliers are needed; only shifts, inversions and one-Wallace tree adder are needed per shift and add block (see FIG. 11)• The bit shifters require no control or active circuitry; the shifts are simply performed by shifting the bit connections. Inversion is very simple, and a Wallace tree adder is the must efficient VLSI design for adding many values. In the preferred embodiment shown in FIG. 11, the first input sample is shifted/inverted in two ways in respective blocks 116A, 116B; the second input sample is shifted/inverted in three ways in respective blocks 116C-116E; the third input sample is shifted/ inverted in three ways in respective blocks 116F-116H; and the fourth input sample is shifted/inverted in two ways in respective blocks 1161, 116J. For example, to obtain a delay of 2.75, the 1st, 5th, 9th and 13th coefficients listed in Table 1 are broken down and used as follows: input IN1 to shift/invert block 116A is shifted by 4 bits and inverted (i.e., equivalent to multiplication by -16); input IN1 to shift/invert block 116B is shifted by 2 bits and inverted (i.e., equivalent to multiplication by -4); input IN2 to shift/invert block 116C is shifted by 6 bits (i.e., equivalent to multiplication by 64); input IN2 to shift/invert block 116D is shifted by 3 bits (i.e., equivalent to multiplication by 8); input IN2 to shift/invert block 116E is shifted by 1 bit (i.e., equivalent to multiplication by 2); input IN3 to shift/invert block 116F is shifted by 8 bits (i.e., equivalent to multiplication by 256); input IN3 to shift/invert block 116G is shifted by 5 bits and inverted (i.e., equivalent to multiplication by -32); input IN3 to shift/invert block 116H is shifted by 2 -17- bits and inverted (i.e., equivalent to multiplication by -4); input IN4 to shift/invert block 1161 is shifted by 6 bits and inverted (i.e., equivalent to multiplication by -32); and input IN4 to shift/invert block 116J is shifted by 2 bits (i.e., equivalent to multiplication-by 4). All shifted/inverted samples are then supplied to a Wallace tree adder 115 for summing, e.g., -20(IN1) + 74(IN2) + 220(IN3) - 28(IN4). This is equivalent to interpolating with coefficients that are limited to the sum or difference of two or three powers of 2, i.e., ±2shift. More powers of two can be used for better performance. An alternate approach takes advantage of the symmetry of the interpolation coefficients. Coefficients for the i/L fractional delay are just reversed in order from coefficients for the (L - i) /L delay, where i Proper selection of the shifts and inversions, i.e., coefficients, can provide adequate performance across the entire ultrasound imaging band. The foregoing preferred embodiments have been disclosed for the purpose of illustration. Variations and modifications will be readily apparent to those skilled in the art of beamforming for ultrasound imaging. All such variations and modifications are intended to be encompassed by the claims set forth hereinafter. -18- WE CLAIM: 1. A beamforming channel (35) comprising analog-to-digital conversion means (54) for outputting digital samples at a sampling rate, an integer sampling period delay circuit (56) having an input coupled to receive said digital samples and having an output, a fractional sampling period delay circuit (58) having an input coupled to receive said digital samples from said integer sampling period delay circuit (56) and having an output, and a delay control circuit (106) coupled to said integer sampling period delay circuit (56) and to said fractional sampling period delay circuit (58) for outputting delay signals which dynamically synchronously control the amount by which said integer sampling period delay circuit (56) and said fractional sampling period delay circuit (58) will respectively delay a signal passing therethrough, wherein said integer sampling period delay circuit (56) comprises a FIFO (101) having an input coupled to receive said digital samples and having an output, and a first register (102) having an input coupled to said output of said FIFO (101) and having an output, said fractional sampling period delay circuit comprises an interpolator (107) having a first input (IN1) coupled to said output of said first register (102) and said delay control circuit comprises means (108, 110) for holding the contents of said first register (102) to keep said output of said first register (102) synchronized with said output of said FIFO (101) following a change in the amount of delay provided by said FIFO (101). 2. The beamformer channel as defined in claim 1, further comprising a second register (103) having an input coupled to said output of said first register (102) and having an output, wherein said interpolator (107) has a second input (IN2) coupled to said output of said second register (103) and said delay control circuit (106) comprising means (108, 110) for holding the contents of said second register (103) to keep said output of said second register (103) synchronized with said output of said FIFO (101) following said change in the amount'of delay provided by said FIFO (101). 3. The beamformer channel as defined in claim 2, further comprising a third register (104) having an input coupled to said output of said second register (103) and having an output, and a fourth register (105) having an input coupled to said output of said third register and having an output, wherein said interpolator has third and fourth inputs (IN3, IN4) respectively coupled to said outputs of said third and fourth registers (104, 105), and said delay control circuit (106) comprising means (108, 110) for holding the contents of said third and fourth registers (104, 105) to keep said outputs of said third and fourth registers synchronized with said output of said FIFO (101) following said change in the amount of delay provided by said FIFO. 4. The beamformer channel as defined in claim 2, wherein said interpolator (107) outputs an interpolated digital sample which is a function of first and second digital samples - 19 - received from said first and second registers (102, 103) respectively. 5. The beamformer channel as defined in claim 2, wherein said interpolator (107) comprises: first means for shifting and inverting (112, 116A-J) said first and second digital samples from said first and second registers (102, 103) in accordance with a first set of interpolation coefficients to produce a first multiplicity of shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second digital samples from said first and second registers (102, 103) in accordance with said first set of interpolation coefficients; a first adder (112, 115) coupled to receive and add said first multiplicity of shifted and inverted digital samples to produce a first interpolated digital sample; second means (113, 116A-J) for shifting and inverting said first and second digital samples from said first and second registers in accordance with a second set of interpolation coefficients to produce a second multiplicity of shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second digital samples from said first and second registers in accordance with said second set of interpolation coefficients; a second adder (113, 115) coupled to receive and add said second multiplicity of shifted and inverted digital samples to produce a second interpolated digital sample; and a multiplexer (111) having first and second inputs respectively coupled to receive said first and second interpolated digital samples, said multiplexer outputting one of said, first and second interpolated digital samples in response to a control signal from said delay control circuit. 6. The beamformer channel as defined in claim 5, wherein each of said first and second adders (112, 115; 113, 115) is a Wallace tree adder. 7. The beamformer channel as defined in claim 2, wherein said interpolator (107) comprises: first and second bit shift and invert circuits (112, 116A-J) respectively coupled to receive said first and second digital samples from said first and second registers (102, 103), each of said first and second bit shift and invert circuits (112, 116A-J) having an output; a first adder (112, 115) having first and second inputs coupled to said outputs of said first and second bit shift and invert circuits (112, 116A-J) respectively and having an output; and a multiplexer (111) having a first input coupled to said output of said first adder (115). 8. The beamformer channel as defined in claim 7, wherein said interpolator further comprises: third and fourth bit shift and invert circuits (113, 116A-J) respectively coupled to receive said first and second digital samples from said first and second registers (102, 103), each of said third and fourth bit shift and invert circuits (113, 116A-J) having an output; 'and - 20 - a second adder (113,115) having first and second inputs coupled to said outputs of said third and fourth bit shift and invert circuits respectively and having an output, wherein said multiplexer (111) has a second input coupled to said output of said second adder. 9. The beamformer channel as defined in claim 8, wherein each of said first and second adders (112, 115; 113, 115) is a Wallace tree adder. 10. A beamformer comprising a multiplicity of beamformer channels (35) and a summer (36) having a multiplicity of inputs respectively coupled to said multiplicity of beamformer channels (35), wherein each of said beamformer channels (35) comprises: analog-to-digital conversion means (54) for outputting digital samples at a sampling rate; an integer sampling period delay circuit (56) having an input coupled to receive said digital samples and having an output; a fractional sampling period delay circuit (58) having an input coupled to receive said digital samples from said integer sampling period delay circuit and having an output coupled to a respective input of said summer; and a delay control circuit (106) coupled to said integer sampling period delay circuit (56) and to said fractional sampling period delay circuit (58) for outputting delay signals which dynamically synchronously control the amount by which said integer sampling period delay circuit and said fractional sampling period delay circuit will respectively delay a signal passing therethrough, wherein said integer sampling period delay circuit (106) comprises a FIFO (101) having an input coupled to receive said digital samples and having an output, and a first register (102) having an input coupled to said output of said FIFO (101) and having an output, said fractional sampling period delay circuit comprises an interpolator having a first input coupled to said output of said first register and said delay control circuit (106) comprises means (108, 110) for holding the contents of said first register to keep said output of said first register synchronized with said output of said FIFO (101) following a change in the amount of delay provided by said FIFO. 11. The beamformer as defined in claim 10, wherein each of said beamformer channels further comprises a second register (103) having an input coupled to said output of said first register and having an output, wherein said interpolator (107) has a second input coupled to said output of said second register and (103) said delay control circuit (106) comprising means for holding the contents of said second register (103) to keep said output of said second register (103) synchronized with said output of said FIFO (101) following said change in the amount of delay provided by said FIFO. 12. The beamformer as defined in claim 11, wherein each of said beamformer channels further comprises a third register (104) having an input coupled to said output of said second register (103) and having an output, and a fourth register (105) having an input coupled to said output of said third register (104) and having an output, wherein said interpolator (107) has third and fourth inputs respectively coupled to said outputs of said third and fourth registers, and said delay control circuit (106) comprising means for 11. - 21 - holding the contents of said third and fourth registers (104, 105) to keep said outputs of said third and fourth registers synchronized with said output of said FIFO (101) following said change in the amount of delay provided by said FIFO. 13. The beamformer as defined in claim 12, wherein said interpolator (107) outputs an interpolated digital sample which is a function of first through fourth digital samples received from said first through fourth registers (102-105) respectively. 14. The beamformer as defined in claim 12, wherein said interpolator (107) comprises: first means (112, 116A-J) for shifting and inverting said first and second digital samples from said first and-second registers (102, 103) in accordance with a first set of interpolation coefficients to produce a first multiplicity of shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second digital samples from said first and second registers in accordance with said first set of interpolation coefficients; a first adder (112, 115) coupled to receive and add said first multiplicity of shifted and inverted digital samples to produce a first interpolated digital sample; second means (113, 116A-J) for shifting and inverting said first and second digital samples from said first and second registers (102, 103) in accordance with a second set of interpolation coefficients to produce a second multiplicity of shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second digital samples from said first and second registers in accordance with said second set of interpolation coefficients; a second adder (113, 115) coupled to receive and add said second multiplicity of shifted and inverted digital samples to produce a second interpolated digital sample; and a multiplexer (111) having first and second inputs respectively coupled to receive said first and second interpolated digital samples, said multiplexer outputting one of said first and second interpolated digital samples in response to a control signal from said delay control circuit (106). 15. The beamformer as defined in claim 14, wherein each of said first and second adders (112,115; 113, 115) is a Wallace tree adder. 16. The beamformer as defined in claim 12, wherein said interpolator (107) comprises: first and second bit shift and invert circuits (112, 116A-J) respectively coupled to receive said first and second digital samples from said first and second registers (102, 103), each of said first and second bit shift and invert circuits having an output; a first adder (112, 115) having first and second inputs coupled to said outputs of said first and second bit shift and invert circuits respectively and having an output; and a multiplexer (111) having a first input coupled to said output of said first adder. 17. The beamformer as defined in claim 16, wherein said interpolator further comprises: third and fourth bit shift and invert circuits (113, 116A-J) respectively coupled to receive said first and second digital samples from said first and second registers (102, 103), each of said third and fourth bit shift and invert circuits (113, 116A-J) having an output; and - 22 - a second adder (113, 115) having first and second inputs coupled to said outputs of said third and fourth bit shift and invert circuits respectively and having an output, wherein said multiplexer (111) has a second input coupled to said output of said second adder. 18. The beamformer as defined in claim 17, wherein each of said first and second adders (112, 115; 113; 115) is a Wallace tree adder. 19. An ultrasonic imaging system comprising a transducer array, a beamformer (35) coupled to said transducer array (10), a signal processor coupled to said beamformer (35), a scan converter (32) coupled to said signal processor, and a display monitor (30) coupled to said scan converter (32), wherein said transducer array comprises a multiplicity of transducer elements (12) and said beamformer (34) comprises a multiplicity of beamformer channels (35), switching circuitry for selectively coupling said beamformer channels (35) to said transducer elements (12), and summing means (34) having a multiplicity of inputs respectively coupled to said multiplicity of beamformer channels, wherein each of said beamformer channels (35) comprises: analog-to-digital conversion means (54) for outputting digital samples at a sampling rate; an integer sampling period delay circuit (56) having an input coupled to receive said digital samples and having an output; a fractional sampling period delay circuit (58) having an input coupled to receive said digital samples from said integer sampling period delay circuit (56) and having an output coupled to a respective input of said summer (36); and a delay control circuit (106) coupled to said integer sampling period delay circuit (56) and to said fractional sampling period delay circuit (58) for outputting delay signals which dynamically synchronously control the amount by which said integer sampling period delay circuit and said fractional sampling period delay circuit will respectively delay a signal passing therethrough, wherein said integer sampling period delay circuit (56) comprises a FIFO (101) having an input coupled to receive said digital samples and having an output, a first register (102) having an input coupled to said output of said FIFO (101) and having an output, and a second register (103) having an input coupled to said output of said first register and having an output, said fractional sampling period delay circuit (58) comprises an interpolator (107) having first and second inputs respectively coupled to said outputs of said first and second registers (102, 103), and said delay control circuit (106) comprises means for holding the contents of said first and second registers (102, 103) to keep said outputs of said first and second registers synchronized with said output of said FIFO (101) following a change in the amount of delay provided by said FIFO. 20. The ultrasonic imaging system as defined in claim 19, wherein said interpolator (107) comprises: first means for shifting and inverting (112, 116A-J) said first and second digital samples from said first and second registers (102, 103) in accordance with a first set of interpolation coefficients to produce a first multiplicity :of shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second - 23 - digital samples from said first and second registers in accordance with said first set of interpolation coefficients; a first adder (112, 115) coupled to receive and add said first multiplicity of shifted and inverted digital samples to produce a first interpolated digital sample; second means for shifting and inverting (113, 116A-J) said first and second digital samples from said first and second registers (102, 103) in accordance with a second set of interpolation coefficients to produce a second multiplicity of shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second digital samples from said first and second registers in accordance with said second set of interpolation coefficients; a second adder (113, 115) coupled to receive and add said second multiplicity of shifted and inverted digital samples to produce a second interpolated digital sample; and a multiplexer (111) having first and second inputs respectively coupled to receive said first and second interpolated digital samples, said multiplexer outputting one of said first and second interpolated digital samples in response to a control signal from said delay control circuit (106). 21. A method of generating a time-delayed digital sample in an ultrasound beamformer (34) corresponding to a digital sample having a time delay which is a fraction of a sampling period, comprising the steps of: acquiring first and second digital samples of an ultrasound receive signal in first and second sampling periods; bit shifting and inverting said first and second digital samples in accordance with a first set of interpolation coefficients to produce a first multiplicity of bit shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second digital samples from first and second registers (102, 103) in accordance with said first set of interpolation coefficients; adding said first multiplicity of bit shifted and inverted digital samples to produce a first interpolated digital sample; bit shifting and inverting said first through fourth digital samples in accordance with a second set of interpolation coefficients to produce a second multiplicity of bit shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second digital samples from said first and second registers (102, 103) in accordance with said second set of interpolation coefficients; adding said second multiplicity of bit shifted and inverted digital samples to produce a second interpolated digital sample; and multiplexing (111) one of said first and second interpolated digital samples to an output. 22. A beamforming channel (35) comprising: analog-to-digital conversion means(54) for outputting digital samples at a sampling rate; a FIFO (101) having an input coupled to receive said digital samples and having an output; - 24 - first through N-th registers (102, 103, 104, 105) connected in series, said first register having an input coupled to said output of said FIFO (101) and having an output, and said N-th register having an input and an output; an interpolator (107) having first through N-th inputs (IN1-IN4) respectively coupled to said outputs of said first through N-th registers; and a delay control circuit (106) coupled to said FIFO (101), to said first through N-th registers and to said interpolator (107) for outputting delay signals which dynamically synchronously control the amount of delay of a signal passing through said FIFO, said registers and said interpolator (107), wherein said delay control circuit (106) comprises means for holding the contents of said first through N-th registers (102-105) to keep said outputs of said first through N-th registers synchronized with said output of said FIFO (101) following a change in the amount of delay provided by said FIFO. 23. The beamformer channel (35) as defined in claim 22, wherein said interpolator (107) comprises: first interpolation means (112, 116A-J) for generating a first interpolated digital sample as a function of outputs from said first through N-th registers into in accordance with a first set of interpolation coefficients; second interpolation means (113, 116A-J) for converting the outputs of said first through N-th registers into a second interpolated digital sample in accordance with a second set of interpolation coefficients; and a multiplexer (111) having first and second inputs respectively coupled to receive said first and second interpolated digital samples, said multiplexer outputting one of said first and second interpolated digital samples in response to a control signal from said delay control circuit (106). 24. The beamformer channel as defined in claim 22, wherein said first interpolation means comprises means (112, 116A-J) for bit shifting the output of said first register as a function of a first interpolation coefficient of said first set of interpolation coefficients. 25. The beamformer channel as defined in claim 24, wherein said first interpolation means further comprises means (112, 116A-J) for inverting said bit-shifted output of said first register as a function of said first interpolation coefficient of said first set of interpolation coefficients. 26. The beamformer channel as defined in claim 22, wherein said first interpolation means comprises: means for bit shifting (112, 116A-J) the outputs of said first through N-th registers as a function of said first set of interpolation coefficients; means for inverting (112, 116A-J) at least some of said bit-shifted outputs as a function of said first set of interpolation coefficients to produce a plurality of values; and means (112, 115) for adding said values to produce said first interpolated digital sample. 27. The beamformer channel as defined in claim 26, wherein said adding.means (112, 115) comprises a Wallace tree adder. Dated this 11th day of November, 1997 A phased array sector scanning ultrasonic system includes a separate receive channel for each respective element- in an ultrasonic transducer array. Each receive channel inparts at delay to the echo signal produced by each respective element The delayed echo signals are summed to form a steered, dynamically focused and dynamically windowed receive beam even when the transmit beam does not emanate from the center of the array. The receiver has a beamformer including a multiplicity of beamformer channels 35% The beamformer dynamically increases delays to each channel without introducing unwanted discontinuities, by combing and synchronizing a FIFO and an interpolator. The interpolator uses "Wallace tree" adders to accumulate bit-shifted versions of the inputs. The number of additions is less than the number of bits which would be needed to represent equivalent coefficients. This reduces the hardware relative to a conventional implementation which incorporates multipliers with shifts and adds equaling the number of bits in the coefficients.

Full Text

METHOD AND APPARATUS FOR PROVIDING
DYNAMICALLY VARIABLE TIME DELAYS
FOR ULTRASOUND BEAMFORMER
Field of the Invention
This invention generally relates to ultrasound imaging systems which form ultrasonic beams by time delay and summation of return signals in a multiplicity of parallel channels. In particular, the invention relates to means for providing the required beamforming delays to channel processing.
Background of the Invention
Conventional ultrasound imaging systems comprise an array of ultrasonic transducers which are used to transmit an ultrasound beam and then receive the reflected beam from the object being studied. For ultrasound imaging, the array typically has a multiplicity of transducers arranged in a line and driven with separate voltages. By selecting the time delay (or phase) and amplitude of the applied voltages, the individual transducers can be controlled to produce ultrasonic waves which combine to form a net ultrasonic wave that travels along a preferred vector direction and is focused at a selected point along the beam. Multiple firings may be used to acquire data representing the same anatomical information. The beamforming parameters of each of the firings may be varied to provide a change in maximum focus or otherwise change the content of the received data for each firing, e.g., by transmitting successive beams along the same scan line with the focal point of each beam being shifted relative to the focal

-2-
point of the previous beam. By changing the time delay and amplitude of the applied voltages, the beam with its focal point can be moved in a plane to scan the object.
The same principles apply when the transducer is employed to receive the reflected sound (receiver mode). The voltages produced at the receiving transducers are summed so that the net signal is indicative of the ultrasound reflected from a single focal point in the object. As with the transmission mode, this focused reception of the ultrasonic energy is achieved by imparting separate time delay (and/or phase shifts) and gains to the signal from each receiving transducer.
Such scanning comprises a series of measurements in which the steered ultrasonic wave is transmitted, and the reflected ultrasonic wave is received and stored. Typically, transmission and reception are steered in the same direction during each measurement to acquire data from a series of points, along an acoustic beam or scan line. The receiver is dynamically focused at a succession of ranges along the scan line as the reflected ultrasonic waves are received.
An ultrasound image is composed of multiple image scan lines. A single scan line (or small localized group of scan lines) is acquired by transmitting focused ultrasound energy at a point in the region of interest, and then receiving the reflected energy over time. The focused transmit energy is referred to as a transmit beam. During the time after transmit, one or more receive beamformers coherently sum the energy received by each channel, with dynamically changing phase rotation or delays, to produce peak sensitivity along the desired scan lines at ranges proportional to the elapsed time. The resulting focused sensitivity pattern is referred to as a receive beam. A scan line's resolution is a result of the directivity of the associated transmit and receive beam pair.

-3-
Scan lines are defined by their position and angle. The intersection of a beam with the transducer face is referred to as the phase center. The angle of a scan line relative to orthogonal is referred to as the steering angle.
Beamforming delays may be fixed or dynamic. Transmit delays are fixed to provide peak pressure at - a particular range. Receive delays are typically dynamic since the peak sensitivity must track the increasing range r of reflections as a function of elapsed time t:
(1)
where c is the speed of sound in the imaged media. The elapsed time may be quantized by an amount ##r, which is equivalent to quantized focal ranges:
(2)
The geometry used herein is shown in FIGS. 1A and 1B for linear/sector and curved linear transducers, respectively. The important reference points are the phase center, focal point and element position. The phase center will always be the origin of the (x,z) Cartesian coordinate system. The focal point is r and the element position is pi. For curved arrays the element position is determined by the radius of curvature p and the channel angle ##*j = lip, where li is the distance from phase center along the face of the probe.
The beamformer must compensate for channel to channel differences in the propagation time Tp of sound traveling between phase center and pi via a reflector at r. The relative delay Td is the difference between the propagation time for channel i and the propagation time for the phase center. For the geometry in FIG. 1A, the times Tp and Td are as follows:

-4-
Referring to FIG. 2, a conventional ultrasound imaging system includes a transducer array 10 comprised of a plurality of separately driven transducer elements 12, each of which produces a burst of ultrasonic energy when energized by a pulsed waveform produced by a transmitter 22. The ultrasonic energy reflected back to transducer array 10 from the object under study is converted to an electrical signal by each receiving transducer element 12 and applied separately to a receiver 24 through a set of transmit/receive (T/R) switches 26. The T/R switches 2 6 are typically diodes which protect the receive electronics from the high voltages generated by the transmit electronics. The transmit signal causes the diodes to shut off or limit the signal to the receiver. Transmitter 2 2 and receiver 24 are operated under control of a scan controller 28 responsive to commands by a human operator. A complete scan is performed by acquiring a series of echoes in which transmitter 22 is gated ON momentarily to energize each transducer element 12, and the subsequent echo signals produced by each transducer element 12 are applied to receiver 24. A channel may begin reception while another channel is still transmitting. The receiver 24 combines the separate echo signals from each transducer element to produce a single echo signal which is used to produce a line in an image on a display monitor 30.

-5-
Transmitter 22 drives transducer array 10 such that the ultrasonic energy produced is directed, or steered, in a beam. To accomplish this, transmitter 22 imparts a time delay to the respective pulsed waveforms W. that are applied to successive transducer elements 12 via respective beamformer channels. Each channel has a respective pulser associated therewith. By adjusting the pulse time delays appropriately in a conventional manner, the ultrasonic beam can be directed away from axis 36 by an angle ##8 and/or focused at a fixed range R. A sector scan is performed by progressively changing the time delays in successive excitations. The angle ##$ is thus changed in increments to steer the transmitted beam in a succession of directions.
The echo signals produced by each burst of ultrasonic energy reflect from objects located at successive ranges along the ultrasonic beam. The echo signals are sensed separately by each transducer element 12 and the magnitude of the echo signal at a particular point in time represents the amount of reflection occurring at a specific range. Due to the differences in the propagation paths between a reflecting point P and each transducer element 12, however, these echo signals will not be detected simultaneously and their amplitudes will not be equal. Receiver 24 amplifies the separate echo signals, imparts the proper time delay to each, and sums them to provide a single echo signal which accurately indicates the total ultrasonic energy reflected from point P located at range R along the ultrasonic beam oriented at the angle ##0.
To simultaneously sum the electrical signals produced by the echoes impinging on each transducer element 12, time delays are introduced into each separate beam-former channels of receiver 24. The beam time delays for reception are the same delays as the transmission delays described above. However, the time delay of each

-6-
receiver channel is continuously changing during reception of the echo to provide dynamic focusing of the received beam at the range R from which the echo signal emanates.
Under the direction of scan controller 28, receiver. 24 provides delays during the scan such that steering of receiver 2 4 tracks the direction ##6 of the beam steered by transmitter 2 2 and provides the proper delays and phase shifts to dynamically focus at points P along the beam. Thus, each transmission of an ultrasonic pulse waveform results in the acquisition of a signal with a magnitude which represents the amount of reflected sound from anatomy located along the ultrasonic beam.
A detector 25 converts the received signal to display data. in the B-mode (greyscale) , this would be the envelope of the signal with some additional processing such as edge enhancement and logarithmic compression.
Scan converter/interpolator 32 receives the display data from detector 25 and converts the data into the desired image for display. In particular, the scan converter converts the acoustic image data from polar coordinate (R-##6) sector format or Cartesian coordinate linear array to appropriately scaled Cartesian coordinate display pixel data at the video rate. This scan-converted acoustic data is then output for display on display monitor 30, which images the time-varying amplitude of the envelope of the signal as a grey scale.
Referring to FIG. 3, the receiver comprises a receive beamforming section 34 and a signal processor 38. The receive beamforming section 34 of receiver 24 includes separate beamformer channels 35. Each beam-former channel 35 receives the analog echo signal from a respective transducer element. The beamformer controller 50 converts scan line and transmit focus numbers to addresses into a channel control memory (not shown). The scan controller 28 (FIG. 2) and beamformer control-

-7-

ler 50 (FIG. 3) are loaded by the system host CPU in response to user actions such as changing the display format or connecting a different ultrasound probe.
As seen in FIG. 4, each beamformer channel 35 comprises a receive channel and a transmit channel, each, channel incorporating delay means 40 and 42 respectively, which are controlled to provide the needed beamform-ing delays by receive control logic 44 and transmit control logic 46 respectively. Transmit is typically done by using a counter to delay the start of transmit pulse generation. Some systems may also apply relative phase rotations in addition to, or in place of, delays for receive. The receive channels also have circuitry 48 for apodizing and filtering the receive pulses.
The signals entering the summer 3 6 (see FIG. 3) have been delayed so that when they are summed with delayed signals from each of the other beamformer channels 35, the summed signals indicate the magnitude and phase of the echo signal reflected from anatomy located along the steered beam (##$) . Signal processor 38 receives the beam samples from the summer 3 6 and produces an output to scan converter 3 2 (see FIG. 2).
In accordance with the foregoing conventional time-delay digital beamforming system, each signal processing channel 35 comprises an analog-to-digital converter (ADC) and a FIFO which is controlled to provide integer time delays. The ADC and FIFO inputs are driven with asynchronous clocks to produce variable delays. Extra clock cycles are inserted when necessary to increase the FIFO depth. This degrades the performance of the ADCs and presents many implementation difficulties due to timing.
Other prior art digital beamformers interpolate the data to a higher sampler rate before entering the FIFO. This increases the required size of the FIFO.

-8-
Yet, other prior art digital beamformers interpolate the output of the FIFO. Dynamic changes in the delay of the FIFO create discontinuities at the input to the interpolator, degrading the interpolator per- formance.
Summary of the Invention
The present invention is an apparatus for generat-ing the required beamforming delays for an ultrasound imaging system with minimal hardware and software. In particular, the invention--is a method for providing dynamically variable time delays with sub-sample rate precision in an ultrasound beamformer.
Receive beamforming for a high-performance ultrasound imaging system requires time delay precision on the order of 5 nsec. However the receive signal may be fully represented, digitally, with much lower sample periods: such as 40 MHz for a real signal or 10 MHz after demodulation and/or filtering. The present invention provides dynamically variable delays with a precision which is a fraction of the sample period, without increasing the actual sample rate. The fractional delays are provided through the use of an interpolator running at the input sample rate.
To maintain focus during reception, ultrasound beamformer must dynamically increase delays to each channel. The present invention provides the required dynamic delay without introducing unwanted discontinuities, by combining and synchronizing a FIFO and an interpolator.
The preferred embodiment of the interpolator uses "Wallace tree" adders to accumulate bit-shifted versions of the inputs. The number of additions is less than the number of bits which would be needed to represent equivalent coefficients. This reduces the hardware relative to a conventional implementation which incorporates

-9-
multipliers with shifts and adds equaling the number of bits in the coefficients.
Another feature of the preferred embodiment is that its performance is adequate over the complete range of input frequencies conventionally utilized for medical imaging, while allowing for degradation outside of that frequency range. It does not require modification when the input signal changes frequency. This feature is optional: some embodiments may include frequency-dependent configurations.
Brief Description of the Drawings
FIGS. 1A and 1B are diagrams showing the beamform-ing geometry for linear/sector and curved linear transducers respectively.
FIG. 2 is a block diagram showing the major functional subsystems within a conventional real-time ultrasound imaging system.
FIG. 3 is a block diagram of a typical 128-channel beamformer for the system depicted in FIG. 2.
FIG. 4 is a block diagram of the channel processing in the conventional beamformer depicted in FIG. 3.
FIG. 5 is a block diagram of a receive signal processing channel in accordance with the present invention.
FIG. 6 is a graph showing the four-point cubic interpolation frequency response of an interpolation filter in accordance with the invention.
FIGS. 7A and 7B are graphs showing the magnitude response and group delay, respectively, for an interpolation filter in accordance with the invention.
FIG. 8 is a block diagram showing the dynamic beam-forming delay logic in accordance with the preferred embodiment of the invention.
FIG. 9 is a block diagram showing the delay control logic incorporated in the dynamic beamforming delay

-10-
logic depicted in FIG. 8.
FIG. 10 is a block diagram showing the interpolator incorporated in the dynamic beamforming delay logic depicted in FIG. 8 in accordance with one preferred embodiment of the invention.
FIG. 11 is a block diagram showing further details of a representative shift and add block incorporated in the interpolator depicted in FIG. 10.
FIG. 12 is a block diagram showing the interpolator incorporated in the dynamic beamforming delay logic depicted in FIG. 8 in accordance with another preferred embodiment of the invention.
Detailed Description of the Preferred Embodiments
Referring to FIG. 5, each receive signal processing channel 3 5 in accordance with the present invention comprises an amplifier 52 which amplifies the signal detected by a respective ultrasound transducer element; an analog-to-digital converter 54 which converts the amplified analog signal into a stream of digital samples at a sampling rate (e.g., each digital sample having 8 bits); an integer sample period delay circuit 56 for delaying the digital samples by a time interval equal to an integer number of sample periods; and a fractional sample period delay circuit 58 for delaying the digital samples by a time interval equal to a fraction of the sample period. The outputs of the respective fractional sample period delay circuits for each processing channel are then summed in the summer 36, shown in FIG. 3.
In accordance with the present invention, the integer sample period delay circuit comprises a dynamic FIFO 101 and a series of clocked pipeline registers 102-105 (see FIG. 8), while the fractional sample period delay circuit comprises an interpolator 107. Parallel receive beamforming could be supported by having multiple read locations from each FIFO. An alternative would be to

-11-
have separate FIFOs for each receive beam.
In accordance with the broad concept of the invention, the dynamic FIFOs provide range-dependent time delay to support broadband beamforming. The FIFOs support a 40-MHz sample rate providing a "coarse" delay, accuracy of ±12.5 nsec. The initial lengths of the FIFOs are controlled by multiple-bit control fields called "initial receive delay". When a delay increment machine (not shown) requests a FIFO delay increment, the FIFO length is increased at the output with a repetition or "hold" of the output sample, i.e., the output data does not change from the previous 40 MHz clock tick.
In accordance with the invention, one interpolator is required for each receive beam. The interpolator provides the "fine" delay adjustment by interpolating between samples from the FIFO. In accordance with one preferred embodiment, the interpolator interpolates between four samples from the FIFO to produce a delay of 2.75, 2.5, 2.25 or 2.0 25-nsec clock periods. This provides a delay accuracy of ±3.125 nsec. The interpolator coefficients in accordance with the preferred embodiment are listed in Table 1.

TABLE
1
Coefficients
Breakdown
-20
-(16+4)
-31
-32+1
-28
-32+4
0
0
74
64+8+2
152
128+32-8
220
256-32-4
256
256
220
256-32-4
152
128+32-8
74
64+8+2
0
0
-28
-32+4
-31
-32 + 1
-20
-(16+4)
0
0

-12-
These coefficients are all simple combinations of powers of 2, scaled by 256. To obtain a delay of 2.75, the 1st, 5th, 9th and 13th coefficients are used; to obtain a delay of 2.5, the 2nd, 6th, 10th and 14th coefficients are used; and so on.
The delay counter 106 (see FIG. 8) associated with each beam selects the interpolation coefficients and indicates when a FIFO delay increase is required. When a FIFO delay increase "holds" the FIFO output, the interpolator data must also be held.
An example is shown in Table 2, where each row represents a 4 0 MHz clock tick. The first column indicates the desired dynamic delay in units of 40 MHz clock ticks, starting in the first row at 5.0. The interpolator provides the fractional portion of this delay, with two additional integer delays. The next four columns are the content of the interpolator input buffers, and the last four columns are the coefficients used. A FIFO delay increment is required in the last row, thus s(25) is held at the output of the FIFO, as well as all the data in the interpolator input buffer.

TABLE
; 2

Time
Delay
Interpolator
Input Buffer
Interpolator Coefficients
10.0
5.0
8(6)
8(5)
s(4)
8(3)
0
256
0
0
11.0
5.0
8(7)
8(6)
8(5)
8(4)
0
256
0
0
12.0
5.0
8(8)
8(7)
s(6)
8(5)
0
256
0
0
13.0
5.0
8(9)
s(8)
s{7)
8(6)
0
256
0
0
14.0
5.25
8(10)
8(9)
8(8)
8(7)
-28
220
74
-20
15.0
5.25
8(11)
8(10)
8(9)
8(8)
-28
220
74
-20
16.0
5.25
8(12)
8(11)
8(10)
8(9)
-28
220
74
-20
17.0
5.25
8(13)
8(12)
s(ll)
8(10)
-28
220
74
-20
18.0
5.5
8(14)
8(13)
s(12)
8(11)
-31
152
152
-31
19.0
5.5
S(1S)
8(14)
a(13)
8(12)
-31
152
152
-31
20.0
5.5
8(16)
8(15)
s(14)
a(13)
-31
152
152
-31
21.0
5.5
8(17)
8(16)
6(15)
8(14)
-31
152
152
-31
22.0
5.5
8(18)
8(17)
s(16)
8(15)
-31
152
152
-31
23.0
5.5
8(19)
a(18)
8(17)
8(16)
-31
152
152
-31
24.0
5.5
s(20)
8(19)
8(18)
8(17)
-31
152
152
-31
25.0
5.5
8(21)
8(20)
8(19)
8(18)
-31
152
152
-31
26.0
5.75
8(22)
8(21)
s(20)
8(19)
-20
74
220
-28
27.0
5.75
8(23)
s{22)
8(21)
s(20)
-20
74
220
-28
28.0
5.75
8(24)
s
s(22)
8(21)
-20
74
220
-28
29.0
5.75
s(25)
s(24)
B(23>
s(22)
-20
74
220
-28
30.0
6.0
S(25)
s(24)
s(23)
s(22)
0
256
0
0
31.0
6.0
8(26)
8(25)
s(24)
s(23)
0
256
0
0

-13-
Interpolation is equivalent to applying a linear time-invariant filter to a zero-filled signal. The zero-filled signal represents the sampled input signal with zeros between the known sample values. The spectrum of the zero-filled, sampled signal has high-fre-. quency images of the input spectrum at harmonics of the sample rate. The interpolation filter passes the spectrum of the input signal while attenuating all the images. These images are above the array design frequency as determined by the interelement spacing. Thus, they produce grating lobes. The relative level of these grating lobes is determined by the stopbands of the interpolation filter around the sample rate harmonics.
The filter coefficients for this design are listed in Table 1. The frequency response of this interpolation filter is shown in FIG. 6. It has a -3 dB passband to greater than 13 MHz, and -35 dB stopbands around 40, 80, and 120 MHz, each 26 MHz wide. Thus a CW signal would have grating lobes at -35 dB in the worst case. The grating lobes of a typical signal are much lower. A worst case example would be a 20-cycle PW Doppler burst on a 40-channel aperture. The first grating lobe will be attenuated an additional -6 dB, making the overall level less than -40 dB.
Another way to look at the interpolator is as a selection of all-pass filters with different group delays. This approach may be more intuitive since it is closer to the actual implementation. In this design, four coefficients are applied according to the desired fractional delay. Since there are four fractional delays available, there are four sets of four coefficients, each with an associated group delay and magnitude response. FIGS. 7A and 7B shows the responses for the coefficients listed in Table 1. The magnitude response is flat to ±0.5 dB out to 13 MHz, and the group delay is correct to within 3.25 nsec out to 13 MHz.

-14-
While this approach provides insight into the resulting accuracy, it does not lead to an estimate of beamforming performance (i.e. grating lobe levels), as directly as the first approach. Compared to cordic rotation or linear interpolation, this approach provides better-performance and/or less hardware in all modes.
In accordance with a preferred embodiment of the invention shown in FIG. 8, dynamic beamforming delays are provided by FIFO 101, pipeline registers 102-105, and interpolator 107. The FIFO 101 provides delays that are an integer number of sample clock (SCLK) periods. Registers 102 and 103, provide an additional delay of two sample periods, to IN2, the nominal center input of the interpolator 107. The interpolator 107 provides an additional fractional delay between the center two (IN2 and IN3) input samples. Although a four-sample interpolator is shown, the invention may be generalized to use Q input samples from Q registers, where Q is an integer equal to 2 or more. The input registers would then provide Q/2 sample periods of delay, while the interpolator interpolated between the .center two inputs.
The dynamic beamforming delay logic shown in FIG. 8 has a delay counter 106 which controls FIFO 101, registers 102-105, and interpolator 107 in a synchronous manner. The overall delay may be increased in response to a "Delay Increment" signal from a delay increment machine (not shown) , at each tick of a control clock (CCLK). The delay counter 106, shown in FIG. 9, outputs a fractional delay index and an overflow bit. In the general case where the interpolator 107 provides a selection of L fractional delays from 0 to (L - 1) /L sample periods, then the index is M - log2L bits. Each time CCLK ticks with "Delay Increment" set, the delay counter accumulator 108 increments to select the next fractional delay. When overflowing from (L - 1) to 0, the overflow logic 110 sets the overflow bit for one

-15-
SCLK period to disable reading the FIFO 101 via REN and clocking the registers via CE. REN stops the read of the FIFO while continuing, to write, producing an extra sample of FIFO delay per SCLK tick. One SCLK tick of REN increases the FIFO delay one sample period. CE holds the contents on the interpolator input registers to keep them synchronized with the FIFO output, with the nearest four samples to the desired output. This happens simultaneously with the interpolator delay switching from (L - 1)/L to 0 fractional delay, producing the desired net increase of 1/L fractional delays without discontinuity. This is illustrated in Table 2.
To meet practical timing constraints, CCLK must have the proper relationship to SCLK. The CCLK trigger edge must occur early enough to allow the REN" and CE control inputs to setup before the SCLK trigger edge. In general, the CCLK may run at a slower rate than the SCLK. The CCLK frequency fc only needs to be high enough to keep up with the rate that the beamforming delays must change over range.
A good approximation is:

(7)

where fs is the SCLK frequency, fn is the minimum receive f-number, and $ is the maximum steering angle relative to broadside. A system which has a minimum receive f-number of 1.5, a maximum steering angle of 45 degrees, a sample rate of 40 MHz, and an interpolation ratio L of 4, requires a 10 MHz control clock.
The interpolator may be a conventional interpolator such as described in the prior art; however, the preferred embodiment is shown in FIG. 10. A multiplexer 111 selects one of the L fractional delays according to the index from delay counter 106 (see FIG. 8). If the index is zero, the sample from the second (0/2) input

-16-
register is passed to the output directly. Otherwise, the output of one of (L - 1) shift and add blocks 112 through 114 is used.
An advantage of the foregoing method is that no multipliers are needed; only shifts, inversions and one-Wallace tree adder are needed per shift and add block (see FIG. 11)• The bit shifters require no control or active circuitry; the shifts are simply performed by shifting the bit connections. Inversion is very simple, and a Wallace tree adder is the must efficient VLSI design for adding many values. In the preferred embodiment shown in FIG. 11, the first input sample is shifted/inverted in two ways in respective blocks 116A, 116B; the second input sample is shifted/inverted in three ways in respective blocks 116C-116E; the third input sample is shifted/ inverted in three ways in respective blocks 116F-116H; and the fourth input sample is shifted/inverted in two ways in respective blocks 1161, 116J. For example, to obtain a delay of 2.75, the 1st, 5th, 9th and 13th coefficients listed in Table 1 are broken down and used as follows: input IN1 to shift/invert block 116A is shifted by 4 bits and inverted (i.e., equivalent to multiplication by -16); input IN1 to shift/invert block 116B is shifted by 2 bits and inverted (i.e., equivalent to multiplication by -4); input IN2 to shift/invert block 116C is shifted by 6 bits (i.e., equivalent to multiplication by 64); input IN2 to shift/invert block 116D is shifted by 3 bits (i.e., equivalent to multiplication by 8); input IN2 to shift/invert block 116E is shifted by 1 bit (i.e., equivalent to multiplication by 2); input IN3 to shift/invert block 116F is shifted by 8 bits (i.e., equivalent to multiplication by 256); input IN3 to shift/invert block 116G is shifted by 5 bits and inverted (i.e., equivalent to multiplication by -32); input IN3 to shift/invert block 116H is shifted by 2

-17-
bits and inverted (i.e., equivalent to multiplication by -4); input IN4 to shift/invert block 1161 is shifted by 6 bits and inverted (i.e., equivalent to multiplication by -32); and input IN4 to shift/invert block 116J is shifted by 2 bits (i.e., equivalent to multiplication-by 4). All shifted/inverted samples are then supplied to a Wallace tree adder 115 for summing, e.g., -20(IN1) + 74(IN2) + 220(IN3) - 28(IN4). This is equivalent to interpolating with coefficients that are limited to the sum or difference of two or three powers of 2, i.e., ±2shift. More powers of two can be used for better performance.
An alternate approach takes advantage of the symmetry of the interpolation coefficients. Coefficients for the i/L fractional delay are just reversed in order from coefficients for the (L - i) /L delay, where i Proper selection of the shifts and inversions, i.e., coefficients, can provide adequate performance across the entire ultrasound imaging band.
The foregoing preferred embodiments have been disclosed for the purpose of illustration. Variations and modifications will be readily apparent to those skilled in the art of beamforming for ultrasound imaging. All such variations and modifications are intended to be encompassed by the claims set forth hereinafter.

-18-
WE CLAIM:
1. A beamforming channel (35) comprising analog-to-digital conversion means (54) for
outputting digital samples at a sampling rate, an integer sampling period delay circuit
(56) having an input coupled to receive said digital samples and having an output, a
fractional sampling period delay circuit (58) having an input coupled to receive said
digital samples from said integer sampling period delay circuit (56) and having an output,
and a delay control circuit (106) coupled to said integer sampling period delay circuit
(56) and to said fractional sampling period delay circuit (58) for outputting delay signals
which dynamically synchronously control the amount by which said integer sampling
period delay circuit (56) and said fractional sampling period delay circuit (58) will
respectively delay a signal passing therethrough, wherein said integer sampling period
delay circuit (56) comprises a FIFO (101) having an input coupled to receive said digital
samples and having an output, and a first register (102) having an input coupled to said
output of said FIFO (101) and having an output, said fractional sampling period delay
circuit comprises an interpolator (107) having a first input (IN1) coupled to said output of
said first register (102) and said delay control circuit comprises means (108, 110) for
holding the contents of said first register (102) to keep said output of said first register
(102) synchronized with said output of said FIFO (101) following a change in the
amount of delay provided by said FIFO (101).
2. The beamformer channel as defined in claim 1, further comprising a second register
(103) having an input coupled to said output of said first register (102) and having an
output, wherein said interpolator (107) has a second input (IN2) coupled to said output of
said second register (103) and said delay control circuit (106) comprising means (108,
110) for holding the contents of said second register (103) to keep said output of said second register (103) synchronized with said output of said FIFO (101) following said change in the amount'of delay provided by said FIFO (101).
3. The beamformer channel as defined in claim 2, further comprising a third register
(104) having an input coupled to said output of said second register (103) and having an
output, and a fourth register (105) having an input coupled to said output of said third
register and having an output, wherein said interpolator has third and fourth inputs (IN3,
IN4) respectively coupled to said outputs of said third and fourth registers (104, 105), and
said delay control circuit (106) comprising means (108, 110) for holding the contents of
said third and fourth registers (104, 105) to keep said outputs of said third and fourth
registers synchronized with said output of said FIFO (101) following said change in the
amount of delay provided by said FIFO.
4. The beamformer channel as defined in claim 2, wherein said interpolator (107) outputs
an interpolated digital sample which is a function of first and second digital samples

- 19 -
received from said first and second registers (102, 103) respectively.
5. The beamformer channel as defined in claim 2, wherein said interpolator (107) comprises:
first means for shifting and inverting (112, 116A-J) said first and second digital samples from said first and second registers (102, 103) in accordance with a first set of interpolation coefficients to produce a first multiplicity of shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second digital samples from said first and second registers (102, 103) in accordance with said first set of interpolation coefficients;
a first adder (112, 115) coupled to receive and add said first multiplicity of shifted and inverted digital samples to produce a first interpolated digital sample;
second means (113, 116A-J) for shifting and inverting said first and second digital samples from said first and second registers in accordance with a second set of interpolation coefficients to produce a second multiplicity of shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second digital samples from said first and second registers in accordance with said second set of interpolation coefficients;
a second adder (113, 115) coupled to receive and add said second multiplicity of shifted and inverted digital samples to produce a second interpolated digital sample; and
a multiplexer (111) having first and second inputs respectively coupled to receive said first and second interpolated digital samples, said multiplexer outputting one of said, first and second interpolated digital samples in response to a control signal from said delay control circuit.
6. The beamformer channel as defined in claim 5, wherein each of said first and second
adders (112, 115; 113, 115) is a Wallace tree adder.
7. The beamformer channel as defined in claim 2, wherein said interpolator (107)
comprises:
first and second bit shift and invert circuits (112, 116A-J) respectively coupled to receive said first and second digital samples from said first and second registers (102, 103), each of said first and second bit shift and invert circuits (112, 116A-J) having an output;
a first adder (112, 115) having first and second inputs coupled to said outputs of said first and second bit shift and invert circuits (112, 116A-J) respectively and having an output; and
a multiplexer (111) having a first input coupled to said output of said first adder (115).
8. The beamformer channel as defined in claim 7, wherein said interpolator further
comprises:
third and fourth bit shift and invert circuits (113, 116A-J) respectively coupled to receive said first and second digital samples from said first and second registers (102, 103), each of said third and fourth bit shift and invert circuits (113, 116A-J) having an output; 'and

- 20 -
a second adder (113,115) having first and second inputs coupled to said outputs of said third and fourth bit shift and invert circuits respectively and having an output,
wherein said multiplexer (111) has a second input coupled to said output of said second adder.
9. The beamformer channel as defined in claim 8, wherein each of said first and second
adders (112, 115; 113, 115) is a Wallace tree adder.
10. A beamformer comprising a multiplicity of beamformer channels (35) and a summer
(36) having a multiplicity of inputs respectively coupled to said multiplicity of
beamformer channels (35), wherein each of said beamformer channels (35) comprises:
analog-to-digital conversion means (54) for outputting digital samples at a sampling rate;
an integer sampling period delay circuit (56) having an input coupled to receive said digital samples and having an output;
a fractional sampling period delay circuit (58) having an input coupled to receive said digital samples from said integer sampling period delay circuit and having an output coupled to a respective input of said summer; and
a delay control circuit (106) coupled to said integer sampling period delay circuit (56) and to said fractional sampling period delay circuit (58) for outputting delay signals which dynamically synchronously control the amount by which said integer sampling period delay circuit and said fractional sampling period delay circuit will respectively delay a signal passing therethrough,
wherein said integer sampling period delay circuit (106) comprises a FIFO (101) having an input coupled to receive said digital samples and having an output, and a first register (102) having an input coupled to said output of said FIFO (101) and having an output, said fractional sampling period delay circuit comprises an interpolator having a first input coupled to said output of said first register and said delay control circuit (106) comprises means (108, 110) for holding the contents of said first register to keep said output of said first register synchronized with said output of said FIFO (101) following a change in the amount of delay provided by said FIFO.
11. The beamformer as defined in claim 10, wherein each of said beamformer channels
further comprises a second register (103) having an input coupled to said output of said
first register and having an output, wherein said interpolator (107) has a second input
coupled to said output of said second register and (103) said delay control circuit (106)
comprising means for holding the contents of said second register (103) to keep said
output of said second register (103) synchronized with said output of said FIFO (101)
following said change in the amount of delay provided by said FIFO.
12. The beamformer as defined in claim 11, wherein each of said beamformer channels
further comprises a third register (104) having an input coupled to said output of said
second register (103) and having an output, and a fourth register (105) having an input
coupled to said output of said third register (104) and having an output, wherein said
interpolator (107) has third and fourth inputs respectively coupled to said outputs of said
third and fourth registers, and said delay control circuit (106) comprising means for
11.
- 21 -
holding the contents of said third and fourth registers (104, 105) to keep said outputs of said third and fourth registers synchronized with said output of said FIFO (101) following said change in the amount of delay provided by said FIFO.
13. The beamformer as defined in claim 12, wherein said interpolator (107) outputs an
interpolated digital sample which is a function of first through fourth digital samples
received from said first through fourth registers (102-105) respectively.
14. The beamformer as defined in claim 12, wherein said interpolator (107) comprises:
first means (112, 116A-J) for shifting and inverting said first and second digital samples from said first and-second registers (102, 103) in accordance with a first set of interpolation coefficients to produce a first multiplicity of shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second digital samples from said first and second registers in accordance with said first set of interpolation coefficients;
a first adder (112, 115) coupled to receive and add said first multiplicity of shifted and inverted digital samples to produce a first interpolated digital sample;
second means (113, 116A-J) for shifting and inverting said first and second digital samples from said first and second registers (102, 103) in accordance with a second set of interpolation coefficients to produce a second multiplicity of shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second digital samples from said first and second registers in accordance with said second set of interpolation coefficients;
a second adder (113, 115) coupled to receive and add said second multiplicity of shifted and inverted digital samples to produce a second interpolated digital sample; and
a multiplexer (111) having first and second inputs respectively coupled to receive said first and second interpolated digital samples, said multiplexer outputting one of said first and second interpolated digital samples in response to a control signal from said delay control circuit (106).
15. The beamformer as defined in claim 14, wherein each of said first and second adders
(112,115; 113, 115) is a Wallace tree adder.
16. The beamformer as defined in claim 12, wherein said interpolator (107) comprises:
first and second bit shift and invert circuits (112, 116A-J) respectively coupled to receive said first and second digital samples from said first and second registers (102, 103), each of said first and second bit shift and invert circuits having an output;
a first adder (112, 115) having first and second inputs coupled to said outputs of said first and second bit shift and invert circuits respectively and having an output; and
a multiplexer (111) having a first input coupled to said output of said first adder.
17. The beamformer as defined in claim 16, wherein said interpolator further comprises:
third and fourth bit shift and invert circuits (113, 116A-J) respectively coupled to receive said first and second digital samples from said first and second registers (102, 103), each of said third and fourth bit shift and invert circuits (113, 116A-J) having an output; and

- 22 -
a second adder (113, 115) having first and second inputs coupled to said outputs of said third and fourth bit shift and invert circuits respectively and having an output,
wherein said multiplexer (111) has a second input coupled to said output of said second adder.
18. The beamformer as defined in claim 17, wherein each of said first and second adders
(112, 115; 113; 115) is a Wallace tree adder.
19. An ultrasonic imaging system comprising a transducer array, a beamformer (35)
coupled to said transducer array (10), a signal processor coupled to said beamformer (35),
a scan converter (32) coupled to said signal processor, and a display monitor (30) coupled
to said scan converter (32), wherein said transducer array comprises a multiplicity of
transducer elements (12) and said beamformer (34) comprises a multiplicity of
beamformer channels (35), switching circuitry for selectively coupling said beamformer
channels (35) to said transducer elements (12), and summing means (34) having a
multiplicity of inputs respectively coupled to said multiplicity of beamformer channels,
wherein each of said beamformer channels (35) comprises:
analog-to-digital conversion means (54) for outputting digital samples at a sampling rate;
an integer sampling period delay circuit (56) having an input coupled to receive said digital samples and having an output;
a fractional sampling period delay circuit (58) having an input coupled to receive said digital samples from said integer sampling period delay circuit (56) and having an output coupled to a respective input of said summer (36); and
a delay control circuit (106) coupled to said integer sampling period delay circuit (56) and to said fractional sampling period delay circuit (58) for outputting delay signals which dynamically synchronously control the amount by which said integer sampling period delay circuit and said fractional sampling period delay circuit will respectively delay a signal passing therethrough,
wherein said integer sampling period delay circuit (56) comprises a FIFO (101) having an input coupled to receive said digital samples and having an output, a first register (102) having an input coupled to said output of said FIFO (101) and having an output, and a second register (103) having an input coupled to said output of said first register and having an output, said fractional sampling period delay circuit (58) comprises an interpolator (107) having first and second inputs respectively coupled to said outputs of said first and second registers (102, 103), and said delay control circuit (106) comprises means for holding the contents of said first and second registers (102, 103) to keep said outputs of said first and second registers synchronized with said output of said FIFO (101) following a change in the amount of delay provided by said FIFO.
20. The ultrasonic imaging system as defined in claim 19, wherein said interpolator (107) comprises:
first means for shifting and inverting (112, 116A-J) said first and second digital samples from said first and second registers (102, 103) in accordance with a first set of interpolation coefficients to produce a first multiplicity :of shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second

- 23 -

digital samples from said first and second registers in accordance with said first set of interpolation coefficients;
a first adder (112, 115) coupled to receive and add said first multiplicity of shifted and inverted digital samples to produce a first interpolated digital sample;
second means for shifting and inverting (113, 116A-J) said first and second digital samples from said first and second registers (102, 103) in accordance with a second set of interpolation coefficients to produce a second multiplicity of shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second digital samples from said first and second registers in accordance with said second set of interpolation coefficients;
a second adder (113, 115) coupled to receive and add said second multiplicity of shifted and inverted digital samples to produce a second interpolated digital sample; and
a multiplexer (111) having first and second inputs respectively coupled to receive said first and second interpolated digital samples, said multiplexer outputting one of said first and second interpolated digital samples in response to a control signal from said delay control circuit (106).
21. A method of generating a time-delayed digital sample in an ultrasound beamformer (34) corresponding to a digital sample having a time delay which is a fraction of a sampling period, comprising the steps of:
acquiring first and second digital samples of an ultrasound receive signal in first and second sampling periods;
bit shifting and inverting said first and second digital samples in accordance with a first set of interpolation coefficients to produce a first multiplicity of bit shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second digital samples from first and second registers (102, 103) in accordance with said first set of interpolation coefficients;
adding said first multiplicity of bit shifted and inverted digital samples to produce a first interpolated digital sample;
bit shifting and inverting said first through fourth digital samples in accordance with a second set of interpolation coefficients to produce a second multiplicity of bit shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second digital samples from said first and second registers (102, 103) in accordance with said second set of interpolation coefficients;
adding said second multiplicity of bit shifted and inverted digital samples to produce a second interpolated digital sample; and
multiplexing (111) one of said first and second interpolated digital samples to an output.
22. A beamforming channel (35) comprising:
analog-to-digital conversion means(54) for outputting digital samples at a sampling rate;
a FIFO (101) having an input coupled to receive said digital samples and having an output;

- 24 -
first through N-th registers (102, 103, 104, 105) connected in series, said first register having an input coupled to said output of said FIFO (101) and having an output, and said N-th register having an input and an output;
an interpolator (107) having first through N-th inputs (IN1-IN4) respectively coupled to said outputs of said first through N-th registers; and
a delay control circuit (106) coupled to said FIFO (101), to said first through N-th registers and to said interpolator (107) for outputting delay signals which dynamically synchronously control the amount of delay of a signal passing through said FIFO, said registers and said interpolator (107), wherein said delay control circuit (106) comprises means for holding the contents of said first through N-th registers (102-105) to keep said outputs of said first through N-th registers synchronized with said output of said FIFO (101) following a change in the amount of delay provided by said FIFO.
23. The beamformer channel (35) as defined in claim 22, wherein said interpolator (107)
comprises:
first interpolation means (112, 116A-J) for generating a first interpolated digital sample as a function of outputs from said first through N-th registers into in accordance with a first set of interpolation coefficients;
second interpolation means (113, 116A-J) for converting the outputs of said first through N-th registers into a second interpolated digital sample in accordance with a second set of interpolation coefficients; and
a multiplexer (111) having first and second inputs respectively coupled to receive said first and second interpolated digital samples, said multiplexer outputting one of said first and second interpolated digital samples in response to a control signal from said delay control circuit (106).
24. The beamformer channel as defined in claim 22, wherein said first interpolation
means comprises means (112, 116A-J) for bit shifting the output of said first register as a
function of a first interpolation coefficient of said first set of interpolation coefficients.
25. The beamformer channel as defined in claim 24, wherein said first interpolation
means further comprises means (112, 116A-J) for inverting said bit-shifted output of said
first register as a function of said first interpolation coefficient of said first set of
interpolation coefficients.
26. The beamformer channel as defined in claim 22, wherein said first interpolation
means comprises:
means for bit shifting (112, 116A-J) the outputs of said first through N-th registers as a function of said first set of interpolation coefficients;
means for inverting (112, 116A-J) at least some of said bit-shifted outputs as a function of said first set of interpolation coefficients to produce a plurality of values; and
means (112, 115) for adding said values to produce said first interpolated digital sample.
27. The beamformer channel as defined in claim 26, wherein said adding.means (112,
115) comprises a Wallace tree adder.
Dated this 11th day of November, 1997

A phased array sector scanning ultrasonic system includes a separate receive channel for each respective element- in an ultrasonic transducer array. Each receive channel inparts at delay to the echo signal produced by each respective element* The delayed echo signals are summed to form a steered, dynamically focused and dynamically windowed receive beam even when the transmit beam does not emanate from the center of the array. The receiver has a beamformer including a multiplicity of beamformer channels 35% The beamformer dynamically increases delays to each channel without introducing unwanted discontinuities, by combing and synchronizing a FIFO and an interpolator. The interpolator uses "Wallace tree" adders to accumulate bit-shifted versions of the inputs. The number of additions is less than the number of bits which would be needed to represent equivalent coefficients. This reduces the hardware relative to a conventional implementation which incorporates multipliers with shifts and adds equaling the number of bits in the coefficients.

Documents:

02129-cal-1997-abstract.pdf

02129-cal-1997-claims.pdf

02129-cal-1997-correspondence.pdf

02129-cal-1997-description (complete).pdf

02129-cal-1997-drawings.pdf

02129-cal-1997-form-1.pdf

02129-cal-1997-form-2.pdf

02129-cal-1997-form-3.pdf

02129-cal-1997-form-5.pdf

02129-cal-1997-gpa.pdf

02129-cal-1997-priority document.pdf

2129-CAL-1997-FORM 27.pdf

2129-cal-1997-granted-abstract.pdf

2129-cal-1997-granted-assignment.pdf

2129-cal-1997-granted-claims.pdf

2129-cal-1997-granted-correspondence.pdf

2129-cal-1997-granted-description (complete).pdf

2129-cal-1997-granted-drawings.pdf

2129-cal-1997-granted-examination report.pdf

2129-cal-1997-granted-form 1.pdf

2129-cal-1997-granted-form 2.pdf

2129-cal-1997-granted-form 3.pdf

2129-cal-1997-granted-form 5.pdf

2129-cal-1997-granted-gpa.pdf

2129-cal-1997-granted-letter patent.pdf

2129-cal-1997-granted-others.pdf

2129-cal-1997-granted-pa.pdf

2129-cal-1997-granted-reply to examination report.pdf

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Patent Number

194519

Indian Patent Application Number

2129/CAL/1997

PG Journal Number

30/2009

Publication Date

24-Jul-2009

Grant Date

24-Jun-2005

Date of Filing

11-Nov-1997

Name of Patentee

GENERAL ELECTRIC COMPANY

Applicant Address

1 RIVER ROAD, SCHENECTADY, 12345 NEW YORK

Inventors:

#	Inventor's Name	Inventor's Address
1	STEVEN C. MILLER	W226 N2572 ASPENWOOD LANE,WAUKESHA,WISCONSIN 53186
2	GREGORY A. LILLEGARD	4068 SOUTH 43rd STREET #5,GREENFIELD,WISCONSIN 53220
3	DANIEL C. MILON	1671 NORTH PROSPECT AVENUE #309,MILWAUKEE,WISCONSIN 53205

PCT International Classification Number

G03B 42/06

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	08/774, 667	1996-12-30	U.S.A.