Title of Invention	" AN IMPROVED PROCESS FOR FABRICATION OF SILICON VARACTOR DIODES USEFUL FOR ELECTRONIC TUNING APPLICATIONS"
Abstract	The present invention relates to an improved process for fabrication of silicon varactor diodes useful for electronic tuning applications, and particularly relates to a simple planar process based on double ion-implantation, involving only a few processing steps for the fabrication of silicon varactor diodes. Silicon varactor diode is a semiconductor device which finds applications for electronic tuning in almost all areas of modem electronics. In conventional process minimum three oxidation step, four masks and four photolithography steps are required. In the present invention only two implantation steps, two masks and two photolithographic steps are required which improves device yield, and cost effective.

Title of Invention

" AN IMPROVED PROCESS FOR FABRICATION OF SILICON VARACTOR DIODES USEFUL FOR ELECTRONIC TUNING APPLICATIONS"

Abstract

The present invention relates to an improved process for fabrication of silicon varactor diodes useful for electronic tuning applications, and particularly relates to a simple planar process based on double ion-implantation, involving only a few processing steps for the fabrication of silicon varactor diodes. Silicon varactor diode is a semiconductor device which finds applications for electronic tuning in almost all areas of modem electronics. In conventional process minimum three oxidation step, four masks and four photolithography steps are required. In the present invention only two implantation steps, two masks and two photolithographic steps are required which improves device yield, and cost effective.

Full Text	The present invention relates to an improved process for fabrication of silicon varactor diodes useful for electronic tuning applications. The present invention particularly relates to a simple planar process based on double ion-iinplantation, involving only a few processing steps for the fabrication of silicon varactor diodes. Silicon varactor diode is a semicondutor device which find extesive applications for electronic tunning in almost all areas of modern electronics such as entertainment eletronics, space, communications and industrial electronics systems. For tuning applications more than one diode is used. It is therefore, desired that the specifications of the fabricated diodes are closely matched. The hitherto known processes to fabricate varactor diodes are double diffusion, multi-layer epitaxy, molecular beam epitaxy and ion-implantation or a suitable combination of these techniques. A silicon varactor diode for tuning applications requires large capacitance variation with externally applied voltage. This demands an appx'opiate impurity distribution of impurities in the device structure. In conventional double diffusion and implantation processes, a silicon wafer is oxidised and windows are open in it using a mask and photolithography. An appropriate impurity is then doped in the windows and a heat treatment is given to obtain a desired distribution of the impurity. The wafer is again oxidised and second photolithography is performed using second mask to open windows for formation of junction by doping an appropriate impurity. Now third oxidation and photolithography is done again to open contact windows. A thin film of a metal is deposited over the surface of the wafer followed by fourth photo¬lithography to delineate contacts on individual diode on the wafer. Thus all these coventional processes involves too many processing steps namely four photolithography, three oxidation and four masks. In conventional double diffusion process silicon wafers are heated in a diffusant environment. Atoms of the diffusant diffuse into silicon. Substjuently, a proper heat treatment is given to the wafers to obtain desired impurity profile. However, the process produces diodes with large spread in their capacitance and specifications. Therrore, the process is not suitable and cost effective for large scale production of the device. In epitaxial processes, a number of ultra thin layers of silicon of appropriate thicknes and conductivity are grown on the surface of a silicon wafer to achieve the desired impurity profile. Individual diodes on the wafer are seperated by chemical etching after deposition of contact metal film. A passivation layer is subsequently deposited to protect the devices. The epitaxial processes are usually very critical and are not based on silicon planar technology. The equipments used in epitaxy are complex and most of the gases used to grow layers are toxic. The critical processing and low throughput make this technique unsuitable for manufacturing the device. The main object of the present invention is to provide an improved process for the fabrication of silicon varactor diodes useful fox- electronic tuning applications which obviates the drawbacks of the hitherto known processes. Another object of the present invention is to provide a process which is economical as the number of processing steps are significantly i-educed. Still another object of the present invention is to provide a process which results in high process yield. Yet another object of the present invention is to provide a process for fabrication of diodes of matched specifications. Another object of the present invention is to provide a process which is simple and particularly suitable for manufacturing silicon diodes for electronic tuning applications. The improved process of the present invention is illustrated in Figs 1 to 10 of the drawings accompanying this specifications wherein : Fig.l is a pictorial view of a silicon epitaxial wafer.Layer (1) + is highly doped n -type substrate and layer (2) is epitaxial layer n-type. Fig.2 is a pictorial view of the wafer oxide growth (3). Fig.3 is a pictorial view of the wafer after opening diffusion windows (4) in oxide by photolithography and oxide etching. Fig.4 indicates phosphorus implantation (5) in the wafer. Fig.5 is a pictorial view of the wafer after phosphorus drive-in (5). Fig.6 indicates boron implantation (6) in the wafer. Fig.7 is a pictorial view of the wafer after boron drive-in (6) . Fig.8 is a view of the wafer after aluminium metallization (7). Fig.9 is a pictorial view of the wafer after defining contacts (8) by photolithography and aluminum etching. Fig. 10 is a picture of a cross-section of the device describing different layers of the processed wafer which are silicon dioxide (3), phosphorous doped layer (5), and boron doped layer (6) and aluminum contact (8). Accordingly the present invention provides an improved process for fabrication of silicon varactor diodes useful for electronic tuning applications which comprises, a) oxidation of silicon epitaxial wafer as herein described at a temperature in the range of 1050 to 1150°C for a period of 1.5 to 3 hours. b) opening of difftision windows in oxidised wafer using photolithography and etching, c) implantation of phosphorous in the said windows by conventional methods as herein described followed by heating the implanted wafer to a temperature in the range of 1000°C to 1150°C for a period of 60 to 90 minutes. d) implantation of boron in the phosphorous implanted windows by conventional methods followed by heating of the boron implanted wafer to a temperature in the range of 1000° to 1100°C for a period of 70 to 100 minutes, e) vacuum depositing aluminum metal on the surface of the boron implanted wafer in step (d), f) removing aluminum from unwanted areas other than the said windows through photolithography and aluminum etching, g) annealing the resultant wafer in an inert atmosphere to effect fabrication of silicon varactor diodes. The process of the present invention consists of the following basic steps: 1. Thermal oxidation of the epitaxial silicon wafer (n on n): Silicon wafers are thermally oxdised using conventional drywet-dry process i.e. by heating the wafers in dry-wet-dry oxygen ambient at a temperature in the range of 1150°C to 1050°C for a period of 1.5 to 3 hours to grow about 7500 A silicon-dioxide on the surface of the wafers. 2. First photolithography : to define windows in the oxide of the wafer for- phosphorus implantation. 3. Phophorus implantation : Phosphorous is implanted at a energy in the range of 80 to 120 KeV and a dose in the range of 1X10 cm to 5x10 cm . 4. Phosphorus drive-in : Implanted wafers are heated in a diffusion furnace at 1100°C to 1150°C for a period of 3 hours to 1.5 hours in argon or nitrogen inert gas atmosphere. 5. Boron implantation : Boron is implanted at a energy in the ange of 80 KeV to 100 KeV and a dose in the range of 1x1015 cm2 to 1X1016 cm2 . 6. Boi-on di-ive-in : Boron implanted wafers are heated at a temperature in the range of 1050°C to 1150°C for 50 to 80 minutes in nitrogen or argon ambient for 80 to 90 minutes to obtain a desired junction depth and zero voltage capacitance. 7. Aluminium metallization : A thin film of aluminium (approx. 8000 A° is deposited in a high vacuum (10-6 Torr.) evapo- ator on the surface of the wafers. 8. Second photolithography : to define aluminium contacts. In this process step aluminium is r^etained on the windows and it is removed from unwanted region by etching in an aluminium etchant based on phosphoric acid or any other suitable etching solution. 9. Annealing : The wafers are heated in a furnace at a temperature in the range of 420 C to 460 C for 20 to 30 minutes in nitrogen or forming gas flow for aluminium alloying with silicon. In the process of the present invention, n/n+ silicon epitaxial wafers are used to fabricate silicon varactor diodes for electronic tuning applications. The wafers are oxidised by heating in oxygen atmosphere to grow a layer of silicondioxide on its surface. The oxidised wafers are coated with a photo¬sensitive material called photoresist and exposed to ultra-violet light through a mask containing opaque and transparent areas. This step is known as photolithography. The wafer^s are then subjected to chemical etching using hydroflouric acid to open windows in oxide on the wafer surface. Phosphorous is then implanted in the windows and implanted wafers are heated in an inert gas at an appropriate temperature for approprate time to drive-in the phosphorous atoms into the silicon to a desired depth. Subsiquently boron is implanteolin the windowspnd the implanted wafers are heated again in an inert gas at an appropriate temperature for appropriate time to drive-in boron atoms to obtain desired junction depth. Then aluminium metal is vacuum deposited. Then second photolithography and etching is done to remove aluminium from unwanted areas. Finally the wafers are subjected to a heat treatment in an inert gas ambient at an appr-opriate temperature to anneal the metal to accomplish the fabrication of diodes. The process of the present invention as described above is a simple process based on only two ion-implantation. The process employs only one oxidation, two masks, two photolithograpy steps compared to three oxidation, four masks and four photolithography steps involved in the conventional processes. Since the process of the present invention employs implantation for doping impurities into silicon, the process yield is high and specifications of all diodes fabricated on the wafers are highly uniform. Therefore, the process is capable of producing diodes of matched capacitance variation and equal breakdown voltages. Thus the process of the present invention is cost effective and suitable for mass production. The following example is given by way of illustration of the present invention and should not be construed to limit the scope of the present invention. Example 1: Following process steps are followed to fabricate silicon varactor diodes for application in TV tuners. 1. Thermal oxidation of the epitaxial silicon wafer (n on n+) : Silicon wafers are oxidised using conventional dry-wet-dry o o oxidation process at 1050 C for 3 hours to grow about 7500 A silicon-dioxide on the surface of the wafers. 2. First photolithography : to define windows in the oxide of the wafer for phosphorus implantation. 3. Phophorus implantation : at 120 KeV and a dose of 5x1014 cm2. 4. Phosphorus drive-in : Implanted wafers are heated in a diffusion furnace at 1150°C for about 80 minutes in an inert gas atmosphere. 5. Boron implantation : at 80 KeV and a dose of about 7x1015 6. Boron drive-in : Bor^on implanted wafers are heated at 1100 C for 85 minutes to obtain a desired junction depth and zero voltage capacitance. 7. Aluminium metallization : A thin film of aluminium (approx. 8000 A° is deposited in a high vacuum (10-6 Terr.) evapo- ator on the surface of the wafers. 8. Second photolithography : to define aluminium contacts. In this process step aluminium is retained on the windows and it is removed from unwanted region by etching in an aluminium etchant based on phosphoric acid or any other suitable etching solution. o 9. Annealing : The wafers are heated in a furnace at 450 C for 20 minutes in an inert gas flow for alloying contact aluminium with silicon. The above pi-ocess produced diodes of following specifications : (i) Capacitance ratio i.e. the ratio of capacitance at applied voltage of 3 volts [ C(3) 1 to that at 25 volts [ C(25) ] i.e. C(3)/C(25) is more than 4. (ii) Break down voltage > 30 Volts. (iii) Leakage current These diodes were tested in an electronic tuner for TV tuning application. The diodes were packaged in TO-92 plastic packages and three diodes were used in a TV tuner. Gain of 38 db to 23 db was obtained for tuning channels 2 to 12 of colour TV transmission. Five batches of six wafers each and each two inch diameter wafer containing about 20,000 diodes were processed. The yield above 95 % was estimated from the batches so produced of these devices. The capacitance unifomity among diodes fabricated on a wafer is better than 10 % at different bias voltages. The deviation in capacitance uniformity on different wafers or batches is extremely small. The capacitance ratio [ C(3)/C{25) ] uniformity among the diodes is also better than 10 % - The process is highly reproducible, repeatable and cost effective thereby most suitable for high volume production. The above example suggests that the process of present invention gives high yield and diodes of matched specifications for tuning applications. Therefore, the novelty of the invented process is that it pi'ovides diodes of high capacitance uniformity with high yield. Fui'ther, a special feature of the process of the present invention is that by adjusting just one parameter i.e. the junction depth at the time of boron drive-in the diodes of different capacitance variation oi other specifications for other tuning applications can be fabricated. Thus the process is capable of manufacturing a family of diodes suitable for a variety of tuning applications. The main advantages of the process of the present invention are that : (1) This is a simple planar process, employing conventioaial processing equipments and technology, (2) Although two implantation steps are involved to complete the fabrication of the devices only one oxidation Is employed in comparison to the requirements of minimum three oxidation steps in the conventional technologYr (3) Only two masks and two photolithographic steps are needed as compared to four masks and four photolithography in case of the conventional methods, (4) Owing to use of implantation in the process, the capacitance uniformity of the diodes on the wafer and from wafer to wafer is high, (5) Device yield, repeatibility and reproducibility of the process is very high, as the process is based on ion-implantation, (6) It is a cost effective process as device yield and capacitance uniformity among the diodes are very high, and (7) It is a planar process so readily suitable for high volume production, We Claim: 1. An improved process for fabrication of silicon varactor diodes useful for electronic tuning applications which comprises, a) oxidation of silicon epitaxial wafer as herein described at a temperature in the range of 1050 to 1150°C for a period of 1.5 to 3 hours. b) opening of diffusion windows in oxidised wafer using photolithography and etching, c) implantation of phosphorous in the said windows by conventional methods as herein described followed by heating the implanted wafer to a temperature in the range of 1000 to 1150°C for a period of 60 to 90 minutes. d) implantation of boron in the phosphorous implanted windows by conventional methods followed by heating of the boron implanted wafer to a temperature in the range of 1000 to 1100°C for a penod of 70 to 100 minutes, e) vacuum depositing aluminum metal on the surface of the boron implanted wafer in step (d), f) removing aluminum from unwanted areas other than the said windows through photolithography and aluminum etching, g) annealing the resultant wafer in an inert atmosphere to effect fabrication of silicon varactor diodes. 2. An improved process as claimed in claim in 1 wherein the silicon epitaxial wafer used is such as n on n. 3. An improved process as claimed in claim in 1 and 2 wherein the phosphorous implantation is effected at a energy in the range of 80 to 120 KeV and a dose in the range of 1X1014 cm2 to 5x1014 cm2. 4. An improved process as claimed in claim in 1 to 3 wherein the boron implantation is effected at a energy in the range of 80 KeV to 100 KeV and a dose in the range of 1x1015cm2 to lx1016 cm2 5. An improved process as claimed in claim in 1 to 4 wherein the vacuum deposition of aluminum is effected in a vacuum evaporator at a vacuum higher than 10" Torr. 6. An improved process as claimed in claims 1 to 5 wherein the aluminum etching is effected using an aluminum etchant such as based on phosphoric acid or any other suitable etching solution. 7. An improved process as claimed in claims 1 to 6 wherein the annealing is effected in a furnace at a temperature in the range of 420 to 460°C for 20 to 30 minutes in nitrogen or forming gas flow. 8. An improved process for fabrication of silicon varactor diodes useful for electronic tuning application substantially as herein described with reference to the example and the drawings accompanying this specification.

Full Text

The present invention relates to an improved process for fabrication of silicon varactor diodes useful for electronic tuning applications. The present invention particularly relates to a simple planar process based on double ion-iinplantation, involving only a few processing steps for the fabrication of silicon varactor diodes.
Silicon varactor diode is a semicondutor device which find extesive applications for electronic tunning in almost all areas of modern electronics such as entertainment eletronics, space, communications and industrial electronics systems. For tuning applications more than one diode is used. It is therefore, desired that the specifications of the fabricated diodes are closely matched.
The hitherto known processes to fabricate varactor diodes are double diffusion, multi-layer epitaxy, molecular beam epitaxy and ion-implantation or a suitable combination of these techniques. A silicon varactor diode for tuning applications requires large capacitance variation with externally applied voltage. This demands an appx'opiate impurity distribution of impurities in the device structure. In conventional double diffusion and implantation processes, a silicon wafer is oxidised and windows are open in it using a mask and photolithography. An appropriate impurity is then doped in the windows and a heat treatment is given to obtain a desired distribution of the impurity. The wafer is again oxidised and second photolithography is performed using second mask to open windows for formation of junction by doping an appropriate impurity. Now third oxidation and photolithography

is done again to open contact windows. A thin film of a metal is deposited over the surface of the wafer followed by fourth photo¬lithography to delineate contacts on individual diode on the wafer. Thus all these coventional processes involves too many processing steps namely four photolithography, three oxidation and four masks. In conventional double diffusion process silicon wafers are heated in a diffusant environment. Atoms of the diffusant diffuse into silicon. Substjuently, a proper heat treatment is given to the wafers to obtain desired impurity
profile. However, the process produces diodes with large spread
in their capacitance and specifications. Therrore, the process is
not suitable and cost effective for large scale production of the
device. In epitaxial processes, a number of ultra thin layers of
silicon of appropriate thicknes and conductivity are grown on
the surface of a silicon wafer to achieve the desired impurity
profile. Individual diodes on the wafer are seperated by
chemical etching after deposition of contact metal film. A
passivation layer is subsequently deposited to protect the
devices. The epitaxial processes are usually very critical and
are not based on silicon planar technology. The equipments used
in epitaxy are complex and most of the gases used to grow layers
are toxic. The critical processing and low throughput make this
technique unsuitable for manufacturing the device.
The main object of the present invention is to provide an improved process for the fabrication of silicon varactor diodes useful fox- electronic tuning applications which obviates the drawbacks of the hitherto known processes. Another object of the

present invention is to provide a process which is economical as the number of processing steps are significantly i-educed. Still another object of the present invention is to provide a process which results in high process yield. Yet another object of the present invention is to provide a process for fabrication of diodes of matched specifications. Another object of the present invention is to provide a process which is simple and particularly suitable for manufacturing silicon diodes for electronic tuning applications.
The improved process of the present invention is illustrated in
Figs 1 to 10 of the drawings accompanying this specifications
wherein :
Fig.l is a pictorial view of a silicon epitaxial wafer.Layer (1)
+ is highly doped n -type substrate and layer (2) is
epitaxial layer n-type. Fig.2 is a pictorial view of the wafer oxide growth (3). Fig.3 is a pictorial view of the wafer after opening diffusion
windows (4) in oxide by photolithography and oxide
etching. Fig.4 indicates phosphorus implantation (5) in the wafer. Fig.5 is a pictorial view of the wafer after phosphorus
drive-in (5). Fig.6 indicates boron implantation (6) in the wafer. Fig.7 is a pictorial view of the wafer after boron drive-in
(6) . Fig.8 is a view of the wafer after aluminium metallization (7). Fig.9 is a pictorial view of the wafer after defining contacts

(8) by photolithography and aluminum etching.
Fig. 10 is a picture of a cross-section of the device describing different layers of the processed wafer which are silicon dioxide (3), phosphorous doped layer (5), and boron doped layer (6) and aluminum contact (8).
Accordingly the present invention provides an improved process for fabrication of silicon varactor diodes useful for electronic tuning applications which comprises,
a) oxidation of silicon epitaxial wafer as herein described at a temperature in the range of 1050 to 1150°C for a period of 1.5 to 3 hours.
b) opening of difftision windows in oxidised wafer using photolithography and etching,
c) implantation of phosphorous in the said windows by conventional methods as herein described followed by heating the implanted wafer to a temperature in the range of 1000°C to 1150°C for a period of 60 to 90 minutes.
d) implantation of boron in the phosphorous implanted windows by conventional methods followed by heating of the boron implanted wafer to a temperature in the range of 1000° to 1100°C for a period of 70 to 100 minutes,
e) vacuum depositing aluminum metal on the surface of the boron implanted wafer in step (d),
f) removing aluminum from unwanted areas other than the said windows through photolithography and aluminum etching,
g) annealing the resultant wafer in an inert atmosphere to effect fabrication of silicon varactor diodes.
The process of the present invention consists of the following basic steps:
1. Thermal oxidation of the epitaxial silicon wafer (n on n): Silicon wafers are thermally oxdised using conventional drywet-dry process i.e. by heating the wafers in dry-wet-dry oxygen ambient at a temperature in the range of 1150°C to
1050°C for a period of 1.5 to 3 hours to grow about 7500 A silicon-dioxide on the surface of the wafers.
2. First photolithography : to define windows in the oxide of the wafer for- phosphorus implantation.
3. Phophorus implantation : Phosphorous is implanted at a energy
in the range of 80 to 120 KeV and a dose in the range of

1X10 cm to 5x10 cm .
4. Phosphorus drive-in : Implanted wafers are heated in a

diffusion furnace at 1100°C to 1150°C for a period of 3 hours
to 1.5 hours in argon or nitrogen inert gas atmosphere.
5. Boron implantation : Boron is implanted at a energy in the

ange of 80 KeV to 100 KeV and a dose in the range of 1x1015

cm2 to 1X1016 cm2 .
6. Boi-on di-ive-in : Boron implanted wafers are heated at a

temperature in the range of 1050°C to 1150°C for 50 to 80
minutes in nitrogen or argon ambient for 80 to 90 minutes to
obtain a desired junction depth and zero voltage capacitance.
7. Aluminium metallization : A thin film of aluminium (approx.

8000 A° is deposited in a high vacuum (10-6 Torr.) evapo-
ator on the surface of the wafers.
8. Second photolithography : to define aluminium contacts. In this process step aluminium is r^etained on the windows and it is removed from unwanted region by etching in an aluminium etchant based on phosphoric acid or any other suitable etching solution.
9. Annealing : The wafers are heated in a furnace at a

temperature in the range of 420 C to 460 C for 20 to 30
minutes in nitrogen or forming gas flow for aluminium alloying with silicon.
In the process of the present invention, n/n+ silicon epitaxial
wafers are used to fabricate silicon varactor diodes for electronic tuning applications. The wafers are oxidised by heating in oxygen atmosphere to grow a layer of silicondioxide on its surface. The oxidised wafers are coated with a photo¬sensitive material called photoresist and exposed to ultra-violet light through a mask containing opaque and transparent areas. This step is known as photolithography. The wafer^s are then subjected to chemical etching using hydroflouric acid to open windows in oxide on the wafer surface. Phosphorous is then implanted in the windows and implanted wafers are heated in an inert gas at an appropriate temperature for approprate time to drive-in the phosphorous atoms into the silicon to a desired depth. Subsiquently boron is implanteolin the windowspnd the implanted wafers are heated again in an inert gas at an appropriate temperature for appropriate time to drive-in boron atoms to obtain desired junction depth. Then aluminium metal is vacuum deposited. Then second photolithography and etching is done to remove aluminium from unwanted areas. Finally the wafers are subjected to a heat treatment in an inert gas ambient at an appr-opriate temperature to anneal the metal to accomplish the fabrication of diodes.
The process of the present invention as described above is a simple process based on only two ion-implantation. The process employs only one oxidation, two masks, two photolithograpy steps
compared to three oxidation, four masks and four photolithography

steps involved in the conventional processes. Since the process of the present invention employs implantation for doping impurities into silicon, the process yield is high and specifications of all diodes fabricated on the wafers are highly uniform. Therefore, the process is capable of producing diodes of matched capacitance variation and equal breakdown voltages. Thus the process of the present invention is cost effective and suitable for mass production.
The following example is given by way of illustration of the present invention and should not be construed to limit the scope of the present invention.
Example 1: Following process steps are followed to fabricate silicon varactor diodes for application in TV tuners.

1. Thermal oxidation of the epitaxial silicon wafer (n on n+) :
Silicon wafers are oxidised using conventional dry-wet-dry
o o
oxidation process at 1050 C for 3 hours to grow about 7500 A
silicon-dioxide on the surface of the wafers.
2. First photolithography : to define windows in the oxide of
the wafer for phosphorus implantation.

3. Phophorus implantation : at 120 KeV and a dose of 5x1014 cm2.
4. Phosphorus drive-in : Implanted wafers are heated in a
diffusion furnace at 1150°C for about 80 minutes in an inert
gas atmosphere.

5. Boron implantation : at 80 KeV and a dose of about 7x1015
6. Boron drive-in : Bor^on implanted wafers are heated at 1100 C for 85 minutes to obtain a desired junction depth and zero voltage capacitance.
7. Aluminium metallization : A thin film of aluminium (approx.

8000 A° is deposited in a high vacuum (10-6 Terr.) evapo-
ator on the surface of the wafers.
8. Second photolithography : to define aluminium contacts. In
this process step aluminium is retained on the windows and
it is removed from unwanted region by etching in an aluminium
etchant based on phosphoric acid or any other suitable
etching solution.
o
9. Annealing : The wafers are heated in a furnace at 450 C for
20 minutes in an inert gas flow for alloying contact
aluminium with silicon. The above pi-ocess produced diodes of following specifications : (i) Capacitance ratio i.e. the ratio of capacitance at applied voltage of 3 volts [ C(3) 1 to that at 25 volts [ C(25) ] i.e. C(3)/C(25) is more than 4. (ii) Break down voltage > 30 Volts. (iii) Leakage current These diodes were tested in an electronic tuner for TV tuning application. The diodes were packaged in TO-92 plastic packages and three diodes were used in a TV tuner. Gain of 38 db to 23 db was obtained for tuning channels 2 to 12 of colour TV transmission. Five batches of six wafers each and each two inch diameter wafer containing about 20,000 diodes were processed. The
yield above 95 % was estimated from the batches so produced of these devices. The capacitance unifomity among diodes fabricated on a wafer is better than 10 % at different bias voltages. The deviation in capacitance uniformity on different wafers or batches is extremely small. The capacitance ratio [ C(3)/C{25) ] uniformity among the diodes is also better than 10 % - The process is highly reproducible, repeatable and cost effective thereby most suitable for high volume production.
The above example suggests that the process of present invention gives high yield and diodes of matched specifications for tuning applications. Therefore, the novelty of the invented process is that it pi'ovides diodes of high capacitance uniformity with high yield. Fui'ther, a special feature of the process of the present invention is that by adjusting just one parameter i.e. the junction depth at the time of boron drive-in the diodes of different capacitance variation oi other specifications for other tuning applications can be fabricated. Thus the process is capable of manufacturing a family of diodes suitable for a variety of tuning applications.
The main advantages of the process of the present invention are that :
(1) This is a simple planar process, employing conventioaial processing equipments and technology,
(2) Although two implantation steps are involved to complete the fabrication of the devices only one oxidation Is employed in comparison to the requirements of minimum three oxidation
steps in the conventional technologYr
(3) Only two masks and two photolithographic steps are needed as compared to four masks and four photolithography in case of the conventional methods,
(4) Owing to use of implantation in the process, the capacitance uniformity of the diodes on the wafer and from wafer to wafer is high,
(5) Device yield, repeatibility and reproducibility of the process is very high, as the process is based on ion-implantation,
(6) It is a cost effective process as device yield and capacitance uniformity among the diodes are very high, and
(7) It is a planar process so readily suitable for high volume production,

We Claim:
1. An improved process for fabrication of silicon varactor diodes useful for
electronic tuning applications which comprises,
a) oxidation of silicon epitaxial wafer as herein described at a temperature in the range of 1050 to 1150°C for a period of 1.5 to 3 hours.
b) opening of diffusion windows in oxidised wafer using photolithography and etching,
c) implantation of phosphorous in the said windows by conventional methods as herein described followed by heating the implanted wafer to a temperature in the range of 1000 to 1150°C for a period of 60 to 90 minutes.
d) implantation of boron in the phosphorous implanted windows by conventional methods followed by heating of the boron implanted wafer to a temperature in the range of 1000 to 1100°C for a penod of 70 to 100 minutes,
e) vacuum depositing aluminum metal on the surface of the boron implanted wafer in step (d),
f) removing aluminum from unwanted areas other than the said windows through photolithography and aluminum etching,
g) annealing the resultant wafer in an inert atmosphere to effect fabrication of silicon varactor diodes.
2. An improved process as claimed in claim in 1 wherein the silicon epitaxial wafer used is such as n on n.
3. An improved process as claimed in claim in 1 and 2 wherein the phosphorous implantation is effected at a energy in the range of 80 to 120 KeV and a dose in the range of 1X1014 cm2 to 5x1014 cm2.
4. An improved process as claimed in claim in 1 to 3 wherein the boron implantation is effected at a energy in the range of 80 KeV to 100 KeV and a dose in the range of 1x1015cm2 to lx1016 cm2
5. An improved process as claimed in claim in 1 to 4 wherein the vacuum deposition of aluminum is effected in a vacuum evaporator at a vacuum higher than 10" Torr.
6. An improved process as claimed in claims 1 to 5 wherein the aluminum etching is effected using an aluminum etchant such as based on phosphoric acid or any other suitable etching solution.
7. An improved process as claimed in claims 1 to 6 wherein the annealing is effected in a furnace at a temperature in the range of 420 to 460°C for 20 to 30 minutes in nitrogen or forming gas flow.
8. An improved process for fabrication of silicon varactor diodes useful for electronic tuning application substantially as herein described with reference to the example and the drawings accompanying this specification.

Documents:

1266-del-1997-abstract.pdf

1266-del-1997-claims.pdf

1266-del-1997-correspondence-others.pdf

1266-del-1997-correspondence-po.pdf

1266-del-1997-description (complete).pdf

1266-del-1997-drawings.pdf

1266-del-1997-form-1.pdf

1266-del-1997-form-19.pdf

1266-del-1997-form-2.pdf

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Patent Number

194357

Indian Patent Application Number

1266/DEL/1997

PG Journal Number

43/2004

Publication Date

23-Oct-2004

Grant Date

10-Feb-2006

Date of Filing

13-May-1997

Name of Patentee

COUNCIL OF SCIENTIFIC AND INDUSRIAL RESEARCH

Applicant Address

RAFI MARG NEW DELHI-110001, INDIA

Inventors:

#	Inventor's Name	Inventor's Address
1	PURUSHOTTAM DAS VYAS	CENTRAL ELECTRONICS ENGINEERING RESEARCH INSTITUTE,PILANI-333031, INDIA
2	RAM PRATAP GUPTA	CENTRAL ELECTRONICS ENGINEERING RESEARCH INSTITUTE,PILANI-333031, INDIA
3	DWARKA PRASAD RUNTHALA	CENTRAL ELECTRONICS ENGINEERING RESEARCH INSTITUTE,PILANI-333031, INDIA

PCT International Classification Number

H01L 25/00

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA